From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751820AbeANPl2 (ORCPT + 1 other); Sun, 14 Jan 2018 10:41:28 -0500 Received: from mail.skyhub.de ([5.9.137.197]:39980 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751505AbeANPl1 (ORCPT ); Sun, 14 Jan 2018 10:41:27 -0500 Date: Sun, 14 Jan 2018 16:41:08 +0100 From: Borislav Petkov To: Tom Lendacky Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Rik van Riel , Andi Kleen , Josh Poimboeuf , Peter Zijlstra , Linus Torvalds , Jiri Kosina , Dan Williams , Dave Hansen , Andy Lutomirski , Kees Cook , Thomas Gleixner , Tim Chen , Greg Kroah-Hartman , David Woodhouse , Paul Turner Subject: Re: [PATCH v2] x86/retpoline: Add LFENCE to the retpoline/RSB filling RSB macros Message-ID: <20180114154108.3og4oqascfawy4oe@pd.tnic> References: <20180113232730.31060.36287.stgit@tlendack-t1.amdoffice.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20180113232730.31060.36287.stgit@tlendack-t1.amdoffice.net> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Sat, Jan 13, 2018 at 05:27:30PM -0600, Tom Lendacky wrote: > The PAUSE instruction is currently used in the retpoline and RSB filling > macros as a speculation trap. The use of PAUSE was originally suggested > because it showed a very, very small difference in the amount of > cycles/time used to execute the retpoline as compared to LFENCE. On AMD, > the PAUSE instruction is not a serializing instruction, so the pause/jmp > loop will use excess power as it is speculated over waiting for return > to mispredict to the correct target. > > The RSB filling macro is applicable to AMD, and, if software is unable to > verify that LFENCE is serializing on AMD (possible when running under a > hypervisor), the generic retpoline support will be used and, so, is also > applicable to AMD. Keep the current usage of PAUSE for Intel, but add an > LFENCE instruction to the speculation trap for AMD. > > Signed-off-by: Tom Lendacky > --- > arch/x86/include/asm/nospec-branch.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) Reviewed-by: Borislav Petkov -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.