From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751140AbeAVLdG (ORCPT ); Mon, 22 Jan 2018 06:33:06 -0500 Received: from foss.arm.com ([217.140.101.70]:57406 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751058AbeAVLdE (ORCPT ); Mon, 22 Jan 2018 06:33:04 -0500 Date: Mon, 22 Jan 2018 11:33:11 +0000 From: Will Deacon To: Jayachandran C Cc: Jon Masters , marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, ard.biesheuvel@linaro.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, labbott@redhat.com, christoffer.dall@linaro.org Subject: Re: [PATCH v3 1/2] arm64: Branch predictor hardening for Cavium ThunderX2 Message-ID: <20180122113311.GB15456@arm.com> References: <20180118135354.GB20783@arm.com> <1516364568-95577-1-git-send-email-jnair@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1516364568-95577-1-git-send-email-jnair@caviumnetworks.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 19, 2018 at 04:22:47AM -0800, Jayachandran C wrote: > Use PSCI based mitigation for speculative execution attacks targeting > the branch predictor. We use the same mechanism as the one used for > Cortex-A CPUs, we expect the PSCI version call to have a side effect > of clearing the BTBs. > > Signed-off-by: Jayachandran C > --- > arch/arm64/kernel/cpu_errata.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 70e5f18..45ff9a2 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -338,6 +338,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT, > MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), > }, > + { > + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, > + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), > + .enable = enable_psci_bp_hardening, > + }, > + { > + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, > + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), > + .enable = enable_psci_bp_hardening, > + }, > #endif Thanks. Acked-by: Will Deacon Will