From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x226kqeY4pmu4e+YdmfnDGnKVW9hsxBo+lfa0yAKNCpQXq12p7evEwEzZoaDer2f1G8+sB+v1 ARC-Seal: i=1; a=rsa-sha256; t=1516747180; cv=none; d=google.com; s=arc-20160816; b=o2Q2Wt9XJZ8MaQhR99f4dmmCbkbXioICtZRFOqdOcgKBw+YZdDnvxMKkc5prQcxdCG NIj7VHzLqd2ZQIgygQ2YYd4NpdTjFP0JuRxkuytgpJauWz8wTzJJghOV56ivi3AEB0zm +5DGw9/In7DjraHBab/8fjMT5M6CRaL9ckpshQqs+4SpROCpzp1FLXjjdIFaFH2uvU+V PceWuBUrEIHJCt6Bi+XQombGesArpoUnMWTsq0uoiN2W0+IpmtITFp1CDwoOBsFuKDJV KST+J65O5KNxyKwfVMTMQwh2a7NSKpHIiGKLHmuA1Ks1SIEV5d0M0K2XAsQg832JD9S2 fZCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=MQbENMPeC+3MwXZOdWHsmL2HXUD0DAjjN9XbIFEJdJg=; b=dyIYjqbGqUrigZOwQ+GOZT2CXgoU8GEeKupJw9qn/QM1QaPelR/U0LyEjM//o+ND24 MoREhBdvYAzKUIc9330Y+vftxnpEdBwEhLKMVCCFqVsKhyFPOf/MqydJ6OlApPUDZTFt AS+UoELO2ZGl9fn2RmP2Qd+yENDBSHIE1/y2lSQ1cSG6T26ufyNf+nnFWu44OrG5HBVD p7FSEx0Dy/h5gKvOeI5uSqtiCIuuna8WVtNjWlAgYcGLlEQ7S+bS32DOy3luUlyulDKH bkecKpUfc2pjyrHZc8OAxiMfMP/vtRMIp9h2ugYCcXEtzugaGPD+byeXlwbOhzF3h1bn Umrg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of ak@linux.intel.com designates 192.55.52.88 as permitted sender) smtp.mailfrom=ak@linux.intel.com Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of ak@linux.intel.com designates 192.55.52.88 as permitted sender) smtp.mailfrom=ak@linux.intel.com X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,403,1511856000"; d="scan'208";a="168602366" From: Andi Kleen To: tglx@linutronix.de Cc: dwmw@amazon.co.uk, thomas.lendacky@amd.com, peterz@infradead.org, torvalds@linux-foundation.org, luto@amacapital.net, x86@kernel.org, gregkh@linux-foundation.org, linux-kernel@vger.kernel.org, Andi Kleen Subject: [PATCH 1/2] x86/retpoline: Add feature bit for additional return buffer protections Date: Tue, 23 Jan 2018 14:39:15 -0800 Message-Id: <20180123223916.26904-2-andi@firstfloor.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180123223916.26904-1-andi@firstfloor.org> References: <20180123223916.26904-1-andi@firstfloor.org> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590424691949140463?= X-GMAIL-MSGID: =?utf-8?q?1590424691949140463?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Andi Kleen On Skylake we want additional protections against spectre_v2 over the normal RETPOLINE against underflowing return buffers. On return buffer underflow the CPU could fall back to the poisoned indirect branch predictor. This patch adds a feature bit, only enabled on Skylake, to enable additional return buffer underflow protections This will be used in the next patches Signed-off-by: Andi Kleen --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/bugs.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 25b9375c1484..85108eb1876b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -211,6 +211,7 @@ #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ +#define X86_FEATURE_RSB_UNDERFLOW ( 7*32+20) /* Avoid return stack underflows */ /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 390b3dc3d438..68d449d51673 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -249,6 +249,11 @@ static void __init spectre_v2_select_mitigation(void) setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); pr_info("Filling RSB on context switch\n"); } + + if (is_skylake_era()) { + setup_force_cpu_cap(X86_FEATURE_RSB_UNDERFLOW); + pr_info("Enabling return buffer underflow protections"); + } } #undef pr_fmt -- 2.14.3