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Tue, 23 Jan 2018 23:44:56 -0500 Received: from mail-sn1nam01on0139.outbound.protection.outlook.com ([104.47.32.139]:26809 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932626AbeAXEQq (ORCPT ); Tue, 23 Jan 2018 23:16:46 -0500 From: Sasha Levin To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" CC: Juergen Gross , Thomas Gleixner , "xen-devel@lists.xenproject.org" , "boris.ostrovsky@oracle.com" , Sasha Levin Subject: [PATCH AUTOSEL for 4.14 098/100] x86/xen: Support early interrupts in xen pv guests Thread-Topic: [PATCH AUTOSEL for 4.14 098/100] x86/xen: Support early interrupts in xen pv guests Thread-Index: AQHTlMnwTFaHU41nXkShIkgK/xWPCw== Date: Wed, 24 Jan 2018 04:15:17 +0000 Message-ID: <20180124041414.32065-98-alexander.levin@microsoft.com> References: <20180124041414.32065-1-alexander.levin@microsoft.com> In-Reply-To: <20180124041414.32065-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR2101MB0727;7:GUT+WBK5p18EP/31lD3f3uyxFlS2M5ns7cMEbTzHVIjp4qABy1Mpv6WMP+LLVfTBBkI5MdChLGRGd35zA6/XsBFd7Ap80zCK3Ku83m4pfS0I9qnnz2Dc7yt6cAsOA+uxuSSSY9EEsewKHQNOwfnpQRGEpcF+CpBIWyy4rfWZVt3oMc0Ii+lonATA5sVXvvDDuvXkUpxOJHJVcCTOfA6bdDEza0HZu/Luyml+2nZgamapldJQmzsDuy1Vxgdnfu+/ x-ms-office365-filtering-correlation-id: e349ab20-ea12-46ed-590f-08d562e144fc x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(5600026)(4604075)(3008032)(4534165)(4627221)(201703031133081)(201702281549075)(48565401081)(2017052603307)(7193020);SRVR:DM5PR2101MB0727; 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authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alexander.Levin@microsoft.com; x-microsoft-antispam-message-info: l3aHR/JY/FHC5uUefziwjhWqEYDEKeNrQQmfGMgg3rPmX9DkMjDLczo+/XuTs+ZLSXVLtMvOMHOX7CXtkqpyYw== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: e349ab20-ea12-46ed-590f-08d562e144fc X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jan 2018 04:15:17.0561 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB0727 Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Juergen Gross [ Upstream commit 42b3a4cb5609de757f5445fcad18945ba9239a07 ] Add early interrupt handlers activated by idt_setup_early_handler() to the handlers supported by Xen pv guests. This will allow for early WARN() calls not crashing the guest. Suggested-by: Andy Lutomirski Signed-off-by: Juergen Gross Signed-off-by: Thomas Gleixner Cc: xen-devel@lists.xenproject.org Cc: boris.ostrovsky@oracle.com Link: https://lkml.kernel.org/r/20171124084221.30172-1-jgross@suse.com Signed-off-by: Sasha Levin --- arch/x86/include/asm/segment.h | 12 ++++++++++++ arch/x86/mm/extable.c | 4 +++- arch/x86/xen/enlighten_pv.c | 37 ++++++++++++++++++++++++------------- arch/x86/xen/xen-asm_64.S | 14 ++++++++++++++ 4 files changed, 53 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.= h index b20f9d623f9c..8f09012b92e7 100644 --- a/arch/x86/include/asm/segment.h +++ b/arch/x86/include/asm/segment.h @@ -236,11 +236,23 @@ */ #define EARLY_IDT_HANDLER_SIZE 9 =20 +/* + * xen_early_idt_handler_array is for Xen pv guests: for each entry in + * early_idt_handler_array it contains a prequel in the form of + * pop %rcx; pop %r11; jmp early_idt_handler_array[i]; summing up to + * max 8 bytes. + */ +#define XEN_EARLY_IDT_HANDLER_SIZE 8 + #ifndef __ASSEMBLY__ =20 extern const char early_idt_handler_array[NUM_EXCEPTION_VECTORS][EARLY_IDT= _HANDLER_SIZE]; extern void early_ignore_irq(void); =20 +#if defined(CONFIG_X86_64) && defined(CONFIG_XEN_PV) +extern const char xen_early_idt_handler_array[NUM_EXCEPTION_VECTORS][XEN_E= ARLY_IDT_HANDLER_SIZE]; +#endif + /* * Load a segment. Fall back on loading the zero segment if something goes * wrong. This variant assumes that loading zero fully clears the segment= . diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 30bc4812ceb8..9fe656c42aa5 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -1,6 +1,7 @@ #include #include #include +#include =20 #include #include @@ -212,8 +213,9 @@ void __init early_fixup_exception(struct pt_regs *regs,= int trapnr) * Old CPUs leave the high bits of CS on the stack * undefined. I'm not sure which CPUs do this, but at least * the 486 DX works this way. + * Xen pv domains are not using the default __KERNEL_CS. */ - if (regs->cs !=3D __KERNEL_CS) + if (!xen_pv_domain() && regs->cs !=3D __KERNEL_CS) goto fail; =20 /* diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index ae3a071e1d0f..899a22a02e95 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -622,7 +622,7 @@ static struct trap_array_entry trap_array[] =3D { { simd_coprocessor_error, xen_simd_coprocessor_error, false }, }; =20 -static bool get_trap_addr(void **addr, unsigned int ist) +static bool __ref get_trap_addr(void **addr, unsigned int ist) { unsigned int nr; bool ist_okay =3D false; @@ -644,6 +644,14 @@ static bool get_trap_addr(void **addr, unsigned int is= t) } } =20 + if (nr =3D=3D ARRAY_SIZE(trap_array) && + *addr >=3D (void *)early_idt_handler_array[0] && + *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { + nr =3D (*addr - (void *)early_idt_handler_array[0]) / + EARLY_IDT_HANDLER_SIZE; + *addr =3D (void *)xen_early_idt_handler_array[nr]; + } + if (WARN_ON(ist !=3D 0 && !ist_okay)) return false; =20 @@ -1261,6 +1269,21 @@ asmlinkage __visible void __init xen_start_kernel(vo= id) xen_setup_gdt(0); =20 xen_init_irq_ops(); + + /* Let's presume PV guests always boot on vCPU with id 0. */ + per_cpu(xen_vcpu_id, 0) =3D 0; + + /* + * Setup xen_vcpu early because idt_setup_early_handler needs it for + * local_irq_disable(), irqs_disabled(). + * + * Don't do the full vcpu_info placement stuff until we have + * the cpu_possible_mask and a non-dummy shared_info. + */ + xen_vcpu_info_reset(0); + + idt_setup_early_handler(); + xen_init_capabilities(); =20 #ifdef CONFIG_X86_LOCAL_APIC @@ -1294,18 +1317,6 @@ asmlinkage __visible void __init xen_start_kernel(vo= id) */ acpi_numa =3D -1; #endif - /* Let's presume PV guests always boot on vCPU with id 0. */ - per_cpu(xen_vcpu_id, 0) =3D 0; - - /* - * Setup xen_vcpu early because start_kernel needs it for - * local_irq_disable(), irqs_disabled(). - * - * Don't do the full vcpu_info placement stuff until we have - * the cpu_possible_mask and a non-dummy shared_info. - */ - xen_vcpu_info_reset(0); - WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); =20 local_irq_disable(); diff --git a/arch/x86/xen/xen-asm_64.S b/arch/x86/xen/xen-asm_64.S index 8a10c9a9e2b5..417b339e5c8e 100644 --- a/arch/x86/xen/xen-asm_64.S +++ b/arch/x86/xen/xen-asm_64.S @@ -15,6 +15,7 @@ =20 #include =20 +#include #include =20 .macro xen_pv_trap name @@ -54,6 +55,19 @@ xen_pv_trap entry_INT80_compat #endif xen_pv_trap hypervisor_callback =20 + __INIT +ENTRY(xen_early_idt_handler_array) + i =3D 0 + .rept NUM_EXCEPTION_VECTORS + pop %rcx + pop %r11 + jmp early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE + i =3D i + 1 + .fill xen_early_idt_handler_array + i*XEN_EARLY_IDT_HANDLER_SIZE - ., 1, = 0xcc + .endr +END(xen_early_idt_handler_array) + __FINIT + hypercall_iret =3D hypercall_page + __HYPERVISOR_iret * 32 /* * Xen64 iret frame: --=20 2.11.0