From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964899AbeAXRHd convert rfc822-to-8bit (ORCPT ); Wed, 24 Jan 2018 12:07:33 -0500 Received: from www.llwyncelyn.cymru ([82.70.14.225]:35894 "EHLO fuzix.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964791AbeAXRHb (ORCPT ); Wed, 24 Jan 2018 12:07:31 -0500 Date: Wed, 24 Jan 2018 17:07:03 +0000 From: Alan Cox To: David Woodhouse Cc: Dave Hansen , linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 5/5] x86/pti: Do not enable PTI on fixed Intel processors Message-ID: <20180124170652.4c78ca17@alans-desktop> In-Reply-To: <1516811127.13558.150.camel@infradead.org> References: <1516726375-25168-1-git-send-email-dwmw@amazon.co.uk> <1516726375-25168-6-git-send-email-dwmw@amazon.co.uk> <20180123173312.1d8cf02f@alans-desktop> <1516811127.13558.150.camel@infradead.org> Organization: Intel Corporation X-Mailer: Claws Mail 3.15.1-dirty (GTK+ 2.24.31; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >   > +static const __initdata struct x86_cpu_id cpu_no_meltdown[] = { > + { X86_VENDOR_AMD }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, > + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, As Linus said this should be no_specualtion[] If we are going to capture 32bit here with your lines below I'll send you an update at some point with all the 32bit families hunted down (some like the CE4100 may take a bit of hunting) > + { X86_VENDOR_ANY, 5 }, AND K5 speculates, Cyrix 6x86 speculates, IDT WinChip does not. I think this should be X86_VENDOR_ANY, 4 X86_VENDOR_INTEL, 5, X86_VENDOR_CENTAUR, 5, > +static bool __init early_cpu_vulnerable_meltdown(struct cpuinfo_x86 *c) > +{ > + u64 ia32_cap = 0; > + > + if (x86_match_cpu(cpu_no_meltdown)) > +                return false; These processors are also not vulnerable to spectre, so this patch doesn't set the other flags correctly - that's why we need two levels of logic here. "Bonnell" and "Saltwell" uarch Atom processors are not vulnerable to Meltdown or Spectre, neithr is a 486, Pentium, Quark etc. > + > + if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) > + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); > + if (ia32_cap & ARCH_CAP_RDCL_NO) > + return false; > + > + return true; > +} > + >  /* >   * Do minimum CPU detection early. >   * Fields really needed: vendor, cpuid_level, family, model, mask, > @@ -900,9 +929,8 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) >   >   setup_force_cpu_cap(X86_FEATURE_ALWAYS); >   > - if (c->x86_vendor != X86_VENDOR_AMD) > + if (early_cpu_vulnerable_meltdown(c)) >   setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); > - >   setup_force_cpu_bug(X86_BUG_SPECTRE_V1); >   setup_force_cpu_bug(X86_BUG_SPECTRE_V2); >   > --  > 2.14.3