From: Maxime Ripard <maxime.ripard@bootlin.com>
To: "Mylène Josserand" <mylene.josserand@bootlin.com>
Cc: linux@armlinux.org.uk, wens@csie.org, robh+dt@kernel.org,
mark.rutland@arm.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, clabbe.montjoie@gmail.com,
thomas.petazzoni@bootlin.com, quentin.schulz@bootlin.com
Subject: Re: [PATCH v4 08/10] ARM: sunxi: smp: Move assembly code into a file
Date: Fri, 23 Feb 2018 16:09:49 +0100 [thread overview]
Message-ID: <20180223150949.ky4blpbc64tf44tt@flea.lan> (raw)
In-Reply-To: <20180223133742.26044-9-mylene.josserand@bootlin.com>
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On Fri, Feb 23, 2018 at 02:37:40PM +0100, Mylène Josserand wrote:
> Move the assembly code for cluster cache enabling
> into an assembly file instead of having it directly in C code.
>
> Create a sunxi_boot entry that will perform a cluster cached
> enabling and called secondary_startup.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> ---
> arch/arm/mach-sunxi/Makefile | 1 +
> arch/arm/mach-sunxi/headsmp.S | 73 +++++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-sunxi/mc_smp.c | 76 ++++---------------------------------------
> 3 files changed, 80 insertions(+), 70 deletions(-)
> create mode 100644 arch/arm/mach-sunxi/headsmp.S
>
> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
> index 7de9cc286d53..d1a072b879ed 100644
> --- a/arch/arm/mach-sunxi/Makefile
> +++ b/arch/arm/mach-sunxi/Makefile
> @@ -1,5 +1,6 @@
> CFLAGS_mc_smp.o += -march=armv7-a
>
> obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
> +obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
> obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
> obj-$(CONFIG_SMP) += platsmp.o
> diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> new file mode 100644
> index 000000000000..4f5957a6e188
> --- /dev/null
> +++ b/arch/arm/mach-sunxi/headsmp.S
> @@ -0,0 +1,73 @@
> +/*
> + * SMP support for sunxi based systems with Cortex A7/A15
> + *
> + * Copyright (C) 2018 Bootlin
This is just a copy, and while you can claim that you are one of the
copyrights holder, you are not the sole one and the original author
should be there.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
You want to use SPDX there instead.
> + */
> +
> +#include <linux/linkage.h>
> +#include <asm/assembler.h>
> +
> +ENTRY(sunxi_mc_smp_cluster_cache_enable)
> + /*
> + * Enable cluster-level coherency, in preparation for turning on the MMU.
> + *
> + * Also enable regional clock gating and L2 data latency settings for
> + * Cortex-A15. These settings are from the vendor kernel.
> + */
The indentation is not correct there, the * should be aligned
> + mrc p15, 0, r1, c0, c0, 0
> + movw r2, #(0xff00fff0&0xffff)
> + movt r2, #(0xff00fff0>>16)
This used to be defines, we should keep them, and we should have
spaces around the operators as well.
> + and r1, r1, r2
> + movw r2, #(0x4100c0f0&0xffff)
> + movt r2, #(0x4100c0f0>>16)
> + cmp r1, r2
> + bne not_a15
> +
> + /* The following is Cortex-A15 specific */
> +
> + /* ACTLR2: Enable CPU regional clock gates */
> + mrc p15, 1, r1, c15, c0, 4
> + orr r1, r1, #(0x1<<31)
> + mcr p15, 1, r1, c15, c0, 4
> +
> + /* L2ACTLR */
> + mrc p15, 1, r1, c15, c0, 0
> + /* Enable L2, GIC, and Timer regional clock gates */
> + orr r1, r1, #(0x1<<26)
> + /* Disable clean/evict from being pushed to external */
> + orr r1, r1, #(0x1<<3)
> + mcr p15, 1, r1, c15, c0, 0
> +
> + /* L2CTRL: L2 data RAM latency */
> + mrc p15, 1, r1, c9, c0, 2
> + bic r1, r1, #(0x7<<0)
> + orr r1, r1, #(0x3<<0)
> + mcr p15, 1, r1, c9, c0, 2
> +
> + /* End of Cortex-A15 specific setup */
> + not_a15:
> +
> + /* Get value of sunxi_mc_smp_first_comer */
> + adr r1, first
> + ldr r0, [r1]
> + ldr r0, [r1, r0]
> +
> + /* Skip cci_enable_port_for_self if not first comer */
> + cmp r0, #0
> + bxeq lr
> + b cci_enable_port_for_self
> +
> + .align 2
> + first: .word sunxi_mc_smp_first_comer - .
> +ENDPROC(sunxi_mc_smp_cluster_cache_enable)
> +
> +#ifdef CONFIG_SMP
I guess that whole file should be compiled only if we have SMP
enabled.
> +ENTRY(sunxi_boot)
> + bl sunxi_mc_smp_cluster_cache_enable
> + b secondary_startup
> +ENDPROC(sunxi_boot)
> +#endif
> diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
> index f2c2cfca28cd..4e807cc11a0f 100644
> --- a/arch/arm/mach-sunxi/mc_smp.c
> +++ b/arch/arm/mach-sunxi/mc_smp.c
> @@ -82,6 +82,9 @@ static void __iomem *prcm_base;
> static void __iomem *sram_b_smp_base;
> static bool is_sun9i;
>
> +extern void sunxi_boot(void);
Why did you change the name of that function? The older one made it
more obvious to tell what is going on.
> +extern void sunxi_cluster_cache_enable(void);
Is that used somewhere?
Thanks!
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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next prev parent reply other threads:[~2018-02-23 15:09 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-23 13:37 [PATCH v4 00/10] Sunxi: Add SMP support on A83T Mylène Josserand
2018-02-23 13:37 ` [PATCH v4 01/10] ARM: sun9i: smp: Add sun9i dt parsing function Mylène Josserand
2018-02-23 14:54 ` Maxime Ripard
2018-02-25 15:19 ` Mylène Josserand
2018-02-23 13:37 ` [PATCH v4 02/10] ARM: sun9i: smp: Rename clusters's power-off register Mylène Josserand
2018-02-23 14:56 ` Maxime Ripard
2018-02-25 15:20 ` Mylène Josserand
2018-02-23 13:37 ` [PATCH v4 03/10] ARM: sun8i: smp: Add support for A83T Mylène Josserand
2018-02-23 15:03 ` Maxime Ripard
2018-02-25 15:25 ` Mylène Josserand
2018-02-23 13:37 ` [PATCH v4 04/10] ARM: sun8i: smp: Add hotplug support for sun8i-a83t Mylène Josserand
2018-02-23 13:37 ` [PATCH v4 05/10] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
2018-02-23 13:37 ` [PATCH v4 06/10] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
2018-02-23 13:37 ` [PATCH v4 07/10] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
2018-02-23 13:37 ` [PATCH v4 08/10] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
2018-02-23 15:09 ` Maxime Ripard [this message]
2018-03-01 8:21 ` Mylène Josserand
2018-02-26 6:22 ` kbuild test robot
2018-02-23 13:37 ` [PATCH v4 09/10] ARM: sunxi: smp: Move cpu_resume assembly entry into file Mylène Josserand
2018-02-23 13:37 ` [PATCH v4 10/10] ARM: sunxi: smp: Add initialization of CNTVOFF Mylène Josserand
2018-02-23 15:12 ` Maxime Ripard
2018-02-23 16:17 ` Chen-Yu Tsai
2018-02-26 10:12 ` Maxime Ripard
2018-02-26 10:25 ` Chen-Yu Tsai
2018-03-05 7:51 ` Mylène Josserand
2018-03-05 8:31 ` Maxime Ripard
2018-03-05 13:51 ` Mylène Josserand
2018-03-07 12:09 ` Marc Zyngier
2018-03-07 12:18 ` Marc Zyngier
2018-03-18 19:07 ` Mylène Josserand
2018-03-19 2:14 ` Chen-Yu Tsai
2018-03-19 13:55 ` Maxime Ripard
2018-03-19 9:21 ` Marc Zyngier
2018-03-19 10:59 ` Maxime Ripard
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