From: Yixun Lan <yixun.lan@amlogic.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Carlo Caione <carlo@caione.org>
Cc: Yixun Lan <yixun.lan@amlogic.com>, Rob Herring <robh@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Qiufang Dai <qiufang.dai@amlogic.com>,
<linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH v2 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
Date: Fri, 23 Mar 2018 22:38:13 +0800 [thread overview]
Message-ID: <20180323143816.200573-5-yixun.lan@amlogic.com> (raw)
In-Reply-To: <20180323143816.200573-1-yixun.lan@amlogic.com>
Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
include/dt-bindings/clock/axg-aoclkc.h | 26 ++++++++++++++++++++++++++
include/dt-bindings/reset/axg-aoclkc.h | 20 ++++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..61955016a55b
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE 0
+#define CLKID_AO_I2C_MASTER 1
+#define CLKID_AO_I2C_SLAVE 2
+#define CLKID_AO_UART1 3
+#define CLKID_AO_UART2 4
+#define CLKID_AO_IR_BLASTER 5
+#define CLKID_AO_SAR_ADC 6
+#define CLKID_AO_CLK81 7
+#define CLKID_AO_SAR_ADC_SEL 8
+#define CLKID_AO_SAR_ADC_DIV 9
+#define CLKID_AO_SAR_ADC_CLK 10
+#define CLKID_AO_ALT_XTAL 11
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..d342c0b6b2a7
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE 0
+#define RESET_AO_I2C_MASTER 1
+#define RESET_AO_I2C_SLAVE 2
+#define RESET_AO_UART1 3
+#define RESET_AO_UART2 4
+#define RESET_AO_IR_BLASTER 5
+
+#endif
--
2.15.1
next prev parent reply other threads:[~2018-03-23 14:39 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-23 14:38 [PATCH v2 0/7] clk: meson-axg: Add AO Cloclk and Reset driver Yixun Lan
2018-03-23 14:38 ` [PATCH v2 1/7] clk: meson: drop meson_aoclk_gate_regmap_ops Yixun Lan
2018-03-27 8:40 ` Jerome Brunet
2018-03-23 14:38 ` [PATCH v2 2/7] clk: meson: aoclk: refactor common code into dedicated file Yixun Lan
2018-03-27 8:30 ` Jerome Brunet
2018-03-23 14:38 ` [PATCH v2 3/7] dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC Yixun Lan
2018-03-26 22:25 ` Rob Herring
2018-03-23 14:38 ` Yixun Lan [this message]
2018-03-26 22:25 ` [PATCH v2 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings Rob Herring
2018-03-23 14:38 ` [PATCH v2 5/7] clk: meson-axg: Add AO Clock and Reset controller driver Yixun Lan
2018-03-23 14:38 ` [PATCH v2 6/7] arm64: dts: meson-axg: add AO clock driver DT info Yixun Lan
2018-03-23 14:38 ` [PATCH v2 7/7] ARM64: dts: meson-axg: add an 32K alt aoclk Yixun Lan
2018-03-27 9:00 ` Jerome Brunet
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