From: "Luck, Tony" <tony.luck@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH 2/2] x86/MCE: Always save MCA_{ADDR,MISC,SYND} register contents
Date: Mon, 26 Mar 2018 13:27:56 -0700 [thread overview]
Message-ID: <20180326202756.6qqqgjdjnx6ggng2@agluck-desk> (raw)
In-Reply-To: <20180326200955.GG28372@pd.tnic>
On Mon, Mar 26, 2018 at 10:09:55PM +0200, Borislav Petkov wrote:
> On Mon, Mar 26, 2018 at 08:05:37PM +0000, Ghannam, Yazen wrote:
> > Sure, I can do that. But I didn't think it was necessary because it doesn't hurt
> > to read the registers whether or not the valid bits are set.
>
> No, this needs to be AMD-specific because it will confuse people using
> Intel machines.
Worse than confusion it may even cause a crash on Intel. Quoting the
Intel SDM:
15.3.2.3 IA32_MCi_ADDR MSRs
The IA32_MCi_ADDR MSR contains the address of the code or data memory
location that produced the machine- check error if the ADDRV flag in
the IA32_MCi_STATUS register is set (see Section 15-7, “IA32_MCi_ADDR
MSR”). The IA32_MCi_ADDR register is either not implemented or
contains no address if the ADDRV flag in the IA32_MCi_STATUS register
is clear. When not implemented in the processor, all reads and writes
to this MSR will cause a general protection exception.
Ditto for the MISC register. Please don't read them unless
the ADDRV/MISCV bits are set in the corresponding STATUS
register.
Thanks
-Tony
next prev parent reply other threads:[~2018-03-26 20:28 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-26 19:15 [PATCH 1/2] Revert "x86/mce/AMD: Collect error info even if valid bits are not set" Yazen Ghannam
2018-03-26 19:15 ` [PATCH 2/2] x86/MCE: Always save MCA_{ADDR,MISC,SYND} register contents Yazen Ghannam
2018-03-26 19:35 ` Borislav Petkov
2018-03-26 20:05 ` Ghannam, Yazen
2018-03-26 20:09 ` Borislav Petkov
2018-03-26 20:27 ` Luck, Tony [this message]
2018-03-27 14:07 ` Ghannam, Yazen
2018-03-26 19:30 ` [PATCH 1/2] Revert "x86/mce/AMD: Collect error info even if valid bits are not set" Borislav Petkov
2018-03-26 19:58 ` Ghannam, Yazen
2018-03-26 20:07 ` Borislav Petkov
2018-03-27 14:02 ` Ghannam, Yazen
2018-03-27 15:59 ` Ghannam, Yazen
2018-08-23 12:24 ` Borislav Petkov
2018-08-23 17:53 ` Ghannam, Yazen
2018-03-28 18:39 ` [tip:ras/core] " tip-bot for Yazen Ghannam
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