From: "Mylène Josserand" <mylene.josserand@bootlin.com>
To: linux@armlinux.org.uk, maxime.ripard@bootlin.com, wens@csie.org,
marc.zyngier@arm.com, mark.rutland@arm.com, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, clabbe.montjoie@gmail.com,
quentin.schulz@bootlin.com, thomas.petazzoni@bootlin.com,
mylene.josserand@bootlin.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v5 06/13] ARM: dts: sun8i: a83t: Add CCI-400 node
Date: Tue, 3 Apr 2018 08:18:29 +0200 [thread overview]
Message-ID: <20180403061836.3926-7-mylene.josserand@bootlin.com> (raw)
In-Reply-To: <20180403061836.3926-1-mylene.josserand@bootlin.com>
Add CCI-400 node and control-port on CPUs needed by SMP bringup.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 85f14f4ebeed..9ac905884d81 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ cci-control-port = <&cci_control0>;
reg = <0>;
};
@@ -73,6 +74,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ cci-control-port = <&cci_control0>;
reg = <1>;
};
@@ -80,6 +82,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ cci-control-port = <&cci_control0>;
reg = <2>;
};
@@ -87,6 +90,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ cci-control-port = <&cci_control0>;
reg = <3>;
};
@@ -96,6 +100,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <&cpu1_opp_table>;
+ cci-control-port = <&cci_control1>;
reg = <0x100>;
};
@@ -103,6 +108,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <&cpu1_opp_table>;
+ cci-control-port = <&cci_control1>;
reg = <0x101>;
};
@@ -110,6 +116,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <&cpu1_opp_table>;
+ cci-control-port = <&cci_control1>;
reg = <0x102>;
};
@@ -117,6 +124,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <&cpu1_opp_table>;
+ cci-control-port = <&cci_control1>;
reg = <0x103>;
};
};
@@ -354,6 +362,39 @@
reg = <0x01700000 0x400>;
};
+ cci@1790000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x01790000 0x10000>;
+ ranges = <0x0 0x01790000 0x10000>;
+
+ cci_control0: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control1: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu,r1";
+ reg = <0x9000 0x5000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
syscon: syscon@1c00000 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
--
2.11.0
next prev parent reply other threads:[~2018-04-03 6:23 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-03 6:18 [PATCH v5 00/13] Sunxi: Add SMP support on A83T Mylène Josserand
2018-04-03 6:18 ` [PATCH v5 01/13] ARM: move cputype definitions into another file Mylène Josserand
2018-04-03 6:52 ` Chen-Yu Tsai
2018-04-03 7:27 ` Mylène Josserand
2018-04-03 7:34 ` Chen-Yu Tsai
2018-04-03 19:56 ` Florian Fainelli
2018-04-04 13:49 ` Mylène Josserand
2018-04-03 6:18 ` [PATCH v5 02/13] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand
2018-04-03 6:18 ` [PATCH v5 03/13] ARM: sunxi: smp: Move cpu_resume assembly entry into file Mylène Josserand
2018-04-03 6:18 ` [PATCH v5 04/13] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand
2018-04-03 6:45 ` Chen-Yu Tsai
2018-04-03 6:18 ` [PATCH v5 05/13] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand
2018-04-03 9:07 ` Chen-Yu Tsai
2018-04-03 19:52 ` Mylène Josserand
2018-04-03 6:18 ` Mylène Josserand [this message]
2018-04-03 6:44 ` [PATCH v5 06/13] ARM: dts: sun8i: a83t: Add CCI-400 node Chen-Yu Tsai
2018-04-03 6:18 ` [PATCH v5 07/13] ARM: smp: Add initialization of CNTVOFF Mylène Josserand
2018-04-04 13:01 ` Marc Zyngier
2018-04-04 13:59 ` Mylène Josserand
2018-04-04 14:30 ` Marc Zyngier
2018-04-09 8:24 ` Geert Uytterhoeven
2018-04-09 9:04 ` Marc Zyngier
2018-04-11 7:44 ` Mylène Josserand
2018-04-03 6:18 ` [PATCH v5 08/13] ARM: sunxi: " Mylène Josserand
2018-04-03 9:12 ` Maxime Ripard
2018-04-03 20:06 ` Mylène Josserand
2018-04-04 7:45 ` Maxime Ripard
2018-04-08 9:09 ` Mylène Josserand
2018-04-09 9:24 ` Maxime Ripard
2018-04-03 11:13 ` kbuild test robot
2018-04-03 6:18 ` [PATCH v5 09/13] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand
2018-04-03 9:06 ` Chen-Yu Tsai
2018-04-03 6:18 ` [PATCH v5 10/13] ARM: sun9i: smp: Move structures Mylène Josserand
2018-04-03 8:47 ` Maxime Ripard
2018-04-03 8:51 ` Chen-Yu Tsai
2018-04-03 6:18 ` [PATCH v5 11/13] ARM: sun9i: smp: Add is_sun9i field Mylène Josserand
2018-04-03 8:46 ` Maxime Ripard
2018-04-03 8:48 ` Chen-Yu Tsai
2018-04-03 20:08 ` Mylène Josserand
2018-04-03 6:18 ` [PATCH v5 12/13] ARM: sun8i: smp: Add support for A83T Mylène Josserand
2018-04-03 8:47 ` Chen-Yu Tsai
2018-04-03 20:21 ` Mylène Josserand
2018-04-03 6:18 ` [PATCH v5 13/13] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand
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