From: Marc Zyngier <marc.zyngier@arm.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
Rob Herring <robh@kernel.org>,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 9/9] dt-bindings/gic-v3: Add documentation for MBI support
Date: Tue, 8 May 2018 13:14:38 +0100 [thread overview]
Message-ID: <20180508121438.11301-10-marc.zyngier@arm.com> (raw)
In-Reply-To: <20180508121438.11301-1-marc.zyngier@arm.com>
Add the required properties to support the MBI feature on GICv3.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
.../bindings/interrupt-controller/arm,gic-v3.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
index 0a57f2f4167d..3ea78c4ef887 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
@@ -57,6 +57,20 @@ Optional
occupied by the redistributors. Required if more than one such
region is present.
+- msi-controller: Boolean property. Identifies the node as an MSI
+ controller. Only present if the Message Based Interrupt
+ functionnality is being exposed by the HW, and the mbi-ranges
+ property present.
+
+- mbi-ranges: A list of pairs <intid span>, where "intid" is the first
+ SPI of a range that can be used an MBI, and "span" the size of that
+ range. Multiple ranges can be provided. Requires "msi-controller" to
+ be set.
+
+- mbi-alias: Address property. Base address of an alias of the GICD
+ region containing only the {SET,CLR}SPI registers to be used if
+ isolation is required, and if supported by the HW.
+
Sub-nodes:
PPI affinity can be expressed as a single "ppi-partitions" node,
@@ -99,6 +113,9 @@ Examples:
<0x0 0x2c020000 0 0x2000>; // GICV
interrupts = <1 9 4>;
+ msi-controller;
+ mbi-ranges = <256 128>;
+
gic-its@2c200000 {
compatible = "arm,gic-v3-its";
msi-controller;
--
2.14.2
next prev parent reply other threads:[~2018-05-08 12:15 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-08 12:14 [PATCH v2 0/9] Level-triggered MSI support Marc Zyngier
2018-05-08 12:14 ` [PATCH v2 1/9] genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers Marc Zyngier
2018-05-13 14:03 ` [tip:irq/core] " tip-bot for Marc Zyngier
2018-05-08 12:14 ` [PATCH v2 2/9] genirq/msi: Limit level-triggered MSI to platform devices Marc Zyngier
2018-05-13 14:04 ` [tip:irq/core] " tip-bot for Marc Zyngier
2018-05-08 12:14 ` [PATCH v2 3/9] irqchip/mvebu-gicp: Use level-triggered MSIs between ICU and GICP Marc Zyngier
2018-05-13 14:04 ` [tip:irq/core] " tip-bot for Marc Zyngier
2018-05-08 12:14 ` [PATCH v2 4/9] dma-iommu: Fix compilation when !CONFIG_IOMMU_DMA Marc Zyngier
2018-05-13 14:05 ` [tip:irq/core] " tip-bot for Marc Zyngier
2018-05-08 12:14 ` [PATCH v2 5/9] irqdomain: Let irq_find_host default to DOMAIN_BUS_WIRED Marc Zyngier
2018-05-13 14:05 ` [tip:irq/core] " tip-bot for Marc Zyngier
2018-05-08 12:14 ` [PATCH v2 6/9] irqchip/gic-v3: Mark the base irq domain as DOMAIN_BUS_WIRED Marc Zyngier
2018-05-13 14:06 ` [tip:irq/core] " tip-bot for Marc Zyngier
2018-05-08 12:14 ` [PATCH v2 7/9] irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller Marc Zyngier
2018-05-13 14:06 ` [tip:irq/core] " tip-bot for Marc Zyngier
2018-05-08 12:14 ` [PATCH v2 8/9] irqchip/gic-v3: Add PCI/MSI support to the GICv3 MBI sub-driver Marc Zyngier
2018-05-13 14:07 ` [tip:irq/core] " tip-bot for Marc Zyngier
2018-05-08 12:14 ` Marc Zyngier [this message]
2018-05-13 14:07 ` [tip:irq/core] dt-bindings/gic-v3: Add documentation for MBI support tip-bot for Marc Zyngier
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