From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: Ingo Molnar <mingo@redhat.com>,
x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>
Cc: Hugh Dickins <hughd@google.com>,
linux-kernel@vger.kernel.org,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: [PATCH 1/7] x86/boot/compressed/64: Fix trampoline page table address calculation
Date: Fri, 18 May 2018 13:35:22 +0300 [thread overview]
Message-ID: <20180518103528.59260-2-kirill.shutemov@linux.intel.com> (raw)
In-Reply-To: <20180518103528.59260-1-kirill.shutemov@linux.intel.com>
Hugh noticied that I calculate address of trampoline page table wrongly
in cleanup_trampoline(). TRAMPOLINE_32BIT_PGTABLE_OFFSET has to be
divided by sizeof(unsigned long) since trampoline_32bit is unsigned long
pointer.
TRAMPOLINE_32BIT_PGTABLE_OFFSET is zero so the bug doesn't have a
visible effect.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Reported-by: Hugh Dickins <hughd@google.com>
Fixes: e9d0e6330eb8 ("x86/boot/compressed/64: Prepare new top-level page table for trampoline")
---
arch/x86/boot/compressed/pgtable_64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
index a362fa0b849c..23707e1da1ff 100644
--- a/arch/x86/boot/compressed/pgtable_64.c
+++ b/arch/x86/boot/compressed/pgtable_64.c
@@ -130,7 +130,7 @@ void cleanup_trampoline(void *pgtable)
{
void *trampoline_pgtable;
- trampoline_pgtable = trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET;
+ trampoline_pgtable = trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long);
/*
* Move the top level page table out of trampoline memory,
--
2.17.0
next prev parent reply other threads:[~2018-05-18 10:35 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-18 10:35 [PATCHv5 0/7] 5-level paging changes for v4.18 Kirill A. Shutemov
2018-05-18 10:35 ` Kirill A. Shutemov [this message]
2018-05-19 8:43 ` [PATCH 1/7] x86/boot/compressed/64: Fix trampoline page table address calculation Thomas Gleixner
2018-05-19 11:33 ` [tip:x86/boot] " tip-bot for Kirill A. Shutemov
2018-05-18 10:35 ` [PATCH 2/7] x86/mm: Unify pgtable_l5_enabled usage in early boot code Kirill A. Shutemov
2018-05-19 8:44 ` Thomas Gleixner
2018-05-19 11:34 ` [tip:x86/boot] " tip-bot for Kirill A. Shutemov
2018-05-18 10:35 ` [PATCH 3/7] x86/mm: Stop pretending pgtable_l5_enabled is a variable Kirill A. Shutemov
2018-05-19 8:45 ` Thomas Gleixner
2018-05-19 11:34 ` [tip:x86/boot] " tip-bot for Kirill A. Shutemov
2018-05-18 10:35 ` [PATCH 4/7] x86/mm: Introduce 'no5lvl' kernel parameter Kirill A. Shutemov
2018-05-19 8:46 ` Thomas Gleixner
2018-05-19 11:35 ` [tip:x86/boot] x86/mm: Introduce the " tip-bot for Kirill A. Shutemov
2018-05-18 10:35 ` [PATCH 5/7] x86/cpu: Move early cpu initialization into a separate translation unit Kirill A. Shutemov
2018-05-19 8:47 ` Thomas Gleixner
2018-06-05 10:19 ` Kirill A. Shutemov
2018-05-18 10:35 ` [PATCH 6/7] x86/mm: Mark p4d_offset() __always_inline Kirill A. Shutemov
2018-05-19 8:47 ` Thomas Gleixner
2018-05-19 11:35 ` [tip:x86/boot] " tip-bot for Kirill A. Shutemov
2018-05-18 10:35 ` [PATCH 7/7] x86/mm: Mark __pgtable_l5_enabled __initdata Kirill A. Shutemov
2018-05-19 8:48 ` Thomas Gleixner
2018-05-19 11:36 ` [tip:x86/boot] " tip-bot for Kirill A. Shutemov
2018-05-19 8:49 ` [PATCHv5 0/7] 5-level paging changes for v4.18 Thomas Gleixner
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