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From: ilia.lin@gmail.com
To: ilia.lin@gmail.com
Cc: Rajendra Nayak <rnayak@codeaurora.org>,
	Ilia Lin <ilialin@codeaurora.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	Will Deacon <will.deacon@arm.com>,
	Amit Kucheria <amit.kucheria@linaro.org>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v13 6/8] clk: qcom: cpu-8996: Add support to switch to alternate PLL
Date: Thu, 14 Jun 2018 23:53:53 +0200	[thread overview]
Message-ID: <20180614215358.11264-7-ilia.lin@gmail.com> (raw)
In-Reply-To: <20180614215358.11264-1-ilia.lin@gmail.com>

From: Rajendra Nayak <rnayak@codeaurora.org>

Each of the CPU clusters on msm8996 are powered via a primary
PLL and a secondary PLL. The primary PLL is what drives the
CPU clk, except for times when we are reprogramming the PLL
itself, when we temporarily switch to an alternate PLL.
Use clock rate change notifiers to support this.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
---
 drivers/clk/qcom/clk-cpu-8996.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index d92cad93af20..620fdc2266ba 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -52,6 +52,7 @@
  * detect voltage droops.
  */
 
+#include <linux/clk.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
@@ -178,10 +179,14 @@ struct clk_cpu_8996_mux {
 	u32	reg;
 	u8	shift;
 	u8	width;
+	struct notifier_block nb;
 	struct clk_hw	*pll;
 	struct clk_regmap clkr;
 };
 
+#define to_clk_cpu_8996_mux_nb(_nb) \
+	container_of(_nb, struct clk_cpu_8996_mux, nb)
+
 static inline
 struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
 {
@@ -227,6 +232,26 @@ clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
 	return 0;
 }
 
+int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
+			void *data)
+{
+	int ret;
+	struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
+
+	switch (event) {
+	case PRE_RATE_CHANGE:
+		ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
+		break;
+	case POST_RATE_CHANGE:
+		ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX);
+		break;
+	default:
+		ret = 0;
+		break;
+	}
+
+	return notifier_from_errno(ret);
+};
 const struct clk_ops clk_cpu_8996_mux_ops = {
 	.set_parent = clk_cpu_8996_mux_set_parent,
 	.get_parent = clk_cpu_8996_mux_get_parent,
@@ -270,6 +295,7 @@ static struct clk_cpu_8996_mux pwrcl_pmux = {
 	.shift = 0,
 	.width = 2,
 	.pll = &pwrcl_pll.clkr.hw,
+	.nb.notifier_call = cpu_clk_notifier_cb,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "pwrcl_pmux",
 		.parent_names = (const char *[]){
@@ -289,6 +315,7 @@ static struct clk_cpu_8996_mux perfcl_pmux = {
 	.shift = 0,
 	.width = 2,
 	.pll = &perfcl_pll.clkr.hw,
+	.nb.notifier_call = cpu_clk_notifier_cb,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "perfcl_pmux",
 		.parent_names = (const char *[]){
@@ -347,6 +374,12 @@ qcom_cpu_clk_msm8996_register_clks(struct device *dev, struct regmap *regmap)
 	clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
 	clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
 
+	ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
+	if (ret)
+		return ret;
+
+	ret = clk_notifier_register(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
+
 	return ret;
 }
 
-- 
2.11.0


  parent reply	other threads:[~2018-06-14 21:55 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-14 21:53 [PATCH v13 0/8] Clock for CPU scaling support for msm8996 ilia.lin
2018-06-14 21:53 ` [PATCH v13 1/8] soc: qcom: Separate kryo l2 accessors from PMU driver ilia.lin
2018-06-14 21:53 ` [PATCH v13 2/8] clk: qcom: Make clk_alpha_pll_configure available to modules ilia.lin
2018-10-17 15:39   ` Stephen Boyd
2018-06-14 21:53 ` [PATCH v13 3/8] clk: Use devm_ in the register fixed factor clock ilia.lin
2018-09-14 18:53   ` Ricardo Salveti
2018-10-12 22:08     ` Stephen Boyd
2018-10-14 20:21       ` Niklas Cassel
2018-10-17 15:41         ` Stephen Boyd
2018-06-14 21:53 ` [PATCH v13 4/8] clk: qcom: Add CPU clock driver for msm8996 ilia.lin
2018-10-17 15:38   ` Stephen Boyd
2018-06-14 21:53 ` [PATCH v13 5/8] dt-bindings: clk: qcom: Add bindings for CPU clock " ilia.lin
2018-06-14 21:53 ` ilia.lin [this message]
2018-10-17 15:32   ` [PATCH v13 6/8] clk: qcom: cpu-8996: Add support to switch to alternate PLL Stephen Boyd
2018-06-14 21:53 ` [PATCH v13 7/8] clk: qcom: cpu-8996: Add support to switch below 600Mhz ilia.lin
2018-06-14 21:53 ` [PATCH v13 8/8] clk: qcom: Add ACD path to CPU clock driver for msm8996 ilia.lin
2018-10-16 23:56   ` Stephen Boyd

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