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[89.64.25.103]) by smtp.gmail.com with ESMTPSA id h90-v6sm2761220ljf.65.2018.06.18.09.21.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Jun 2018 09:21:46 -0700 (PDT) From: Piotr Bugalski To: Mark Brown , linux-spi@vger.kernel.org, David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Rob Herring , Mark Rutland , Nicolas Ferre , Alexandre Belloni , Cyrille Pitchen , Tudor Ambarus , Piotr Bugalski Subject: [RFC PATCH 0/2] New QuadSPI driver for Atmel SAMA5D2 Date: Mon, 18 Jun 2018 18:21:22 +0200 Message-Id: <20180618162124.21749-1-bugalski.piotr@gmail.com> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, Atmel SAMA5D2 is equipped with two QSPI interfaces. These interfaces can work as in SPI-compatible mode or use two / four lines to improve communication speed. At the moment there is QSPI driver strongly tied to NOR-flash memory and MTD subsystem. Intention of this change is to provide new driver which will not be tied to MTD and allows using QSPI with NAND-flash memory or other peripherals New spi-mem API provides abstraction layer which can disconnect QSPI from MTD. This driver doesn't support regular SPI interface, it should be used with spi-mem interface only. Unfortunately SAMA5D2 hardware by default supports only NOR-flash memory. It allows 24- and 32-bit addressing while NAND-flash requires 16-bit long. To workaround hardware limitation driver is a bit more complicated. Request to spi-mem contains three fiels: opcode (command), address, dummy bytes. SAMA5D2 QSPI hardware supports opcode, address, dummy and option byte where address field can only be 24- or 32- bytes long. Handling 8-bits long addresses is done using option field. For 16-bits address behaviour depends of number of requested dummy bits. If there are 8 or more dummy cycles, address is shifted and sent with first dummy byte. Otherwise opcode is disabled and first byte of address contains command opcode (works only if opcode and address use the same buswidth). The limitation is when 16-bit address is used without enough dummy cycles and opcode is using different buswidth than address. Other modes are supported with described workaround. It looks like hardware has some limitation in performance. The same issue exists in current QSPI driver (MTD/nor-flash) and soft-pack (bare-metal library from Atmel). Without using DMA read speed is much worse than maximum bandwidth (efficiency 30-40%). Any help with performance improvement is highly welcome, especially for NAND-flash memories which offers higher capacity than NOR-flash used with previous driver. Best Regards, Piotr Piotr Bugalski (2): spi: Add QuadSPI driver for Atmel SAMA5D2 dt-bindings: spi: QuadSPI driver for Atmel SAMA5D2 documentation .../devicetree/bindings/spi/spi_atmel-qspi.txt | 41 ++ drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-atmel-qspi.c | 480 +++++++++++++++++++++ 4 files changed, 531 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel-qspi.txt create mode 100644 drivers/spi/spi-atmel-qspi.c -- 2.11.0