From: Mark Rutland <mark.rutland@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, will.deacon@arm.com,
robin.murphy@arm.com, julien.thierry@arm.com
Subject: Re: [PATCH v3 6/7] arm64: perf: Disable PMU while processing counter overflows
Date: Tue, 19 Jun 2018 11:43:23 +0100 [thread overview]
Message-ID: <20180619104323.huwx5n2z53lmtnux@lakrids.cambridge.arm.com> (raw)
In-Reply-To: <1529403342-17899-7-git-send-email-suzuki.poulose@arm.com>
On Tue, Jun 19, 2018 at 11:15:41AM +0100, Suzuki K Poulose wrote:
> The arm64 PMU updates the event counters and reprograms the
> counters in the overflow IRQ handler without disabling the
> PMU. This could potentially cause skews in for group counters,
> where the overflowed counters may potentially loose some event
> counts, while they are reprogrammed. To prevent this, disable
> the PMU while we process the counter overflows and enable it
> right back when we are done.
>
> This patch also moves the PMU stop/start routines to avoid a
> forward declaration.
>
> Suggested-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
This makes me realise that we could remove the pmu_lock, but that's not
a new problem, and we can address that separately.
Thanks,
Mark.
> ---
> arch/arm64/kernel/perf_event.c | 50 +++++++++++++++++++++++-------------------
> 1 file changed, 28 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 9ce3729..eebc635 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -678,6 +678,28 @@ static void armv8pmu_disable_event(struct perf_event *event)
> raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
> }
>
> +static void armv8pmu_start(struct arm_pmu *cpu_pmu)
> +{
> + unsigned long flags;
> + struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
> +
> + raw_spin_lock_irqsave(&events->pmu_lock, flags);
> + /* Enable all counters */
> + armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
> + raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
> +}
> +
> +static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
> +{
> + unsigned long flags;
> + struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
> +
> + raw_spin_lock_irqsave(&events->pmu_lock, flags);
> + /* Disable all counters */
> + armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
> + raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
> +}
> +
> static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
> {
> u32 pmovsr;
> @@ -702,6 +724,11 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
> */
> regs = get_irq_regs();
>
> + /*
> + * Stop the PMU while processing the counter overflows
> + * to prevent skews in group events.
> + */
> + armv8pmu_stop(cpu_pmu);
> for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
> struct perf_event *event = cpuc->events[idx];
> struct hw_perf_event *hwc;
> @@ -726,6 +753,7 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
> if (perf_event_overflow(event, &data, regs))
> cpu_pmu->disable(event);
> }
> + armv8pmu_start(cpu_pmu);
>
> /*
> * Handle the pending perf events.
> @@ -739,28 +767,6 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
> return IRQ_HANDLED;
> }
>
> -static void armv8pmu_start(struct arm_pmu *cpu_pmu)
> -{
> - unsigned long flags;
> - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
> -
> - raw_spin_lock_irqsave(&events->pmu_lock, flags);
> - /* Enable all counters */
> - armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
> - raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
> -}
> -
> -static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
> -{
> - unsigned long flags;
> - struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
> -
> - raw_spin_lock_irqsave(&events->pmu_lock, flags);
> - /* Disable all counters */
> - armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
> - raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
> -}
> -
> static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
> struct perf_event *event)
> {
> --
> 2.7.4
>
next prev parent reply other threads:[~2018-06-19 10:43 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-19 10:15 [PATCH v3 0/7] arm64: perf: Support for chained counters Suzuki K Poulose
2018-06-19 10:15 ` [PATCH v3 1/7] arm_pmu: Clean up maximum period handling Suzuki K Poulose
2018-06-19 10:45 ` Mark Rutland
2018-06-19 10:15 ` [PATCH v3 2/7] arm_pmu: Change API to support 64bit counter values Suzuki K Poulose
2018-06-19 10:52 ` Mark Rutland
2018-06-19 10:15 ` [PATCH v3 3/7] arm_pmu: Add support for 64bit event counters Suzuki K Poulose
2018-06-19 10:57 ` Mark Rutland
2018-06-19 10:15 ` [PATCH v3 4/7] arm_pmu: Tidy up clear_event_idx call backs Suzuki K Poulose
2018-06-29 13:27 ` Mark Rutland
2018-06-29 13:40 ` Mark Rutland
2018-06-29 14:18 ` Suzuki K Poulose
2018-06-29 14:29 ` Mark Rutland
2018-06-19 10:15 ` [PATCH v3 5/7] arm64: perf: Clean up armv8pmu_select_counter Suzuki K Poulose
2018-06-29 13:29 ` Mark Rutland
2018-06-19 10:15 ` [PATCH v3 6/7] arm64: perf: Disable PMU while processing counter overflows Suzuki K Poulose
2018-06-19 10:43 ` Mark Rutland [this message]
2018-06-19 10:15 ` [PATCH v3 7/7] arm64: perf: Add support for chaining event counters Suzuki K Poulose
2018-06-29 14:01 ` Mark Rutland
2018-06-29 14:29 ` Suzuki K Poulose
2018-06-29 14:39 ` Mark Rutland
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