From: Tom Lendacky <thomas.lendacky@amd.com> To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>, Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>, Thomas Gleixner <tglx@linutronix.de>, Borislav Petkov <bpetkov@suse.de>, David Woodhouse <dwmw@amazon.co.uk> Subject: [PATCH 2/2] x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR Date: Mon, 02 Jul 2018 16:36:02 -0500 Message-ID: <20180702213602.29202.33151.stgit@tlendack-t1.amdoffice.net> (raw) In-Reply-To: <20180702213543.29202.79104.stgit@tlendack-t1.amdoffice.net> On AMD, the presence of the MSR_SPEC_CTRL feature does not imply that the SSBD mitigation support should use the SPEC_CTRL MSR. Other features could have caused the MSR_SPEC_CTRL feature to be set, while a different SSBD mitigation option is in place. Update the SSBD support to check for the actual SSBD features that will use the SPEC_CTRL MSR. Fixes: 6ac2f49edb1e ("x86/bugs: Add AMD's SPEC_CTRL MSR usage") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- arch/x86/kernel/cpu/bugs.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 404df26..5c0ea39 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -155,7 +155,8 @@ enum spectre_v2_mitigation_cmd { guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; /* SSBD controlled in MSR_SPEC_CTRL */ - if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) + if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || + static_cpu_has(X86_FEATURE_AMD_SSBD)) hostval |= ssbd_tif_to_spec_ctrl(ti->flags); if (hostval != guestval) { @@ -533,9 +534,10 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void) * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may * use a completely different MSR and bit dependent on family. */ - if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) + if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && + !static_cpu_has(X86_FEATURE_AMD_SSBD)) { x86_amd_ssb_disable(); - else { + } else { x86_spec_ctrl_base |= SPEC_CTRL_SSBD; x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
next prev parent reply index Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-07-02 21:35 [PATCH 0/2] x86/bugs: Updates to SSBD support on AMD Tom Lendacky 2018-07-02 21:35 ` [PATCH 1/2] x86/bugs: Update when to check for the LS_CFG SSBD mitigation Tom Lendacky 2018-07-03 8:33 ` [tip:x86/pti] " tip-bot for Tom Lendacky 2018-07-03 14:12 ` [PATCH 1/2] " Konrad Rzeszutek Wilk 2018-07-02 21:36 ` Tom Lendacky [this message] 2018-07-03 8:34 ` [tip:x86/pti] x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR tip-bot for Tom Lendacky 2018-07-03 14:12 ` [PATCH 2/2] " Konrad Rzeszutek Wilk
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