[PATCH 0/2] x86/bugs: Updates to SSBD support on AMD

[PATCH 0/2] x86/bugs: Updates to SSBD support on AMD

[Tom Lendacky]

These patches update the SSBD support on AMD processors.

The following patches are included in this series:
- In addition to checking the family, the check for the LS_CFG_SSBD
  feature only needs to done if both the AMD_SSBD and VIRT_SSBD features
  are not present.
- Since AMD can support more than one SSBD mitigation method, the check
  for when to use the SPEC_CTRL MSR for SSBD support needs to be more
  specific.  Explicitly check for the features that use the SPEC_CTRL MSR.

This patch series is based on tip:master.

---

Tom Lendacky (2):
      x86/bugs: Update when to check for the LS_CFG SSBD mitigation
      x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR


 arch/x86/kernel/cpu/amd.c  |    4 +++-
 arch/x86/kernel/cpu/bugs.c |    8 +++++---
 2 files changed, 8 insertions(+), 4 deletions(-)

-- 
Tom Lendacky

[PATCH 1/2] x86/bugs: Update when to check for the LS_CFG SSBD mitigation

[Tom Lendacky]

If either the X86_FEATURE_AMD_SSBD or X86_FEATURE_VIRT_SSBD features are
present, then there is no need to perform the check for the LS_CFG SSBD
mitigation support.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
 arch/x86/kernel/cpu/amd.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 082d787..38915fb 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -543,7 +543,9 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
 		nodes_per_socket = ((value >> 3) & 7) + 1;
 	}
 
-	if (c->x86 >= 0x15 && c->x86 <= 0x17) {
+	if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
+	    !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
+	    c->x86 >= 0x15 && c->x86 <= 0x17) {
 		unsigned int bit;
 
 		switch (c->x86) {

[PATCH 2/2] x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR

[Tom Lendacky]

On AMD, the presence of the MSR_SPEC_CTRL feature does not imply that the
SSBD mitigation support should use the SPEC_CTRL MSR. Other features could
have caused the MSR_SPEC_CTRL feature to be set, while a different SSBD
mitigation option is in place.

Update the SSBD support to check for the actual SSBD features that will
use the SPEC_CTRL MSR.

Fixes: 6ac2f49edb1e ("x86/bugs: Add AMD's SPEC_CTRL MSR usage")
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
 arch/x86/kernel/cpu/bugs.c |    8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 404df26..5c0ea39 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -155,7 +155,8 @@ enum spectre_v2_mitigation_cmd {
 		guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 
 		/* SSBD controlled in MSR_SPEC_CTRL */
-		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
+		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
+		    static_cpu_has(X86_FEATURE_AMD_SSBD))
 			hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 
 		if (hostval != guestval) {
@@ -533,9 +534,10 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
 		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
 		 * use a completely different MSR and bit dependent on family.
 		 */
-		if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
+		if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
+		    !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
 			x86_amd_ssb_disable();
-		else {
+		} else {
 			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 			x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 			wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

[tip:x86/pti] x86/bugs: Update when to check for the LS_CFG SSBD mitigation

[tip-bot for Tom Lendacky]

Commit-ID:  845d382bb15c6e7dc5026c0ff919c5b13fc7e11b
Gitweb:     https://git.kernel.org/tip/845d382bb15c6e7dc5026c0ff919c5b13fc7e11b
Author:     Tom Lendacky <thomas.lendacky@amd.com>
AuthorDate: Mon, 2 Jul 2018 16:35:53 -0500
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 3 Jul 2018 09:45:48 +0200

x86/bugs: Update when to check for the LS_CFG SSBD mitigation

If either the X86_FEATURE_AMD_SSBD or X86_FEATURE_VIRT_SSBD features are
present, then there is no need to perform the check for the LS_CFG SSBD
mitigation support.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Borislav Petkov <bpetkov@suse.de>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20180702213553.29202.21089.stgit@tlendack-t1.amdoffice.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/amd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 082d7875cef8..38915fbfae73 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -543,7 +543,9 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
 		nodes_per_socket = ((value >> 3) & 7) + 1;
 	}
 
-	if (c->x86 >= 0x15 && c->x86 <= 0x17) {
+	if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
+	    !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
+	    c->x86 >= 0x15 && c->x86 <= 0x17) {
 		unsigned int bit;
 
 		switch (c->x86) {

[tip:x86/pti] x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR

[tip-bot for Tom Lendacky]

Commit-ID:  612bc3b3d4be749f73a513a17d9b3ee1330d3487
Gitweb:     https://git.kernel.org/tip/612bc3b3d4be749f73a513a17d9b3ee1330d3487
Author:     Tom Lendacky <thomas.lendacky@amd.com>
AuthorDate: Mon, 2 Jul 2018 16:36:02 -0500
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 3 Jul 2018 09:45:48 +0200

x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR

On AMD, the presence of the MSR_SPEC_CTRL feature does not imply that the
SSBD mitigation support should use the SPEC_CTRL MSR. Other features could
have caused the MSR_SPEC_CTRL feature to be set, while a different SSBD
mitigation option is in place.

Update the SSBD support to check for the actual SSBD features that will
use the SPEC_CTRL MSR.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Borislav Petkov <bpetkov@suse.de>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: 6ac2f49edb1e ("x86/bugs: Add AMD's SPEC_CTRL MSR usage")
Link: http://lkml.kernel.org/r/20180702213602.29202.33151.stgit@tlendack-t1.amdoffice.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/bugs.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 404df26b7de8..5c0ea39311fe 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -155,7 +155,8 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 		guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 
 		/* SSBD controlled in MSR_SPEC_CTRL */
-		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
+		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
+		    static_cpu_has(X86_FEATURE_AMD_SSBD))
 			hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 
 		if (hostval != guestval) {
@@ -533,9 +534,10 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
 		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
 		 * use a completely different MSR and bit dependent on family.
 		 */
-		if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
+		if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
+		    !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
 			x86_amd_ssb_disable();
-		else {
+		} else {
 			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 			x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 			wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

Re: [PATCH 1/2] x86/bugs: Update when to check for the LS_CFG SSBD mitigation

[Konrad Rzeszutek Wilk]

On Mon, Jul 02, 2018 at 04:35:53PM -0500, Tom Lendacky wrote:
> If either the X86_FEATURE_AMD_SSBD or X86_FEATURE_VIRT_SSBD features are
> present, then there is no need to perform the check for the LS_CFG SSBD
> mitigation support.
> 
> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

> ---
>  arch/x86/kernel/cpu/amd.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> index 082d787..38915fb 100644
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -543,7 +543,9 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
>  		nodes_per_socket = ((value >> 3) & 7) + 1;
>  	}
>  
> -	if (c->x86 >= 0x15 && c->x86 <= 0x17) {
> +	if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
> +	    !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
> +	    c->x86 >= 0x15 && c->x86 <= 0x17) {
>  		unsigned int bit;
>  
>  		switch (c->x86) {
> 

Re: [PATCH 2/2] x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR

[Konrad Rzeszutek Wilk]

On Mon, Jul 02, 2018 at 04:36:02PM -0500, Tom Lendacky wrote:
> On AMD, the presence of the MSR_SPEC_CTRL feature does not imply that the
> SSBD mitigation support should use the SPEC_CTRL MSR. Other features could
> have caused the MSR_SPEC_CTRL feature to be set, while a different SSBD
> mitigation option is in place.
> 
> Update the SSBD support to check for the actual SSBD features that will
> use the SPEC_CTRL MSR.
> 
> Fixes: 6ac2f49edb1e ("x86/bugs: Add AMD's SPEC_CTRL MSR usage")
> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>

Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

Thank you!
> ---
>  arch/x86/kernel/cpu/bugs.c |    8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
> index 404df26..5c0ea39 100644
> --- a/arch/x86/kernel/cpu/bugs.c
> +++ b/arch/x86/kernel/cpu/bugs.c
> @@ -155,7 +155,8 @@ enum spectre_v2_mitigation_cmd {
>  		guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
>  
>  		/* SSBD controlled in MSR_SPEC_CTRL */
> -		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
> +		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
> +		    static_cpu_has(X86_FEATURE_AMD_SSBD))
>  			hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
>  
>  		if (hostval != guestval) {
> @@ -533,9 +534,10 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
>  		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
>  		 * use a completely different MSR and bit dependent on family.
>  		 */
> -		if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
> +		if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
> +		    !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
>  			x86_amd_ssb_disable();
> -		else {
> +		} else {
>  			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
>  			x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
>  			wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
>