From: Pavel Machek <pavel@ucw.cz>
To: Jan Beulich <JBeulich@suse.com>
Cc: mingo@elte.hu, tglx@linutronix.de, hpa@zytor.com,
davem@davemloft.net, herbert@gondor.apana.org.au,
rjw@rjwysocki.net, Juergen Gross <jgross@suse.com>,
linux-kernel@vger.kernel.org, Alok Kataria <akataria@vmware.com>
Subject: Re: [PATCH v2] x86-64: use 32-bit XOR to zero registers
Date: Wed, 4 Jul 2018 22:29:34 +0200 [thread overview]
Message-ID: <20180704202934.GB15246@amd> (raw)
In-Reply-To: <5B39FF1A02000078001CFB54@prv1-mh.provo.novell.com>
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On Mon 2018-07-02 04:31:54, Jan Beulich wrote:
> Some Intel CPUs don't recognize 64-bit XORs as zeroing idioms. Zeroing
> idioms don't require execution bandwidth, as they're being taken care
> of in the frontend (through register renaming). Use 32-bit XORs instead.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> @@ -702,7 +702,7 @@ _no_extra_mask_1_\@:
>
> # GHASH computation for the last <16 Byte block
> GHASH_MUL \AAD_HASH, %xmm13, %xmm0, %xmm10, %xmm11, %xmm5, %xmm6
> - xor %rax,%rax
> + xor %eax, %eax
>
> mov %rax, PBlockLen(%arg2)
> jmp _dec_done_\@
This is rather subtle... and looks like a bug. To zero 64-bit
register, you zero its lower half, relying on implicit zeroing of the
upper half. Wow.
Perhaps we should get comments in the code? Because the explicit code
is more readable...
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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next prev parent reply other threads:[~2018-07-04 20:29 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-02 10:31 [PATCH v2] x86-64: use 32-bit XOR to zero registers Jan Beulich
2018-07-03 8:35 ` [tip:x86/asm] x86/asm/64: Use " tip-bot for Jan Beulich
2018-07-04 20:29 ` Pavel Machek [this message]
2018-07-05 7:12 ` [PATCH v2] x86-64: use " Ingo Molnar
2018-07-09 8:33 ` Pavel Machek
2018-07-09 8:47 ` Jan Beulich
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