From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8497C6778C for ; Thu, 5 Jul 2018 14:22:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 881ED240EF for ; Thu, 5 Jul 2018 14:22:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="DQl169bP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 881ED240EF Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754102AbeGEOWO (ORCPT ); Thu, 5 Jul 2018 10:22:14 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:57248 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753512AbeGEOWH (ORCPT ); Thu, 5 Jul 2018 10:22:07 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w65ELhpL072729; Thu, 5 Jul 2018 09:21:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1530800503; bh=r0nDY41M61FBqYVJy5eocealUfh8csvf581+1/ANA9I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DQl169bP9300bx+b6a3x9fIGVrx9HpPIyRKPW9NWN+atEbjDt88U1qgQyu6zohpm/ myoYz/4bSKhtiblMHaupxCkWKJwtAkmAsEIov7kj8vdUOI+AgT/rd/A8wn1plMcfPk N+TGrJHa7hB4i6HjovqhQdIPpXlw4dcj0eiAaZzg= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w65ELhH2019652; Thu, 5 Jul 2018 09:21:43 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 5 Jul 2018 09:21:43 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 5 Jul 2018 09:21:43 -0500 Received: from a0230074-OptiPlex-7010.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w65ELPxj020259; Thu, 5 Jul 2018 09:21:40 -0500 From: Faiz Abbas To: , , , , CC: , , , , , , Subject: [PATCH v4 4/6] bus: ti-sysc: Add support for software reset Date: Thu, 5 Jul 2018 19:53:17 +0530 Message-ID: <20180705142319.19583-5-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180705142319.19583-1-faiz_abbas@ti.com> References: <20180705142319.19583-1-faiz_abbas@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the software reset of a target interconnect module using its sysconfig and sysstatus registers. Signed-off-by: Faiz Abbas --- drivers/bus/ti-sysc.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index ad1cd6888757..ac65a4f336d5 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -23,11 +23,14 @@ #include #include #include +#include #include #include +#define MAX_MODULE_SOFTRESET_WAIT 10000 + static const char * const reg_names[] = { "rev", "sysc", "syss", }; enum sysc_clocks { @@ -88,6 +91,11 @@ struct sysc { struct delayed_work idle_work; }; +void sysc_write(struct sysc *ddata, int offset, u32 value) +{ + writel_relaxed(value, ddata->module_va + offset); +} + static u32 sysc_read(struct sysc *ddata, int offset) { if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { @@ -943,6 +951,26 @@ static void sysc_init_revision_quirks(struct sysc *ddata) } } +static int sysc_reset(struct sysc *ddata) +{ + int offset = ddata->offsets[SYSC_SYSCONFIG]; + int val = sysc_read(ddata, offset); + + val |= (0x1 << ddata->cap->regbits->srst_shift); + sysc_write(ddata, offset, val); + + /* Poll on reset status */ + if (ddata->cfg.syss_mask) { + offset = ddata->offsets[SYSC_SYSSTATUS]; + + return readl_poll_timeout(ddata->module_va + offset, val, + (val & ddata->cfg.syss_mask) == 0x0, + 100, MAX_MODULE_SOFTRESET_WAIT); + } + + return 0; +} + /* At this point the module is configured enough to read the revision */ static int sysc_init_module(struct sysc *ddata) { @@ -960,6 +988,17 @@ static int sysc_init_module(struct sysc *ddata) return 0; } + if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && + !ddata->legacy_mode) { + error = sysc_reset(ddata); + if (error) { + dev_err(ddata->dev, "Reset failed with %d\n", error); + pm_runtime_put_sync(ddata->dev); + + return error; + } + } + ddata->revision = sysc_read_revision(ddata); pm_runtime_put_sync(ddata->dev); -- 2.17.0