From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D012DC3279B for ; Fri, 6 Jul 2018 11:01:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 90817217AF for ; Fri, 6 Jul 2018 11:01:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 90817217AF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754164AbeGFLBq (ORCPT ); Fri, 6 Jul 2018 07:01:46 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:45108 "EHLO smtp2200-217.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753946AbeGFLBo (ORCPT ); Fri, 6 Jul 2018 07:01:44 -0400 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.07493031|-1;CH=green;FP=0|0|0|0|0|-1|-1|-1;HT=e01l07447;MF=ren_guo@c-sky.com;NM=1;PH=DS;RN=13;RT=13;SR=0;TI=SMTPD_---.CN3WA2e_1530874891; Received: from localhost(mailfrom:ren_guo@c-sky.com fp:SMTPD_---.CN3WA2e_1530874891) by smtp.aliyun-inc.com(10.147.40.44); Fri, 06 Jul 2018 19:01:31 +0800 Date: Fri, 6 Jul 2018 19:01:31 +0800 From: Guo Ren To: Peter Zijlstra Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, daniel.lezcano@linaro.org, jason@lakedaemon.net, arnd@arndb.de, c-sky_gcc_upstream@c-sky.com, gnu-csky@mentor.com, thomas.petazzoni@bootlin.com, wbx@uclibc-ng.org, green.hu@gmail.com, Will Deacon Subject: Re: [PATCH V2 11/19] csky: Atomic operations Message-ID: <20180706110129.GC8707@guoren> References: <860b8db036b33d7b3648cb1f4ec827a53dc1a01b.1530465326.git.ren_guo@c-sky.com> <20180705175059.GE2530@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180705175059.GE2530@hirez.programming.kicks-ass.net> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 05, 2018 at 07:50:59PM +0200, Peter Zijlstra wrote: > On Mon, Jul 02, 2018 at 01:30:14AM +0800, Guo Ren wrote: > > > +#include > > + > > +#define __xchg(new, ptr, size) \ > > +({ \ > > + __typeof__(ptr) __ptr = (ptr); \ > > + __typeof__(new) __new = (new); \ > > + __typeof__(*(ptr)) __ret; \ > > + unsigned long tmp; \ > > + switch (size) { \ > > + case 4: \ > > + asm volatile ( \ > > + "1: ldex.w %0, (%3) \n" \ > > + " mov %1, %2 \n" \ > > + " stex.w %1, (%3) \n" \ > > + " bez %1, 1b \n" \ > > + : "=&r" (__ret), "=&r" (tmp) \ > > + : "r" (__new), "r"(__ptr) \ > > + : "memory"); \ > > + smp_mb(); \ > > + break; \ > > + default: \ > > + BUILD_BUG(); \ > > + } \ > > + __ret; \ > > +}) > > + > > +#define xchg(ptr, x) (__xchg((x), (ptr), sizeof(*(ptr)))) > > + > > +#define __cmpxchg(ptr, old, new, size) \ > > +({ \ > > + __typeof__(ptr) __ptr = (ptr); \ > > + __typeof__(new) __new = (new); \ > > + __typeof__(new) __tmp; \ > > + __typeof__(old) __old = (old); \ > > + __typeof__(*(ptr)) __ret; \ > > + switch (size) { \ > > + case 4: \ > > + asm volatile ( \ > > + "1: ldex.w %0, (%3) \n" \ > > + " cmpne %0, %4 \n" \ > > + " bt 2f \n" \ > > + " mov %1, %2 \n" \ > > + " stex.w %1, (%3) \n" \ > > + " bez %1, 1b \n" \ > > + "2: \n" \ > > + : "=&r" (__ret), "=&r" (__tmp) \ > > + : "r" (__new), "r"(__ptr), "r"(__old) \ > > + : "memory"); \ > > + smp_mb(); \ > > + break; \ > > + default: \ > > + BUILD_BUG(); \ > > + } \ > > + __ret; \ > > +}) > > + > > +#define cmpxchg(ptr, o, n) \ > > + (__cmpxchg((ptr), (o), (n), sizeof(*(ptr)))) > > What's the memory ordering rules for your LDEX/STEX ? Every CPU has a local exclusive monitor. "Ldex rz, (rx, #off)" will add an entry into the local monitor, and the entry is composed of a address tag and a exclusive flag (inited with 1). Any stores (include other cores') will break the exclusive flag to 0 in the entry which could be indexed by the address tag. "Stex rz, (rx, #off)" has two condition: 1. Store Success: When the entry's exclusive flag is 1, it will store rz to the [rx + off] address and the rz will be set to 1. 2. Store Failure: When the entry's exclusive flag is 0, just rz will be set to 0. > The mandated semantics for xchg() / cmpxchg() is an effective smp_mb() > before _and_ after. switch (size) { \ case 4: \ smp_mb(); \ asm volatile ( \ "1: ldex.w %0, (%3) \n" \ " mov %1, %2 \n" \ " stex.w %1, (%3) \n" \ " bez %1, 1b \n" \ : "=&r" (__ret), "=&r" (tmp) \ : "r" (__new), "r"(__ptr) \ : "memory"); \ smp_mb(); \ break; \ Hmm? But I couldn't undertand what's wrong without the 1th smp_mb()? 1th smp_mb will make all ld/st finish before ldex.w. Is it necessary? > The above implementation suggests LDEX implies a SYNC.IS, is this > correct? No, ldex doesn't imply a sync.is. Guo Ren