From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4E54C6778F for ; Mon, 9 Jul 2018 13:07:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 88689208A2 for ; Mon, 9 Jul 2018 13:07:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 88689208A2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932789AbeGINHA (ORCPT ); Mon, 9 Jul 2018 09:07:00 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:58830 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932595AbeGING6 (ORCPT ); Mon, 9 Jul 2018 09:06:58 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 100F2ED1; Mon, 9 Jul 2018 06:06:58 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D43323F5AD; Mon, 9 Jul 2018 06:06:57 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 4E6361AE3638; Mon, 9 Jul 2018 14:07:39 +0100 (BST) Date: Mon, 9 Jul 2018 14:07:39 +0100 From: Will Deacon To: Alexey Brodkin Cc: linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arch@vger.kernel.org, Peter Zijlstra , Boqun Feng , Russell King , Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Darren Hart , Shuah Khan , "Paul E. McKenney" , Josh Triplett , Steven Rostedt , Mathieu Desnoyers , Lai Jiangshan , David Laight , Geert Uytterhoeven , Greg Kroah-Hartman Subject: Re: [PATCH] atomic{64}_t: Explicitly specify data storage length and alignment Message-ID: <20180709130738.GA28336@arm.com> References: <20180709124741.21037-1-abrodkin@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180709124741.21037-1-abrodkin@synopsys.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jul 09, 2018 at 03:47:41PM +0300, Alexey Brodkin wrote: > Atomic instructions require data they operate on to be aligned > according to data size. I.e. 32-bit atomic values must be 32-bit > aligned while 64-bit values must be 64-bit aligned. > > Otherwise even if CPU may handle not-aligend normal data access, > still atomic instructions fail and typically raise an exception > leaving us dead in the water. > > This came-up during lengthly discussion here: > http://lists.infradead.org/pipermail/linux-snps-arc/2018-July/004022.html > > Signed-off-by: Alexey Brodkin > Cc: Will Deacon > Cc: Peter Zijlstra > Cc: Boqun Feng > Cc: Russell King > Cc: Arnd Bergmann > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: Darren Hart > Cc: Shuah Khan > Cc: "Paul E. McKenney" > Cc: Josh Triplett > Cc: Steven Rostedt > Cc: Mathieu Desnoyers > Cc: Lai Jiangshan > Cc: David Laight > Cc: Geert Uytterhoeven > Cc: Greg Kroah-Hartman > --- > arch/arm/include/asm/atomic.h | 2 +- > include/asm-generic/atomic64.h | 2 +- > include/linux/types.h | 4 ++-- > tools/include/linux/types.h | 2 +- > tools/testing/selftests/futex/include/atomic.h | 2 +- > .../rcutorture/formal/srcu-cbmc/include/linux/types.h | 4 ++-- > 6 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h > index 66d0e215a773..2ed6d7cf1407 100644 > --- a/arch/arm/include/asm/atomic.h > +++ b/arch/arm/include/asm/atomic.h > @@ -267,7 +267,7 @@ ATOMIC_OPS(xor, ^=, eor) > > #ifndef CONFIG_GENERIC_ATOMIC64 > typedef struct { > - long long counter; > + u64 __aligned(8) counter; > } atomic64_t; Long long is 8-byte aligned per EABI ARM, and we use the generic atomic64 infrastructure for OABI, so we don't need to change anything here afaict. Will