From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B2E8C5CFE7 for ; Tue, 10 Jul 2018 08:05:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 09D3C20878 for ; Tue, 10 Jul 2018 08:05:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 09D3C20878 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933461AbeGJIFA (ORCPT ); Tue, 10 Jul 2018 04:05:00 -0400 Received: from mail.bootlin.com ([62.4.15.54]:53200 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933299AbeGJICV (ORCPT ); Tue, 10 Jul 2018 04:02:21 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 1404120C9B; Tue, 10 Jul 2018 10:02:20 +0200 (CEST) Received: from localhost.localdomain (AAubervilliers-681-1-12-56.w90-88.abo.wanadoo.fr [90.88.133.56]) by mail.bootlin.com (Postfix) with ESMTPSA id 40EAE20990; Tue, 10 Jul 2018 10:02:03 +0200 (CEST) From: Paul Kocialkowski To: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mauro Carvalho Chehab , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Paul Kocialkowski , Marco Franchi , Icenowy Zheng , Hans Verkuil , Keiichi Watanabe , Jonathan Corbet , Smitha T Murthy , Tom Saeger , Andrzej Hajda , "David S . Miller" , Greg Kroah-Hartman , Andrew Morton , Randy Dunlap , Arnd Bergmann , Geert Uytterhoeven , Laurent Pinchart , Jacob Chen , Neil Armstrong , Benoit Parrot , Todor Tomov , Alexandre Courbot , Sakari Ailus , Andy Shevchenko , Pawel Osciak , Ricardo Ribalda Delgado , Hans de Goede , Sami Tolvanen , =?UTF-8?q?Niklas=20S=C3=B6derlund?= , linux-sunxi@googlegroups.com, Thomas Petazzoni , Hugues Fruchet , Randy Li Subject: [PATCH v5 20/22] ARM: dts: sun7i-a20: Add Video Engine and reserved memory nodes Date: Tue, 10 Jul 2018 10:01:12 +0200 Message-Id: <20180710080114.31469-21-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180710080114.31469-1-paul.kocialkowski@bootlin.com> References: <20180710080114.31469-1-paul.kocialkowski@bootlin.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds nodes for the Video Engine and the associated reserved memory for the A20. Up to 96 MiB of memory are dedicated to the CMA pool. The VPU can only map the first 256 MiB of DRAM, so the reserved memory pool has to be located in that area. Following Allwinner's decision in downstream software, the last 96 MiB of the first 256 MiB of RAM are reserved for this purpose. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 38999d791cb5..cb6e10196118 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -161,6 +161,21 @@ reg = <0x40000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ + cma_pool: cma@4a000000 { + compatible = "shared-dma-pool"; + size = <0x6000000>; + alloc-ranges = <0x4a000000 0x6000000>; + reusable; + linux,cma-default; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -466,6 +481,19 @@ }; }; + vpu: video-codec@1c0e000 { + compatible = "allwinner,sun7i-a20-video-engine"; + reg = <0x01c0e000 0x1000>; + + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + + resets = <&ccu RST_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; -- 2.17.1