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[24.223.123.72]) by smtp.gmail.com with ESMTPSA id m3-v6sm13724365oif.26.2018.07.11.12.12.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 11 Jul 2018 12:12:53 -0700 (PDT) Date: Wed, 11 Jul 2018 13:12:52 -0600 From: Rob Herring To: Corentin Labbe Cc: linux@armlinux.org.uk, mark.rutland@arm.com, maxime.ripard@free-electrons.com, tj@kernel.org, wens@csie.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, icenowy@aosc.io Subject: Re: [PATCH v2 1/4] dt-bindings: add binding for Allwinner R40 SATA AHCI controller Message-ID: <20180711191252.GA2289@rob-hp-laptop> References: <1531149658-27030-1-git-send-email-clabbe@baylibre.com> <1531149658-27030-2-git-send-email-clabbe@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1531149658-27030-2-git-send-email-clabbe@baylibre.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jul 09, 2018 at 03:20:55PM +0000, Corentin Labbe wrote: > From: Icenowy Zheng > > The Allwinner R40 SoC contains a SATA AHCI controller like the one in > A10/A20 SoCs, however a reset control and two power supplies are added > to it. > > Add a binding document for it. > > As a dedicated binding document is needed now for the A10/A20/R40 AHCI > controller, drop the A10 compatible line from generic platform AHCI > controller binding document. > > Signed-off-by: Icenowy Zheng > Signed-off-by: Corentin Labbe > --- > .../devicetree/bindings/ata/ahci-platform.txt | 1 - > .../bindings/ata/allwinner,sun4i-a10-ahci.txt | 40 ++++++++++++++++++++++ > 2 files changed, 40 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt > > diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt > index c760ecb81381..1bea4b5ef9fd 100644 > --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt > +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt > @@ -9,7 +9,6 @@ PHYs. > > Required properties: > - compatible : compatible string, one of: > - - "allwinner,sun4i-a10-ahci" > - "brcm,iproc-ahci" > - "hisilicon,hisi-ahci" > - "cavium,octeon-7130-ahci" > diff --git a/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt > new file mode 100644 > index 000000000000..0eea78c14ad3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt > @@ -0,0 +1,40 @@ > +Allwinner A10/A20/R40 SoC SATA AHCI Controller > + > +Required properties: > +- compatible : compatible string, one of: > + - "allwinner,sun4i-a10-ahci" > + - "allwinner,sun8i-r40-ahci" > +- interrupts : the SATA IRQ > +- reg : the register mapping > +- clocks : the clocks needed by SATA controller, usually contains > + an AHB clock and a mod clock usually? Need to specify the order. The examples look reversed of what you have here. > + > +Optional properties: > +- target-supply : regulator for SATA target power > + > +Required properties for the following compatibles: > + - "allwinner,sun8i-r40-ahci" > +- resets : the reset control needed by SATA controller > +- vdd1v2-supply : regulator for SATA controller's 1.2V VDD > +- vdd2v5-supply : regulator for SATA controller's 2.5V VDD > + > + > +Examples for A10: > + ahci: sata@1c18000 { > + compatible = "allwinner,sun4i-a10-ahci"; > + reg = <0x01c18000 0x1000>; > + interrupts = <56>; > + clocks = <&pll6 0>, <&ahb_gates 25>; > + target-supply = <®_ahci_5v>; > + }; > + > +Examples for R40: > + ahci: sata@1c18000 { > + compatible = "allwinner,sun8i-r40-ahci"; > + reg = <0x01c18000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_SATA>, <&ccu CLK_BUS_SATA>; > + resets = <&ccu RST_BUS_SATA>; > + vdd1v2-supply = <®_eldo3>; > + vdd2v5-supply = <®_dldo4>; > + }; > -- > 2.16.4 >