* [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support
@ 2018-07-22 16:49 Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc Marcel Ziswiler
` (27 more replies)
0 siblings, 28 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Mikko Perttunen,
Jonathan Hunter, Rob Herring, Marcel Ziswiler, Mark Rutland
This series is a major overhaul and adds support for the V1.1 hardware
revision of the Toradex Apalis T30 system on module.
Marcel Ziswiler (28):
ARM: tegra: apalis_t30: enable broken-hpi on emmc
ARM: tegra: apalis_t30: fix mmc1 cmd pull-up
ARM: tegra: apalis_t30: pull-up sd card detect pins
ARM: tegra: apalis_t30: add local-mac-address property
ARM: tegra: apalis_t30: reorder pcie properties
ARM: tegra: apalis_t30: annotate pcie port nodes
ARM: tegra: apalis_t30: reorder host1x/hdmi properties
ARM: tegra: apalis_t30: regulator clean-up
ARM: tegra: apalis_t30: add missing regulators
ARM: tegra: apalis_t30: annotate uarts
ARM: tegra: apalis_t30: drop unused cami2c label
ARM: tegra: apalis_t30: white-space clean-up
ARM: tegra: apalis_t30: drop unused mmc1/sd1 labels
ARM: tegra: apalis_t30: annotate mmc1/sd1
ARM: tegra: apalis_t30: move dr_mode property from phy to controller
ARM: tegra: apalis_t30: reorder backlight properties
ARM: tegra: apalis_t30: drop pwmleds
ARM: tegra: apalis_t30: pinmux clean-up
ARM: tegra: apalis_t30: add missing pinmux
ARM: tegra: apalis_t30: use proper irq-gpio for stmpe811
ARM: tegra: apalis_t30: further lm95245 temperature sensor annotation
ARM: tegra: apalis_t30: add i2c-thermtrip
ARM: tegra: apalis_t30: add proper emmc vmmc and vqmmc supplies
ARM: tegra: apalis_t30: enable emmc ddr52 mode
ARM: tegra: apalis_t30: rename clk to clock
ARM: tegra: apalis_t30: line break long compatible property line
ARM: tegra: apalis_t30: fix pcie switch vendor compatible
ARM: tegra: apalis_t30: support v1.1 hardware revision
Documentation/devicetree/bindings/arm/tegra.txt | 2 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra30-apalis-eval.dts | 116 +--
arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 280 ++++++
arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 1189 +++++++++++++++++++++++
arch/arm/boot/dts/tegra30-apalis.dtsi | 595 ++++++++++--
6 files changed, 2013 insertions(+), 170 deletions(-)
create mode 100644 arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
create mode 100644 arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
--
2.14.4
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-24 14:03 ` Dmitry Osipenko
2018-07-22 16:49 ` [PATCH 02/28] ARM: tegra: apalis_t30: fix mmc1 cmd pull-up Marcel Ziswiler
` (26 subsequent siblings)
27 siblings, 1 reply; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Avoid eMMC issues by specifying broken-hpi.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 2f807d40c1b7..23ffe6a3bc2d 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -699,8 +699,16 @@
/* eMMC */
sdhci@78000600 {
status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
bus-width = <8>;
non-removable;
+
+ emmc: emmc@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
};
clocks {
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 02/28] ARM: tegra: apalis_t30: fix mmc1 cmd pull-up
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 03/28] ARM: tegra: apalis_t30: pull-up sd card detect pins Marcel Ziswiler
` (25 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Fix MMC1 cmd pin pull-up causing issues on carrier boards without
external pull-up.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 23ffe6a3bc2d..e7f3dd52a209 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -171,14 +171,14 @@
/* Apalis MMC1 */
sdmmc3_clk_pa6 {
- nvidia,pins = "sdmmc3_clk_pa6",
- "sdmmc3_cmd_pa7";
+ nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc3_dat0_pb7 {
- nvidia,pins = "sdmmc3_dat0_pb7",
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4",
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 03/28] ARM: tegra: apalis_t30: pull-up sd card detect pins
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 02/28] ARM: tegra: apalis_t30: fix mmc1 cmd pull-up Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 04/28] ARM: tegra: apalis_t30: add local-mac-address property Marcel Ziswiler
` (24 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
In order to avoid any floating SD card detect pins as may e.g. happen on
Ixora V1.1A pull them all up.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index e7f3dd52a209..f4dc7e77114f 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -194,7 +194,7 @@
pv3 {
nvidia,pins = "pv3";
nvidia,function = "rsvd2";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
@@ -260,7 +260,7 @@
clk2_req_pcc5 {
nvidia,pins = "clk2_req_pcc5";
nvidia,function = "rsvd2";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 04/28] ARM: tegra: apalis_t30: add local-mac-address property
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (2 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 03/28] ARM: tegra: apalis_t30: pull-up sd card detect pins Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 05/28] ARM: tegra: apalis_t30: reorder pcie properties Marcel Ziswiler
` (23 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add empty local-mac-address property to be filled in by boot loader
(e.g. U-Boot).
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index f4dc7e77114f..98d702bc3718 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -34,6 +34,10 @@
pci@3,0 {
nvidia,num-lanes = <1>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
};
};
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 05/28] ARM: tegra: apalis_t30: reorder pcie properties
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (3 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 04/28] ARM: tegra: apalis_t30: add local-mac-address property Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 06/28] ARM: tegra: apalis_t30: annotate pcie port nodes Marcel Ziswiler
` (22 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reorder PCIe properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 98d702bc3718..0574eda8b3f9 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -16,13 +16,13 @@
pcie@3000 {
avdd-pexa-supply = <&vdd2_reg>;
- vdd-pexa-supply = <&vdd2_reg>;
avdd-pexb-supply = <&vdd2_reg>;
- vdd-pexb-supply = <&vdd2_reg>;
avdd-pex-pll-supply = <&vdd2_reg>;
avdd-plle-supply = <&ldo6_reg>;
- vddio-pex-ctl-supply = <&sys_3v3_reg>;
hvdd-pex-supply = <&sys_3v3_reg>;
+ vddio-pex-ctl-supply = <&sys_3v3_reg>;
+ vdd-pexa-supply = <&vdd2_reg>;
+ vdd-pexb-supply = <&vdd2_reg>;
pci@1,0 {
nvidia,num-lanes = <4>;
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 06/28] ARM: tegra: apalis_t30: annotate pcie port nodes
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (4 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 05/28] ARM: tegra: apalis_t30: reorder pcie properties Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 07/28] ARM: tegra: apalis_t30: reorder host1x/hdmi properties Marcel Ziswiler
` (21 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Annotate PCIe port nodes.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 0574eda8b3f9..a1cc415b3893 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -24,14 +24,17 @@
vdd-pexa-supply = <&vdd2_reg>;
vdd-pexb-supply = <&vdd2_reg>;
+ /* Apalis type specific */
pci@1,0 {
nvidia,num-lanes = <4>;
};
+ /* Apalis PCIe */
pci@2,0 {
nvidia,num-lanes = <1>;
};
+ /* I210/I211 Gigabit Ethernet Controller (on-module) */
pci@3,0 {
nvidia,num-lanes = <1>;
pcie@0 {
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 07/28] ARM: tegra: apalis_t30: reorder host1x/hdmi properties
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (5 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 06/28] ARM: tegra: apalis_t30: annotate pcie port nodes Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 08/28] ARM: tegra: apalis_t30: regulator clean-up Marcel Ziswiler
` (20 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reorder Host1x/HDMI properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index a1cc415b3893..d765cac7022a 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -46,12 +46,11 @@
host1x@50000000 {
hdmi@54280000 {
- vdd-supply = <&avdd_hdmi_3v3_reg>;
- pll-supply = <&avdd_hdmi_pll_1v8_reg>;
-
+ nvidia,ddc-i2c-bus = <&hdmiddc>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
- nvidia,ddc-i2c-bus = <&hdmiddc>;
+ pll-supply = <&avdd_hdmi_pll_1v8_reg>;
+ vdd-supply = <&avdd_hdmi_3v3_reg>;
};
};
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 08/28] ARM: tegra: apalis_t30: regulator clean-up
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (6 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 07/28] ARM: tegra: apalis_t30: reorder host1x/hdmi properties Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 09/28] ARM: tegra: apalis_t30: add missing regulators Marcel Ziswiler
` (19 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Just cosmetic regulator clean-up.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 62 ++++++-------
arch/arm/boot/dts/tegra30-apalis.dtsi | 140 +++++++++++++-----------------
2 files changed, 88 insertions(+), 114 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 0dc85a20bd45..85e6adc82515 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -159,7 +159,7 @@
usb-phy@7d000000 {
status = "okay";
dr_mode = "otg";
- vbus-supply = <&usbo1_vbus_reg>;
+ vbus-supply = <®_usbo1_vbus>;
};
/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
@@ -169,7 +169,7 @@
usb-phy@7d004000 {
status = "okay";
- vbus-supply = <&usbh_vbus_reg>;
+ vbus-supply = <®_usbh_vbus>;
};
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
@@ -179,7 +179,7 @@
usb-phy@7d008000 {
status = "okay";
- vbus-supply = <&usbh_vbus_reg>;
+ vbus-supply = <®_usbh_vbus>;
};
backlight: backlight {
@@ -237,38 +237,32 @@
};
};
- regulators {
- sys_5v0_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V_SW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
- /* USBO1_EN */
- usbo1_vbus_reg: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "usbo1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&sys_5v0_reg>;
- };
+ /* USBO1_EN */
+ reg_usbo1_vbus: regulator-usbo1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_USBO1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_5v0>;
+ };
- /* USBH_EN */
- usbh_vbus_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "usbh_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&sys_5v0_reg>;
- };
+ /* USBH_EN */
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_5v0>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index d765cac7022a..45c0066984fe 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -19,8 +19,8 @@
avdd-pexb-supply = <&vdd2_reg>;
avdd-pex-pll-supply = <&vdd2_reg>;
avdd-plle-supply = <&ldo6_reg>;
- hvdd-pex-supply = <&sys_3v3_reg>;
- vddio-pex-ctl-supply = <&sys_3v3_reg>;
+ hvdd-pex-supply = <®_module_3v3>;
+ vddio-pex-ctl-supply = <®_module_3v3>;
vdd-pexa-supply = <&vdd2_reg>;
vdd-pexb-supply = <&vdd2_reg>;
@@ -49,8 +49,8 @@
nvidia,ddc-i2c-bus = <&hdmiddc>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
- pll-supply = <&avdd_hdmi_pll_1v8_reg>;
- vdd-supply = <&avdd_hdmi_3v3_reg>;
+ pll-supply = <®_1v8_avdd_hdmi_pll>;
+ vdd-supply = <®_3v3_avdd_hdmi>;
};
};
@@ -463,8 +463,8 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
- VDDA-supply = <&sys_3v3_reg>;
- VDDIO-supply = <&sys_3v3_reg>;
+ VDDA-supply = <®_module_3v3>;
+ VDDIO-supply = <®_module_3v3>;
clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
};
@@ -481,43 +481,38 @@
#gpio-cells = <2>;
gpio-controller;
- vcc1-supply = <&sys_3v3_reg>;
- vcc2-supply = <&sys_3v3_reg>;
- vcc3-supply = <&vio_reg>;
- vcc4-supply = <&sys_3v3_reg>;
- vcc5-supply = <&sys_3v3_reg>;
- vcc6-supply = <&vio_reg>;
- vcc7-supply = <&charge_pump_5v0_reg>;
- vccio-supply = <&sys_3v3_reg>;
+ vcc1-supply = <®_module_3v3>;
+ vcc2-supply = <®_module_3v3>;
+ vcc3-supply = <®_1v8_vio>;
+ vcc4-supply = <®_module_3v3>;
+ vcc5-supply = <®_module_3v3>;
+ vcc6-supply = <®_1v8_vio>;
+ vcc7-supply = <®_5v0_charge_pump>;
+ vccio-supply = <®_module_3v3>;
regulators {
- /* SW1: +V1.35_VDDIO_DDR */
vdd1_reg: vdd1 {
- regulator-name = "vddio_ddr_1v35";
+ regulator-name = "+V1.35_VDDIO_DDR";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
- /* SW2: +V1.05 */
vdd2_reg: vdd2 {
- regulator-name =
- "vdd_pexa,vdd_pexb,vdd_sata";
+ regulator-name = "+V1.05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
- /* SW CTRL: +V1.0_VDD_CPU */
vddctrl_reg: vddctrl {
- regulator-name = "vdd_cpu,vdd_sys";
+ regulator-name = "+V1.0_VDD_CPU";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
};
- /* SWIO: +V1.8 */
- vio_reg: vio {
- regulator-name = "vdd_1v8_gen";
+ reg_1v8_vio: vio {
+ regulator-name = "+V1.8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@@ -527,27 +522,24 @@
/*
* EN_+V3.3 switching via FET:
- * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
- * see also v3_3 fixed supply
+ * +V3.3_AUDIO_AVDD_S, +V3.3
+ * see also +V3.3 fixed supply
*/
ldo2_reg: ldo2 {
- regulator-name = "en_3v3";
+ regulator-name = "EN_+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
- /* +V1.2_CSI */
ldo3_reg: ldo3 {
- regulator-name =
- "avdd_dsi_csi,pwrdet_mipi";
+ regulator-name = "+V1.2_CSI";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
- /* +V1.2_VDD_RTC */
ldo4_reg: ldo4 {
- regulator-name = "vdd_rtc";
+ regulator-name = "+V1.2_VDD_RTC";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
@@ -555,10 +547,10 @@
/*
* +V2.8_AVDD_VDAC:
- * only required for analog RGB
+ * only required for (unsupported) analog RGB
*/
ldo5_reg: ldo5 {
- regulator-name = "avdd_vdac";
+ regulator-name = "+V2.8_AVDD_VDAC";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
@@ -570,22 +562,20 @@
* granularity
*/
ldo6_reg: ldo6 {
- regulator-name = "avdd_plle";
+ regulator-name = "+V1.05_AVDD_PLLE";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
- /* +V1.2_AVDD_PLL */
ldo7_reg: ldo7 {
- regulator-name = "avdd_pll";
+ regulator-name = "+V1.2_AVDD_PLL";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
- /* +V1.0_VDD_DDR_HS */
ldo8_reg: ldo8 {
- regulator-name = "vdd_ddr_hs";
+ regulator-name = "+V1.0_VDD_DDR_HS";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
@@ -738,50 +728,40 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- avdd_hdmi_pll_1v8_reg: regulator@100 {
- compatible = "regulator-fixed";
- reg = <100>;
- regulator-name = "+V1.8_AVDD_HDMI_PLL";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- enable-active-high;
- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vio_reg>;
- };
+ reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
+ compatible = "regulator-fixed";
+ regulator-name = "+V1.8_AVDD_HDMI_PLL";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <®_1v8_vio>;
+ };
- sys_3v3_reg: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- regulator-name = "3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
+ reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3_AVDD_HDMI";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <®_module_3v3>;
+ };
- avdd_hdmi_3v3_reg: regulator@102 {
- compatible = "regulator-fixed";
- reg = <102>;
- regulator-name = "+V3.3_AVDD_HDMI";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
+ reg_5v0_charge_pump: regulator-5v0-charge-pump {
+ compatible = "regulator-fixed";
+ regulator-name = "+V5.0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- charge_pump_5v0_reg: regulator@103 {
- compatible = "regulator-fixed";
- reg = <103>;
- regulator-name = "5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ reg_module_3v3: regulator-module-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
};
sound {
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 09/28] ARM: tegra: apalis_t30: add missing regulators
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (7 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 08/28] ARM: tegra: apalis_t30: regulator clean-up Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 10/28] ARM: tegra: apalis_t30: annotate uarts Marcel Ziswiler
` (18 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add missing regulators:
- reg_module_3v3_audio being VDDA supply of SGTL5000
- VDDD supply of SGTL5000 actually being reg_1v8_vio
- carrier board HDMI supply being reg_5v0
- carrier board reg_3v3 actually being backlight and panel power supply
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 10 ++++++++++
arch/arm/boot/dts/tegra30-apalis.dtsi | 11 ++++++++++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 85e6adc82515..05f3656c058c 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -47,6 +47,7 @@
};
hdmi@54280000 {
status = "okay";
+ hdmi-supply = <®_5v0>;
};
};
@@ -191,6 +192,7 @@
default-brightness-level = <6>;
/* BKL1_ON */
enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <®_3v3>;
};
gpio-keys {
@@ -213,6 +215,7 @@
compatible = "edt,et057090dhu", "simple-panel";
backlight = <&backlight>;
+ power-supply = <®_3v3>;
};
pwmleds {
@@ -237,6 +240,13 @@
};
};
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V_SW";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5V_SW";
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 45c0066984fe..ef181d13be31 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -463,7 +463,8 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
- VDDA-supply = <®_module_3v3>;
+ VDDA-supply = <®_module_3v3_audio>;
+ VDDD-supply = <®_1v8_vio>;
VDDIO-supply = <®_module_3v3>;
clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
};
@@ -764,6 +765,14 @@
regulator-always-on;
};
+ reg_module_3v3_audio: regulator-module-3v3-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3_AUDIO_AVDD_S";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
sound {
compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
"nvidia,tegra-audio-sgtl5000";
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 10/28] ARM: tegra: apalis_t30: annotate uarts
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (8 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 09/28] ARM: tegra: apalis_t30: add missing regulators Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 11/28] ARM: tegra: apalis_t30: drop unused cami2c label Marcel Ziswiler
` (17 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Annotate UARTs.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 05f3656c058c..37c7db35ab1f 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -51,20 +51,24 @@
};
};
+ /* Apalis UART1 */
serial@70006000 {
status = "okay";
};
+ /* Apalis UART2 */
serial@70006040 {
compatible = "nvidia,tegra30-hsuart";
status = "okay";
};
+ /* Apalis UART3 */
serial@70006200 {
compatible = "nvidia,tegra30-hsuart";
status = "okay";
};
+ /* Apalis UART4 */
serial@70006300 {
compatible = "nvidia,tegra30-hsuart";
status = "okay";
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 11/28] ARM: tegra: apalis_t30: drop unused cami2c label
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (9 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 10/28] ARM: tegra: apalis_t30: annotate uarts Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 12/28] ARM: tegra: apalis_t30: white-space clean-up Marcel Ziswiler
` (16 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Drop unused cami2c label.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 37c7db35ab1f..ba178632d82c 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -104,7 +104,7 @@
* CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
* carrier board)
*/
- cami2c: i2c@7000c500 {
+ i2c@7000c500 {
status = "okay";
clock-frequency = <400000>;
};
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 12/28] ARM: tegra: apalis_t30: white-space clean-up
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (10 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 11/28] ARM: tegra: apalis_t30: drop unused cami2c label Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 13/28] ARM: tegra: apalis_t30: drop unused mmc1/sd1 labels Marcel Ziswiler
` (15 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
White-space clean-up.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index ba178632d82c..74d588561d9f 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -118,6 +118,7 @@
spi@7000d400 {
status = "okay";
spi-max-frequency = <25000000>;
+
spidev0: spidev@1 {
compatible = "spidev";
reg = <1>;
@@ -129,6 +130,7 @@
spi@7000dc00 {
status = "okay";
spi-max-frequency = <25000000>;
+
spidev1: spidev@2 {
compatible = "spidev";
reg = <2>;
@@ -189,7 +191,6 @@
backlight: backlight {
compatible = "pwm-backlight";
-
/* PWM_BKL1 */
pwms = <&pwm 0 5000000>;
brightness-levels = <255 231 223 207 191 159 127 0>;
@@ -217,7 +218,6 @@
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
compatible = "edt,et057090dhu", "simple-panel";
-
backlight = <&backlight>;
power-supply = <®_3v3>;
};
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 13/28] ARM: tegra: apalis_t30: drop unused mmc1/sd1 labels
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (11 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 12/28] ARM: tegra: apalis_t30: white-space clean-up Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 14/28] ARM: tegra: apalis_t30: annotate mmc1/sd1 Marcel Ziswiler
` (14 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Drop unused mmc1/sd1 labels.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 74d588561d9f..078b1061fb26 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -142,7 +142,7 @@
status = "okay";
};
- sd1: sdhci@78000000 {
+ sdhci@78000000 {
status = "okay";
bus-width = <4>;
/* SD1_CD# */
@@ -150,7 +150,7 @@
no-1-8-v;
};
- mmc1: sdhci@78000400 {
+ sdhci@78000400 {
status = "okay";
bus-width = <8>;
/* MMC1_CD# */
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 14/28] ARM: tegra: apalis_t30: annotate mmc1/sd1
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (12 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 13/28] ARM: tegra: apalis_t30: drop unused mmc1/sd1 labels Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 15/28] ARM: tegra: apalis_t30: move dr_mode property from phy to controller Marcel Ziswiler
` (13 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Annotate MMC1/SD1.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 078b1061fb26..a1ae4c3ee39c 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -142,6 +142,7 @@
status = "okay";
};
+ /* Apalis SD1 */
sdhci@78000000 {
status = "okay";
bus-width = <4>;
@@ -150,6 +151,7 @@
no-1-8-v;
};
+ /* Apalis MMC1 */
sdhci@78000400 {
status = "okay";
bus-width = <8>;
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 15/28] ARM: tegra: apalis_t30: move dr_mode property from phy to controller
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (13 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 14/28] ARM: tegra: apalis_t30: annotate mmc1/sd1 Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 16/28] ARM: tegra: apalis_t30: reorder backlight properties Marcel Ziswiler
` (12 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Move dr_mode property from USB PHY node to controller.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index a1ae4c3ee39c..4bb571bffc7f 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -163,11 +163,11 @@
/* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
usb@7d000000 {
status = "okay";
+ dr_mode = "otg";
};
usb-phy@7d000000 {
status = "okay";
- dr_mode = "otg";
vbus-supply = <®_usbo1_vbus>;
};
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 16/28] ARM: tegra: apalis_t30: reorder backlight properties
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (14 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 15/28] ARM: tegra: apalis_t30: move dr_mode property from phy to controller Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 17/28] ARM: tegra: apalis_t30: drop pwmleds Marcel Ziswiler
` (11 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reorder backlight properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 4bb571bffc7f..c4153e8e8b8c 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -193,13 +193,12 @@
backlight: backlight {
compatible = "pwm-backlight";
- /* PWM_BKL1 */
- pwms = <&pwm 0 5000000>;
brightness-levels = <255 231 223 207 191 159 127 0>;
default-brightness-level = <6>;
/* BKL1_ON */
enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
power-supply = <®_3v3>;
+ pwms = <&pwm 0 5000000>; /* BKL1_PWM */
};
gpio-keys {
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 17/28] ARM: tegra: apalis_t30: drop pwmleds
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (15 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 16/28] ARM: tegra: apalis_t30: reorder backlight properties Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 18/28] ARM: tegra: apalis_t30: pinmux clean-up Marcel Ziswiler
` (10 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Drop pwmleds in favour of using regular PWMs.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 22 ----------------------
1 file changed, 22 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index c4153e8e8b8c..6978e3626fae 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -223,28 +223,6 @@
power-supply = <®_3v3>;
};
- pwmleds {
- compatible = "pwm-leds";
-
- pwm1 {
- label = "PWM1";
- pwms = <&pwm 3 19600>;
- max-brightness = <255>;
- };
-
- pwm2 {
- label = "PWM2";
- pwms = <&pwm 2 19600>;
- max-brightness = <255>;
- };
-
- pwm3 {
- label = "PWM3";
- pwms = <&pwm 1 19600>;
- max-brightness = <255>;
- };
- };
-
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3.3V_SW";
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 18/28] ARM: tegra: apalis_t30: pinmux clean-up
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (16 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 17/28] ARM: tegra: apalis_t30: drop pwmleds Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 19/28] ARM: tegra: apalis_t30: add missing pinmux Marcel Ziswiler
` (9 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Clean-up pinmuxing:
- white-space clean-up
- explicitly disable input of BKL1_PWM and BKL1_PWM_EN#
- annotate Apalis I2C3 usage for CAM
- get rid of nvidia,lock property
- add missing eMMC sdmmc4_cmd_pt7 and explicitly enable input
- explicitly disable lcd_dc1_pd2 (e.g. LM95245 I2C address pin)
- annotate TOUCH_PEN_INT# being on-module
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index ef181d13be31..ac87eeebab03 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -68,10 +68,10 @@
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
dap3_fs_pp0 {
- nvidia,pins = "dap3_fs_pp0",
- "dap3_sclk_pp3",
- "dap3_din_pp1",
- "dap3_dout_pp2";
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_sclk_pp3",
+ "dap3_din_pp1",
+ "dap3_dout_pp2";
nvidia,function = "i2s2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -91,6 +91,7 @@
nvidia,function = "pwm0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
uart3_cts_n_pa1 {
@@ -98,6 +99,7 @@
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* Apalis CAN1 on SPI6 */
@@ -163,7 +165,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
- /* Apalis I2C3 */
+ /* Apalis I2C3 (CAM) */
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1",
"cam_i2c_sda_pbb2";
@@ -171,7 +173,6 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
@@ -368,10 +369,12 @@
/* eMMC (On-module) */
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
+ "sdmmc4_cmd_pt7",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
@@ -385,6 +388,7 @@
nvidia,function = "sdmmc4";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* LVDS Transceiver Configuration */
@@ -397,7 +401,6 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pbb3 {
nvidia,pins = "pbb3",
@@ -408,7 +411,6 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* Power I2C (On-module) */
@@ -419,7 +421,6 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
@@ -431,12 +432,12 @@
lcd_dc1_pd2 {
nvidia,pins = "lcd_dc1_pd2";
nvidia,function = "rsvd3";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
- /* TOUCH_PEN_INT# */
+ /* TOUCH_PEN_INT# (On-module) */
pv0 {
nvidia,pins = "pv0";
nvidia,function = "rsvd1";
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 19/28] ARM: tegra: apalis_t30: add missing pinmux
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (17 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 18/28] ARM: tegra: apalis_t30: pinmux clean-up Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 20/28] ARM: tegra: apalis_t30: use proper irq-gpio for stmpe811 Marcel Ziswiler
` (8 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Explicitly mux all T30 SoC balls now:
- Apalis GPIO
- Apalis HDMI1
- Apalis I2C1
- Apalis I2C2 (DDC)
- Apalis LCD1
- Apalis Parallel Camera
- Apalis SATA1_ACT#
- Apalis SPDIF1
- Apalis TS (Low-speed type specific)
- Apalis USBH_EN
- Apalis USBH_OC#
- Apalis VGA1
- on-module i210/i211 LAN control signals
- not connected and therefore disabled signals
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 370 ++++++++++++++++++++++++++++++++++
1 file changed, 370 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index ac87eeebab03..ad48b0daa0f8 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -165,6 +165,68 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
+ /* Apalis GPIO */
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0",
+ "kb_col1_pq1",
+ "kb_row10_ps2",
+ "kb_row11_ps3",
+ "kb_row12_ps4",
+ "kb_row13_ps5",
+ "kb_row14_ps6",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /* Multiplexed and therefore disabled */
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis HDMI1 */
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis I2C1 */
+ gen1_i2c_scl_pc4 {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis I2C2 (DDC) */
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
/* Apalis I2C3 (CAM) */
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -176,6 +238,42 @@
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
+ /* Apalis LCD1 */
+ lcd_d0_pe0 {
+ nvidia,pins = "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_pclk_pb3",
+ "lcd_vsync_pj4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
/* Apalis MMC1 */
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
@@ -206,6 +304,77 @@
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
+ /* Apalis Parallel Camera */
+ cam_mclk_pcc0 {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_vsync_pd6 {
+ nvidia,pins = "vi_d0_pt4",
+ "vi_d1_pd5",
+ "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d4_pl2",
+ "vi_d5_pl3",
+ "vi_d6_pl4",
+ "vi_d7_pl5",
+ "vi_d8_pl6",
+ "vi_d9_pl7",
+ "vi_d10_pt2",
+ "vi_d11_pt3",
+ "vi_hsync_pd7",
+ "vi_pclk_pt0",
+ "vi_vsync_pd6";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /* Multiplexed and therefore disabled */
+ kb_col2_pq2 {
+ nvidia,pins = "kb_col2_pq2",
+ "kb_col3_pq3",
+ "kb_col4_pq4",
+ "kb_row4_pr4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0",
+ "kb_row1_pr1",
+ "kb_row2_pr2",
+ "kb_row3_pr3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row5_pr5 {
+ nvidia,pins = "kb_row5_pr5",
+ "kb_row6_pr6",
+ "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /*
+ * VI level-shifter direction
+ * (pull-down => default direction input)
+ */
+ vi_mclk_pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
/* Apalis PWM1 */
pu6 {
nvidia,pins = "pu6";
@@ -246,6 +415,15 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
+ /* Apalis SATA1_ACT# */
+ pex_l0_prsnt_n_pdd0 {
+ nvidia,pins = "pex_l0_prsnt_n_pdd0";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
/* Apalis SD1 */
sdmmc1_clk_pz0 {
nvidia,pins = "sdmmc1_clk_pz0";
@@ -272,6 +450,16 @@
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
+ /* Apalis SPDIF1 */
+ spdif_out_pk5 {
+ nvidia,pins = "spdif_out_pk5",
+ "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
/* Apalis SPI1 */
spi1_sck_px5 {
nvidia,pins = "spi1_sck_px5",
@@ -294,6 +482,28 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
+ /*
+ * Apalis TS (Low-speed type specific)
+ * pins may be used as GPIOs
+ */
+ kb_col5_pq5 {
+ nvidia,pins = "kb_col5_pq5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col6_pq6 {
+ nvidia,pins = "kb_col6_pq6",
+ "kb_col7_pq7",
+ "kb_row8_ps0",
+ "kb_row9_ps1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
/* Apalis UART1 */
ulpi_data0 {
nvidia,pins = "ulpi_data0_po1",
@@ -338,6 +548,24 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
+ /* Apalis USBH_EN */
+ pex_l0_rst_n_pdd1 {
+ nvidia,pins = "pex_l0_rst_n_pdd1";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBH_OC# */
+ pex_l0_clkreq_n_pdd2 {
+ nvidia,pins = "pex_l0_clkreq_n_pdd2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
/* Apalis USBO1_EN */
gen2_i2c_scl_pt5 {
nvidia,pins = "gen2_i2c_scl_pt5";
@@ -357,6 +585,16 @@
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
+ /* Apalis VGA1 not supported and therefore disabled */
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
/* Apalis WAKE1_MICO */
pv1 {
nvidia,pins = "pv1";
@@ -391,6 +629,33 @@
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
+ /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
+ pex_l2_prsnt_n_pdd7 {
+ nvidia,pins = "pex_l2_prsnt_n_pdd7",
+ "pex_l2_rst_n_pcc6";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
+ pex_wake_n_pdd3 {
+ nvidia,pins = "pex_wake_n_pdd3",
+ "pex_l2_clkreq_n_pcc7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /* LAN i210/i211 SMB_ALERT_N (On-module) */
+ sys_clk_req_pz5 {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
/* LVDS Transceiver Configuration */
pbb0 {
nvidia,pins = "pbb0",
@@ -413,6 +678,111 @@
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
+ /* Not connected and therefore disabled */
+ clk_32k_out_pa0 {
+ nvidia,pins = "clk3_out_pee0",
+ "clk3_req_pee1",
+ "clk_32k_out_pa0",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_fs_pp4",
+ "dap4_sclk_pp7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5",
+ "lcd_dc0_pn6",
+ "lcd_m1_pw1",
+ "lcd_pwr1_pc1",
+ "pex_l1_clkreq_n_pdd6",
+ "pex_l1_prsnt_n_pdd4",
+ "pex_l1_rst_n_pdd5";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad4_pg4",
+ "gmi_ad5_pg5",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7",
+ "gmi_ad8_ph0",
+ "gmi_ad9_ph1",
+ "gmi_ad10_ph2",
+ "gmi_ad11_ph3",
+ "gmi_ad12_ph4",
+ "gmi_ad13_ph5",
+ "gmi_ad14_ph6",
+ "gmi_ad15_ph7",
+ "gmi_adv_n_pk0",
+ "gmi_clk_pk1",
+ "gmi_cs4_n_pk2",
+ "gmi_cs2_n_pk3",
+ "gmi_dqs_pi2",
+ "gmi_iordy_pi5",
+ "gmi_oe_n_pi1",
+ "gmi_wait_pi7",
+ "gmi_wr_n_pi0",
+ "lcd_cs1_n_pw0",
+ "pu0",
+ "pu1",
+ "pu2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs0_n_pj0 {
+ nvidia,pins = "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "sata";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs7_n_pi6 {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "gmi_alt";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pwr2_pc6",
+ "lcd_wr_n_pz3";
+ nvidia,function = "hdcp";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_cts_n_pj5 {
+ nvidia,pins = "uart2_cts_n_pj5",
+ "uart2_rts_n_pj6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
/* Power I2C (On-module) */
pwr_i2c_scl_pz6 {
nvidia,pins = "pwr_i2c_scl_pz6",
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 20/28] ARM: tegra: apalis_t30: use proper irq-gpio for stmpe811
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (18 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 19/28] ARM: tegra: apalis_t30: add missing pinmux Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 21/28] ARM: tegra: apalis_t30: further lm95245 temperature sensor annotation Marcel Ziswiler
` (7 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Use proper irq-gpio for stmpe811 touch controller.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index ad48b0daa0f8..ab4fe7491bbf 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -959,8 +959,7 @@
stmpe811@41 {
compatible = "st,stmpe811";
reg = <0x41>;
- interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
+ irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
id = <0>;
blocks = <0x5>;
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 21/28] ARM: tegra: apalis_t30: further lm95245 temperature sensor annotation
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (19 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 20/28] ARM: tegra: apalis_t30: use proper irq-gpio for stmpe811 Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 22/28] ARM: tegra: apalis_t30: add i2c-thermtrip Marcel Ziswiler
` (6 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Further LM95245 temperature sensor annotation.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index ab4fe7491bbf..4e8ea1a8d9ec 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -993,7 +993,7 @@
/*
* LM95245 temperature sensor
- * Note: OVERT_N directly connected to PMIC PWRDN
+ * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
*/
temp-sensor@4c {
compatible = "national,lm95245";
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 22/28] ARM: tegra: apalis_t30: add i2c-thermtrip
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (20 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 21/28] ARM: tegra: apalis_t30: further lm95245 temperature sensor annotation Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-25 11:11 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 23/28] ARM: tegra: apalis_t30: add proper emmc vmmc and vqmmc supplies Marcel Ziswiler
` (5 subsequent siblings)
27 siblings, 1 reply; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add i2c-thermtrip which would set the DEV_OFF bit in the DCDC control
register of the TPS65911 PMIC.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 4e8ea1a8d9ec..f8caf3f07fff 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -1055,6 +1055,14 @@
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
+
+ /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x2d>;
+ nvidia,reg-addr = <0x3e>;
+ nvidia,reg-data = <0x1>;
+ };
};
ahub@70080000 {
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 23/28] ARM: tegra: apalis_t30: add proper emmc vmmc and vqmmc supplies
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (21 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 22/28] ARM: tegra: apalis_t30: add i2c-thermtrip Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 24/28] ARM: tegra: apalis_t30: enable emmc ddr52 mode Marcel Ziswiler
` (4 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add proper eMMC vmmc and vqmmc supplies e.g. fixing signalling voltage.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index f8caf3f07fff..d50fcb69dd38 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -1078,6 +1078,8 @@
#size-cells = <0>;
bus-width = <8>;
non-removable;
+ vmmc-supply = <®_module_3v3>; /* VCC */
+ vqmmc-supply = <®_1v8_vio>; /* VCCQ */
emmc: emmc@0 {
reg = <0>;
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 24/28] ARM: tegra: apalis_t30: enable emmc ddr52 mode
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (22 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 23/28] ARM: tegra: apalis_t30: add proper emmc vmmc and vqmmc supplies Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 25/28] ARM: tegra: apalis_t30: rename clk to clock Marcel Ziswiler
` (3 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add mmc-ddr-1_8v property enabling eMMC DDR52 mode.
root@apalis-t30:~# cat /sys/kernel/debug/mmc1/ios
clock: 52000000 Hz
actual clock: 52000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 8 (mmc DDR52)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
root@apalis-t30:~# hdparm -t /dev/mmcblk1
/dev/mmcblk1:
Timing buffered disk reads: 232 MB in 3.01 seconds = 77.10 MB/sec
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index d50fcb69dd38..5f5a287eb535 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -1080,6 +1080,7 @@
non-removable;
vmmc-supply = <®_module_3v3>; /* VCC */
vqmmc-supply = <®_1v8_vio>; /* VCCQ */
+ mmc-ddr-1_8v;
emmc: emmc@0 {
reg = <0>;
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 25/28] ARM: tegra: apalis_t30: rename clk to clock
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (23 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 24/28] ARM: tegra: apalis_t30: enable emmc ddr52 mode Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 26/28] ARM: tegra: apalis_t30: line break long compatible property line Marcel Ziswiler
` (2 subsequent siblings)
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Rename clk to clock.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 5f5a287eb535..ee6750247c57 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -1094,14 +1094,14 @@
#address-cells = <1>;
#size-cells = <0>;
- clk32k_in: clk@0 {
+ clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
- clk16m: clk@1 {
+ clk16m: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 26/28] ARM: tegra: apalis_t30: line break long compatible property line
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (24 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 25/28] ARM: tegra: apalis_t30: rename clk to clock Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 27/28] ARM: tegra: apalis_t30: fix pcie switch vendor compatible Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 28/28] ARM: tegra: apalis_t30: support v1.1 hardware revision Marcel Ziswiler
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Line break long compatible property line.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 6978e3626fae..83949ac3cc07 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -6,7 +6,8 @@
/ {
model = "Toradex Apalis T30 on Apalis Evaluation Board";
- compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", "nvidia,tegra30";
+ compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30",
+ "nvidia,tegra30";
aliases {
rtc0 = "/i2c@7000c000/rtc@68";
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 27/28] ARM: tegra: apalis_t30: fix pcie switch vendor compatible
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (25 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 26/28] ARM: tegra: apalis_t30: line break long compatible property line Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 28/28] ARM: tegra: apalis_t30: support v1.1 hardware revision Marcel Ziswiler
27 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Thierry Reding, Jonathan Hunter, Rob Herring,
Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
PLX got bought by Broadcom therefore fix device tree compatible string
vendor which silences the following checkpatch.pl warning:
WARNING: DT compatible string vendor "plx" appears un-documented
-- check ./Documentation/devicetree/bindings/vendor-prefixes.txt
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 83949ac3cc07..2c4fee53425e 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -88,7 +88,7 @@
clock-frequency = <400000>;
pcie-switch@58 {
- compatible = "plx,pex8605";
+ compatible = "brcm,pex8605";
reg = <0x58>;
};
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH 28/28] ARM: tegra: apalis_t30: support v1.1 hardware revision
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
` (26 preceding siblings ...)
2018-07-22 16:49 ` [PATCH 27/28] ARM: tegra: apalis_t30: fix pcie switch vendor compatible Marcel Ziswiler
@ 2018-07-22 16:49 ` Marcel Ziswiler
2018-07-31 21:06 ` Rob Herring
27 siblings, 1 reply; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-22 16:49 UTC (permalink / raw)
To: devicetree, linux-tegra, linux-kernel
Cc: Marcel Ziswiler, Mikko Perttunen, Thierry Reding,
Jonathan Hunter, Rob Herring, Mark Rutland
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Support the V1.1 hardware revisions with the following change:
Changed power rail for MMC1 interface to a 3.3V/1.8V switchable rail in
order to be able to run UHS SD cards in ultra high speed 1.8V mode.
[ 207.502011] mmc2: host does not support reading read-only switch,
assuming write-enable
[ 207.517011] mmc2: new ultra high speed SDR104 SDHC card at address
aaaa
[ 207.534190] mmcblk2: mmc2:aaaa SE32G 29.7 GiB
[ 207.545096] mmcblk2: p1
root@apalis-t30:~# cat /sys/kernel/debug/mmc2/ios
clock: 208000000 Hz
actual clock: 204000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
root@apalis-t30:~# hdparm -t /dev/mmcblk2
/dev/mmcblk2:
Timing buffered disk reads: 256 MB in 3.02 seconds = 84.71 MB/sec
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
Documentation/devicetree/bindings/arm/tegra.txt | 2 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 280 ++++++
arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 1189 +++++++++++++++++++++++
arch/arm/boot/dts/tegra30-apalis.dtsi | 3 +-
5 files changed, 1473 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
create mode 100644 arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index 32f62bb7006d..1073a5e66122 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -47,6 +47,8 @@ board-specific compatible values:
nvidia,ventana
toradex,apalis_t30
toradex,apalis_t30-eval
+ toradex,apalis_t30-v1.1
+ toradex,apalis_t30-v1.1-eval
toradex,apalis-tk1
toradex,apalis-tk1-eval
toradex,colibri_t20-512
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ea25a14f3bad..93de8ca32873 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1068,6 +1068,7 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-ventana.dtb
dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-apalis-eval.dtb \
+ tegra30-apalis-v1.1-eval.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
new file mode 100644
index 000000000000..bf952a09c650
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra30-apalis-v1.1.dtsi"
+
+/ {
+ model = "Toradex Apalis T30 on Apalis Evaluation Board";
+ compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval",
+ "toradex,apalis_t30-v1.1", "toradex,apalis_t30",
+ "nvidia,tegra30";
+
+ aliases {
+ rtc0 = "/i2c@7000c000/rtc@68";
+ rtc1 = "/i2c@7000d000/tps65911@2d";
+ rtc2 = "/rtc@7000e000";
+ serial0 = &uarta;
+ serial1 = &uartb;
+ serial2 = &uartc;
+ serial3 = &uartd;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ pcie@3000 {
+ status = "okay";
+
+ pci@1,0 {
+ status = "okay";
+ };
+
+ pci@2,0 {
+ status = "okay";
+ };
+
+ pci@3,0 {
+ status = "okay";
+ };
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+ nvidia,panel = <&panel>;
+ };
+ };
+ hdmi@54280000 {
+ status = "okay";
+ hdmi-supply = <®_5v0>;
+ };
+ };
+
+ /* Apalis UART1 */
+ serial@70006000 {
+ status = "okay";
+ };
+
+ /* Apalis UART2 */
+ serial@70006040 {
+ compatible = "nvidia,tegra30-hsuart";
+ status = "okay";
+ };
+
+ /* Apalis UART3 */
+ serial@70006200 {
+ compatible = "nvidia,tegra30-hsuart";
+ status = "okay";
+ };
+
+ /* Apalis UART4 */
+ serial@70006300 {
+ compatible = "nvidia,tegra30-hsuart";
+ status = "okay";
+ };
+
+ pwm@7000a000 {
+ status = "okay";
+ };
+
+ /*
+ * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
+ * board)
+ */
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pcie-switch@58 {
+ compatible = "brcm,pex8605";
+ reg = <0x58>;
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+ };
+
+ /* GEN2_I2C: unused */
+
+ /*
+ * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
+ * carrier board)
+ */
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
+ hdmiddc: i2c@7000c700 {
+ status = "okay";
+ };
+
+ /* SPI1: Apalis SPI1 */
+ spi@7000d400 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ spidev0: spidev@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency = <25000000>;
+ };
+ };
+
+ /* SPI5: Apalis SPI2 */
+ spi@7000dc00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ spidev1: spidev@2 {
+ compatible = "spidev";
+ reg = <2>;
+ spi-max-frequency = <25000000>;
+ };
+ };
+
+ hda@70030000 {
+ status = "okay";
+ };
+
+ /* Apalis SD1 */
+ sdhci@78000000 {
+ status = "okay";
+ bus-width = <4>;
+ /* SD1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ };
+
+ /* Apalis MMC1 */
+ sdhci@78000400 {
+ status = "okay";
+ bus-width = <8>;
+ /* MMC1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <®_vddio_sdmmc3>;
+ };
+
+ /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
+ usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ vbus-supply = <®_usbo1_vbus>;
+ };
+
+ /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
+ usb@7d004000 {
+ status = "okay";
+ };
+
+ usb-phy@7d004000 {
+ status = "okay";
+ vbus-supply = <®_usbh_vbus>;
+ };
+
+ /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
+ usb@7d008000 {
+ status = "okay";
+ };
+
+ usb-phy@7d008000 {
+ status = "okay";
+ vbus-supply = <®_usbh_vbus>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <255 231 223 207 191 159 127 0>;
+ default-brightness-level = <6>;
+ /* BKL1_ON */
+ enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <®_3v3>;
+ pwms = <&pwm 0 5000000>; /* BKL1_PWM */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wakeup {
+ label = "WAKE1_MICO";
+ gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ panel: panel {
+ /*
+ * edt,et057090dhu: EDT 5.7" LCD TFT
+ * edt,et070080dh6: EDT 7.0" LCD TFT
+ */
+ compatible = "edt,et057090dhu", "simple-panel";
+ backlight = <&backlight>;
+ power-supply = <®_3v3>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V_SW";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V_SW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ /* USBO1_EN */
+ reg_usbo1_vbus: regulator-usbo1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_USBO1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_5v0>;
+ };
+
+ /* USBH_EN */
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_5v0>;
+ };
+
+ /*
+ * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on
+ * EN_+3.3_SDMMC3 GPIO
+ */
+ reg_vddio_sdmmc3: regulator-vddio-sdmmc3 {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_SDMMC3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-type = "voltage";
+ gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0
+ 3300000 0x1>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vddio_sdmmc_1v8_reg>;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
new file mode 100644
index 000000000000..8b69e9185cee
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
@@ -0,0 +1,1189 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+#include "tegra30.dtsi"
+
+/*
+ * Toradex Apalis T30 Module Device Tree
+ * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B;
+ * 2GB: V1.1A, V1.1B
+ */
+/ {
+ model = "Toradex Apalis T30";
+ compatible = "toradex,apalis_t30", "nvidia,tegra30";
+
+ memory@80000000 {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ pcie@3000 {
+ avdd-pexa-supply = <&vdd2_reg>;
+ avdd-pexb-supply = <&vdd2_reg>;
+ avdd-pex-pll-supply = <&vdd2_reg>;
+ avdd-plle-supply = <&ldo6_reg>;
+ hvdd-pex-supply = <®_module_3v3>;
+ vddio-pex-ctl-supply = <®_module_3v3>;
+ vdd-pexa-supply = <&vdd2_reg>;
+ vdd-pexb-supply = <&vdd2_reg>;
+
+ /* Apalis type specific */
+ pci@1,0 {
+ nvidia,num-lanes = <4>;
+ };
+
+ /* Apalis PCIe */
+ pci@2,0 {
+ nvidia,num-lanes = <1>;
+ };
+
+ /* I210/I211 Gigabit Ethernet Controller (on-module) */
+ pci@3,0 {
+ nvidia,num-lanes = <1>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+
+ host1x@50000000 {
+ hdmi@54280000 {
+ nvidia,ddc-i2c-bus = <&hdmiddc>;
+ nvidia,hpd-gpio =
+ <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+ pll-supply = <®_1v8_avdd_hdmi_pll>;
+ vdd-supply = <®_3v3_avdd_hdmi>;
+ };
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ /* Analogue Audio (On-module) */
+ clk1_out_pw4 {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0",
+ "dap3_sclk_pp3",
+ "dap3_din_pp1",
+ "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis BKL1_ON */
+ pv2 {
+ nvidia,pins = "pv2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis BKL1_PWM */
+ uart3_rts_n_pc0 {
+ nvidia,pins = "uart3_rts_n_pc0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
+ uart3_cts_n_pa1 {
+ nvidia,pins = "uart3_cts_n_pa1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis CAN1 on SPI6 */
+ spi2_cs0_n_px3 {
+ nvidia,pins = "spi2_cs0_n_px3",
+ "spi2_miso_px1",
+ "spi2_mosi_px0",
+ "spi2_sck_px2";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ /* CAN_INT1 */
+ spi2_cs1_n_pw2 {
+ nvidia,pins = "spi2_cs1_n_pw2";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis CAN2 on SPI4 */
+ gmi_a16_pj7 {
+ nvidia,pins = "gmi_a16_pj7",
+ "gmi_a17_pb0",
+ "gmi_a18_pb1",
+ "gmi_a19_pk7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /* CAN_INT2 */
+ spi2_cs2_n_pw3 {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis Digital Audio */
+ clk1_req_pee2 {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ clk2_out_pw5 {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_fs_pn0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis GPIO */
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0",
+ "kb_col1_pq1",
+ "kb_row10_ps2",
+ "kb_row11_ps3",
+ "kb_row12_ps4",
+ "kb_row13_ps5",
+ "kb_row14_ps6",
+ "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /* Multiplexed and therefore disabled */
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis HDMI1 */
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis I2C1 */
+ gen1_i2c_scl_pc4 {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis I2C2 (DDC) */
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis I2C3 (CAM) */
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis LCD1 */
+ lcd_d0_pe0 {
+ nvidia,pins = "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_pclk_pb3",
+ "lcd_vsync_pj4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis MMC1 */
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3_dat0_pb7 {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat4_pd1",
+ "sdmmc3_dat5_pd0",
+ "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ /* Apalis MMC1_CD# */
+ pv3 {
+ nvidia,pins = "pv3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis Parallel Camera */
+ cam_mclk_pcc0 {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ vi_vsync_pd6 {
+ nvidia,pins = "vi_d0_pt4",
+ "vi_d1_pd5",
+ "vi_d2_pl0",
+ "vi_d3_pl1",
+ "vi_d4_pl2",
+ "vi_d5_pl3",
+ "vi_d6_pl4",
+ "vi_d7_pl5",
+ "vi_d8_pl6",
+ "vi_d9_pl7",
+ "vi_d10_pt2",
+ "vi_d11_pt3",
+ "vi_hsync_pd7",
+ "vi_pclk_pt0",
+ "vi_vsync_pd6";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /* Multiplexed and therefore disabled */
+ kb_col2_pq2 {
+ nvidia,pins = "kb_col2_pq2",
+ "kb_col3_pq3",
+ "kb_col4_pq4",
+ "kb_row4_pr4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0",
+ "kb_row1_pr1",
+ "kb_row2_pr2",
+ "kb_row3_pr3";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row5_pr5 {
+ nvidia,pins = "kb_row5_pr5",
+ "kb_row6_pr6",
+ "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /*
+ * VI level-shifter direction
+ * (pull-down => default direction input)
+ */
+ vi_mclk_pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis PWM1 */
+ pu6 {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis PWM2 */
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis PWM3 */
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis PWM4 */
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis RESET_MOCI# */
+ gmi_rst_n_pi4 {
+ nvidia,pins = "gmi_rst_n_pi4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SATA1_ACT# */
+ pex_l0_prsnt_n_pdd0 {
+ nvidia,pins = "pex_l0_prsnt_n_pdd0";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SD1 */
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc1_cmd_pz1 {
+ nvidia,pins = "sdmmc1_cmd_pz1",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ /* Apalis SD1_CD# */
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis SPDIF1 */
+ spdif_out_pk5 {
+ nvidia,pins = "spdif_out_pk5",
+ "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis SPI1 */
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5",
+ "spi1_mosi_px4",
+ "spi1_miso_px7",
+ "spi1_cs0_n_px6";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SPI2 */
+ lcd_sck_pz4 {
+ nvidia,pins = "lcd_sck_pz4",
+ "lcd_sdout_pn5",
+ "lcd_sdin_pz2",
+ "lcd_cs0_n_pn4";
+ nvidia,function = "spi5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /*
+ * Apalis TS (Low-speed type specific)
+ * pins may be used as GPIOs
+ */
+ kb_col5_pq5 {
+ nvidia,pins = "kb_col5_pq5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col6_pq6 {
+ nvidia,pins = "kb_col6_pq6",
+ "kb_col7_pq7",
+ "kb_row8_ps0",
+ "kb_row9_ps1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis UART1 */
+ ulpi_data0 {
+ nvidia,pins = "ulpi_data0_po1",
+ "ulpi_data1_po2",
+ "ulpi_data2_po3",
+ "ulpi_data3_po4",
+ "ulpi_data4_po5",
+ "ulpi_data5_po6",
+ "ulpi_data6_po7",
+ "ulpi_data7_po0";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis UART2 */
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1",
+ "ulpi_nxt_py2",
+ "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis UART3 */
+ uart2_rxd_pc3 {
+ nvidia,pins = "uart2_rxd_pc3",
+ "uart2_txd_pc2";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis UART4 */
+ uart3_rxd_pw7 {
+ nvidia,pins = "uart3_rxd_pw7",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBH_EN */
+ pex_l0_rst_n_pdd1 {
+ nvidia,pins = "pex_l0_rst_n_pdd1";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBH_OC# */
+ pex_l0_clkreq_n_pdd2 {
+ nvidia,pins = "pex_l0_clkreq_n_pdd2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis USBO1_EN */
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5";
+ nvidia,function = "rsvd4";
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBO1_OC# */
+ gen2_i2c_sda_pt6 {
+ nvidia,pins = "gen2_i2c_sda_pt6";
+ nvidia,function = "rsvd4";
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis VGA1 not supported and therefore disabled */
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis WAKE1_MICO */
+ pv1 {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* eMMC (On-module) */
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4",
+ "sdmmc4_cmd_pt7",
+ "sdmmc4_rst_n_pcc3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* EN_+3.3_SDMMC3 */
+ uart2_cts_n_pj5 {
+ nvidia,pins = "uart2_cts_n_pj5";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
+ pex_l2_prsnt_n_pdd7 {
+ nvidia,pins = "pex_l2_prsnt_n_pdd7",
+ "pex_l2_rst_n_pcc6";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
+ pex_wake_n_pdd3 {
+ nvidia,pins = "pex_wake_n_pdd3",
+ "pex_l2_clkreq_n_pcc7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /* LAN i210/i211 SMB_ALERT_N (On-module) */
+ sys_clk_req_pz5 {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* LVDS Transceiver Configuration */
+ pbb0 {
+ nvidia,pins = "pbb0",
+ "pbb7",
+ "pcc1",
+ "pcc2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb3 {
+ nvidia,pins = "pbb3",
+ "pbb4",
+ "pbb5",
+ "pbb6";
+ nvidia,function = "displayb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Not connected and therefore disabled */
+ clk_32k_out_pa0 {
+ nvidia,pins = "clk3_out_pee0",
+ "clk3_req_pee1",
+ "clk_32k_out_pa0",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_fs_pp4",
+ "dap4_sclk_pp7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5",
+ "lcd_dc0_pn6",
+ "lcd_m1_pw1",
+ "lcd_pwr1_pc1",
+ "pex_l1_clkreq_n_pdd6",
+ "pex_l1_prsnt_n_pdd4",
+ "pex_l1_rst_n_pdd5";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad4_pg4",
+ "gmi_ad5_pg5",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7",
+ "gmi_ad8_ph0",
+ "gmi_ad9_ph1",
+ "gmi_ad10_ph2",
+ "gmi_ad11_ph3",
+ "gmi_ad12_ph4",
+ "gmi_ad13_ph5",
+ "gmi_ad14_ph6",
+ "gmi_ad15_ph7",
+ "gmi_adv_n_pk0",
+ "gmi_clk_pk1",
+ "gmi_cs4_n_pk2",
+ "gmi_cs2_n_pk3",
+ "gmi_dqs_pi2",
+ "gmi_iordy_pi5",
+ "gmi_oe_n_pi1",
+ "gmi_wait_pi7",
+ "gmi_wr_n_pi0",
+ "lcd_cs1_n_pw0",
+ "pu0",
+ "pu1",
+ "pu2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs0_n_pj0 {
+ nvidia,pins = "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "sata";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs7_n_pi6 {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "gmi_alt";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pwr2_pc6",
+ "lcd_wr_n_pz3";
+ nvidia,function = "hdcp";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_rts_n_pj6 {
+ nvidia,pins = "uart2_rts_n_pj6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Power I2C (On-module) */
+ pwr_i2c_scl_pz6 {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /*
+ * THERMD_ALERT#, unlatched I2C address pin of LM95245
+ * temperature sensor therefore requires disabling for
+ * now
+ */
+ lcd_dc1_pd2 {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* TOUCH_PEN_INT# (On-module) */
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
+ hdmiddc: i2c@7000c700 {
+ clock-frequency = <10000>;
+ };
+
+ /*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ /* SGTL5000 audio codec */
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_module_3v3_audio>;
+ VDDD-supply = <®_1v8_vio>;
+ VDDIO-supply = <®_module_3v3>;
+ clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
+ };
+
+ pmic: tps65911@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ vcc1-supply = <®_module_3v3>;
+ vcc2-supply = <®_module_3v3>;
+ vcc3-supply = <®_1v8_vio>;
+ vcc4-supply = <®_module_3v3>;
+ vcc5-supply = <®_module_3v3>;
+ vcc6-supply = <®_1v8_vio>;
+ vcc7-supply = <®_5v0_charge_pump>;
+ vccio-supply = <®_module_3v3>;
+
+ regulators {
+ vdd1_reg: vdd1 {
+ regulator-name = "+V1.35_VDDIO_DDR";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ vdd2_reg: vdd2 {
+ regulator-name = "+V1.05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vddctrl_reg: vddctrl {
+ regulator-name = "+V1.0_VDD_CPU";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ };
+
+ reg_1v8_vio: vio {
+ regulator-name = "+V1.8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ /*
+ * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3
+ * is off
+ */
+ vddio_sdmmc_1v8_reg: ldo1 {
+ regulator-name = "+VDDIO_SDMMC3_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ /*
+ * EN_+V3.3 switching via FET:
+ * +V3.3_AUDIO_AVDD_S, +V3.3
+ * see also +V3.3 fixed supply
+ */
+ ldo2_reg: ldo2 {
+ regulator-name = "EN_+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-name = "+V1.2_CSI";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-name = "+V1.2_VDD_RTC";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ /*
+ * +V2.8_AVDD_VDAC:
+ * only required for (unsupported) analog RGB
+ */
+ ldo5_reg: ldo5 {
+ regulator-name = "+V2.8_AVDD_VDAC";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ /*
+ * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
+ * but LDO6 can't set voltage in 50mV
+ * granularity
+ */
+ ldo6_reg: ldo6 {
+ regulator-name = "+V1.05_AVDD_PLLE";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "+V1.2_AVDD_PLL";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "+V1.0_VDD_DDR_HS";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ /* STMPE811 touch screen controller */
+ stmpe811@41 {
+ compatible = "st,stmpe811";
+ reg = <0x41>;
+ irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ id = <0>;
+ blocks = <0x5>;
+ irq-trigger = <0x1>;
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 8 sample average control */
+ st,ave-ctrl = <3>;
+ /* 7 length fractional part in z */
+ st,fraction-z = <7>;
+ /*
+ * 50 mA typical 80 mA max touchscreen drivers
+ * current limit value
+ */
+ st,i-drive = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC converstion time: 80 clocks */
+ st,sample-time = <4>;
+ /* 1 ms panel driver settling time */
+ st,settling = <3>;
+ /* 5 ms touch detect interrupt delay */
+ st,touch-det-delay = <5>;
+ };
+ };
+
+ /*
+ * LM95245 temperature sensor
+ * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
+ */
+ temp-sensor@4c {
+ compatible = "national,lm95245";
+ reg = <0x4c>;
+ };
+
+ /* SW: +V1.2_VDD_CORE */
+ tps62362@60 {
+ compatible = "ti,tps62362";
+ reg = <0x60>;
+
+ regulator-name = "tps62362-vout";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ti,vsel0-state-low;
+ /* VSEL1: EN_CORE_DVFS_N low for DVFS */
+ ti,vsel1-state-low;
+ };
+ };
+
+ /* SPI4: CAN2 */
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <10000000>;
+
+ can@1 {
+ compatible = "microchip,mcp2515";
+ reg = <1>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_RISING>;
+ spi-max-frequency = <10000000>;
+ };
+ };
+
+ /* SPI6: CAN1 */
+ spi@7000de00 {
+ status = "okay";
+ spi-max-frequency = <10000000>;
+
+ can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>;
+ spi-max-frequency = <10000000>;
+ };
+ };
+
+ pmc@7000e400 {
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <1>;
+ nvidia,cpu-pwr-good-time = <5000>;
+ nvidia,cpu-pwr-off-time = <5000>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <0>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+
+ /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x2d>;
+ nvidia,reg-addr = <0x3e>;
+ nvidia,reg-data = <0x1>;
+ };
+ };
+
+ ahub@70080000 {
+ i2s@70080500 {
+ status = "okay";
+ };
+ };
+
+ /* eMMC */
+ sdhci@78000600 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <8>;
+ non-removable;
+ vmmc-supply = <®_module_3v3>; /* VCC */
+ vqmmc-supply = <®_1v8_vio>; /* VCCQ */
+ mmc-ddr-1_8v;
+
+ emmc: emmc@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ clk16m: clock@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "clk16m";
+ };
+ };
+
+ reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
+ compatible = "regulator-fixed";
+ regulator-name = "+V1.8_AVDD_HDMI_PLL";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <®_1v8_vio>;
+ };
+
+ reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3_AVDD_HDMI";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <®_module_3v3>;
+ };
+
+ reg_5v0_charge_pump: regulator-5v0-charge-pump {
+ compatible = "regulator-fixed";
+ regulator-name = "+V5.0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_module_3v3: regulator-module-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_module_3v3_audio: regulator-module-3v3-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3_AUDIO_AVDD_S";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
+ "nvidia,tegra-audio-sgtl5000";
+ nvidia,model = "Toradex Apalis T30";
+ nvidia,audio-routing =
+ "Headphone Jack", "HP_OUT",
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack";
+ nvidia,i2s-controller = <&tegra_i2s2>;
+ nvidia,audio-codec = <&sgtl5000>;
+ clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+ <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index ee6750247c57..4c0a313f6a9d 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -3,8 +3,7 @@
/*
* Toradex Apalis T30 Module Device Tree
- * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
- * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
+ * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
*/
/ {
model = "Toradex Apalis T30";
--
2.14.4
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc
2018-07-22 16:49 ` [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc Marcel Ziswiler
@ 2018-07-24 14:03 ` Dmitry Osipenko
2018-07-24 14:26 ` Marcel Ziswiler
0 siblings, 1 reply; 35+ messages in thread
From: Dmitry Osipenko @ 2018-07-24 14:03 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-tegra, linux-kernel, Marcel Ziswiler,
Thierry Reding, Jonathan Hunter, Rob Herring, Mark Rutland
On Sunday, 22 July 2018 19:49:09 MSK Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Avoid eMMC issues by specifying broken-hpi.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
Is it a specific eMMC card model that has broken HPI or it is a host
controller bug?
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc
2018-07-24 14:03 ` Dmitry Osipenko
@ 2018-07-24 14:26 ` Marcel Ziswiler
2018-07-24 14:55 ` Dmitry Osipenko
0 siblings, 1 reply; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-24 14:26 UTC (permalink / raw)
To: digetx
Cc: thierry.reding, linux-kernel, mark.rutland, jonathanh,
linux-tegra, devicetree, robh+dt
On Tue, 2018-07-24 at 17:03 +0300, Dmitry Osipenko wrote:
> On Sunday, 22 July 2018 19:49:09 MSK Marcel Ziswiler wrote:
> > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> >
> > Avoid eMMC issues by specifying broken-hpi.
> >
> > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> >
> > ---
>
> Is it a specific eMMC card model that has broken HPI or it is a host
> controller bug?
That is a very good question. So far we only have confirmation that at
least some eMMCs from Hynix resp. SKHynix definitely do have bad
firmware. I also found out that ASUS resp. Google did disable HPI on
their Nexus 7 tablet. Therefore, we also disabled HPI quite a while ago
in our downstream BSPs which we successfully validated & verified doing
power cuts and running stress tests in our temperature chambers. I
guess we would have to run more extensive tests with mainline with and
without this setting to be able to really answer your question. For now
I just successfully run a few Apalis T30 and Colibri T30 modules with
this setting over the weekend doing both hdparm -t as well as dding
some urandom files to the eMMC in a loop without seeing any issues.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc
2018-07-24 14:26 ` Marcel Ziswiler
@ 2018-07-24 14:55 ` Dmitry Osipenko
2018-07-25 8:40 ` Marcel Ziswiler
0 siblings, 1 reply; 35+ messages in thread
From: Dmitry Osipenko @ 2018-07-24 14:55 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: thierry.reding, linux-kernel, mark.rutland, jonathanh,
linux-tegra, devicetree, robh+dt
On Tuesday, 24 July 2018 17:26:58 MSK Marcel Ziswiler wrote:
> On Tue, 2018-07-24 at 17:03 +0300, Dmitry Osipenko wrote:
>
> > On Sunday, 22 July 2018 19:49:09 MSK Marcel Ziswiler wrote:
> >
> > > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > >
> > > Avoid eMMC issues by specifying broken-hpi.
> > >
> > > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > >
> > > ---
> >
> >
> > Is it a specific eMMC card model that has broken HPI or it is a host
> > controller bug?
>
>
> That is a very good question. So far we only have confirmation that at
> least some eMMCs from Hynix resp. SKHynix definitely do have bad
> firmware. I also found out that ASUS resp. Google did disable HPI on
> their Nexus 7 tablet. Therefore, we also disabled HPI quite a while ago
> in our downstream BSPs which we successfully validated & verified doing
> power cuts and running stress tests in our temperature chambers. I
> guess we would have to run more extensive tests with mainline with and
> without this setting to be able to really answer your question. For now
> I just successfully run a few Apalis T30 and Colibri T30 modules with
> this setting over the weekend doing both hdparm -t as well as dding
> some urandom files to the eMMC in a loop without seeing any issues.
The broken-hpi quirk was added for the Hynix cards specifically in [0]. Maybe
you should just extend the mmc_ext_csd_fixups list in [1] with another OEM ID?
[0] https://patchwork.kernel.org/patch/9168455/
[1] drivers/mmc/core/quirks.h
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc
2018-07-24 14:55 ` Dmitry Osipenko
@ 2018-07-25 8:40 ` Marcel Ziswiler
0 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-25 8:40 UTC (permalink / raw)
To: digetx
Cc: jonathanh, linux-kernel, mark.rutland, robh+dt, thierry.reding,
linux-tegra, devicetree
On Tue, 2018-07-24 at 17:55 +0300, Dmitry Osipenko wrote:
> On Tuesday, 24 July 2018 17:26:58 MSK Marcel Ziswiler wrote:
> > On Tue, 2018-07-24 at 17:03 +0300, Dmitry Osipenko wrote:
> >
> > > On Sunday, 22 July 2018 19:49:09 MSK Marcel Ziswiler wrote:
> > >
> > > > From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > > >
> > > > Avoid eMMC issues by specifying broken-hpi.
> > > >
> > > > Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > > >
> > > > ---
> > >
> > >
> > > Is it a specific eMMC card model that has broken HPI or it is a
> > > host
> > > controller bug?
> >
> >
> > That is a very good question. So far we only have confirmation that
> > at
> > least some eMMCs from Hynix resp. SKHynix definitely do have bad
> > firmware. I also found out that ASUS resp. Google did disable HPI
> > on
> > their Nexus 7 tablet. Therefore, we also disabled HPI quite a while
> > ago
> > in our downstream BSPs which we successfully validated & verified
> > doing
> > power cuts and running stress tests in our temperature chambers. I
> > guess we would have to run more extensive tests with mainline with
> > and
> > without this setting to be able to really answer your question. For
> > now
> > I just successfully run a few Apalis T30 and Colibri T30 modules
> > with
> > this setting over the weekend doing both hdparm -t as well as dding
> > some urandom files to the eMMC in a loop without seeing any issues.
>
> The broken-hpi quirk was added for the Hynix cards specifically in
> [0]. Maybe
> you should just extend the mmc_ext_csd_fixups list in [1] with
> another OEM ID?
>
> [0] https://patchwork.kernel.org/patch/9168455/
> [1] drivers/mmc/core/quirks.h
Ah, interesting, somehow I missed how that works. Let me give that a
try and if it does work I may make use of this in a v2.
Thanks for the tip, Dmitry.
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 22/28] ARM: tegra: apalis_t30: add i2c-thermtrip
2018-07-22 16:49 ` [PATCH 22/28] ARM: tegra: apalis_t30: add i2c-thermtrip Marcel Ziswiler
@ 2018-07-25 11:11 ` Marcel Ziswiler
0 siblings, 0 replies; 35+ messages in thread
From: Marcel Ziswiler @ 2018-07-25 11:11 UTC (permalink / raw)
To: linux-kernel, linux-tegra, devicetree
Cc: jonathanh, mark.rutland, thierry.reding, robh+dt
On Sun, 2018-07-22 at 18:49 +0200, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Add i2c-thermtrip which would set the DEV_OFF bit in the DCDC control
> register of the TPS65911 PMIC.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> arch/arm/boot/dts/tegra30-apalis.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi
> b/arch/arm/boot/dts/tegra30-apalis.dtsi
> index 4e8ea1a8d9ec..f8caf3f07fff 100644
> --- a/arch/arm/boot/dts/tegra30-apalis.dtsi
> +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
> @@ -1055,6 +1055,14 @@
> nvidia,core-pwr-off-time = <0>;
> nvidia,core-power-req-active-high;
> nvidia,sys-clock-req-active-high;
> +
> + /* Set DEV_OFF bit in DCDC control register of
> TPS65911 PMIC */
> + i2c-thermtrip {
> + nvidia,i2c-controller-id = <4>;
> + nvidia,bus-addr = <0x2d>;
> + nvidia,reg-addr = <0x3e>;
When running some more tests I just realized that the reg-addr should
really be 0x3f instead. Will change this in a v2.
> + nvidia,reg-data = <0x1>;
> + };
> };
>
> ahub@70080000 {
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 28/28] ARM: tegra: apalis_t30: support v1.1 hardware revision
2018-07-22 16:49 ` [PATCH 28/28] ARM: tegra: apalis_t30: support v1.1 hardware revision Marcel Ziswiler
@ 2018-07-31 21:06 ` Rob Herring
0 siblings, 0 replies; 35+ messages in thread
From: Rob Herring @ 2018-07-31 21:06 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-tegra, linux-kernel, Marcel Ziswiler,
Mikko Perttunen, Thierry Reding, Jonathan Hunter, Mark Rutland
On Sun, Jul 22, 2018 at 06:49:36PM +0200, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Support the V1.1 hardware revisions with the following change:
>
> Changed power rail for MMC1 interface to a 3.3V/1.8V switchable rail in
> order to be able to run UHS SD cards in ultra high speed 1.8V mode.
>
> [ 207.502011] mmc2: host does not support reading read-only switch,
> assuming write-enable
> [ 207.517011] mmc2: new ultra high speed SDR104 SDHC card at address
> aaaa
> [ 207.534190] mmcblk2: mmc2:aaaa SE32G 29.7 GiB
> [ 207.545096] mmcblk2: p1
>
> root@apalis-t30:~# cat /sys/kernel/debug/mmc2/ios
> clock: 208000000 Hz
> actual clock: 204000000 Hz
> vdd: 21 (3.3 ~ 3.4 V)
> bus mode: 2 (push-pull)
> chip select: 0 (don't care)
> power mode: 2 (on)
> bus width: 2 (4 bits)
> timing spec: 6 (sd uhs SDR104)
> signal voltage: 1 (1.80 V)
> driver type: 0 (driver type B)
> root@apalis-t30:~# hdparm -t /dev/mmcblk2
>
> /dev/mmcblk2:
> Timing buffered disk reads: 256 MB in 3.02 seconds = 84.71 MB/sec
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Documentation/devicetree/bindings/arm/tegra.txt | 2 +
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 280 ++++++
> arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 1189 +++++++++++++++++++++++
> arch/arm/boot/dts/tegra30-apalis.dtsi | 3 +-
> 5 files changed, 1473 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
> create mode 100644 arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
Build your DTS files with W=12 and fix any new warnings.
>
> diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
> index 32f62bb7006d..1073a5e66122 100644
> --- a/Documentation/devicetree/bindings/arm/tegra.txt
> +++ b/Documentation/devicetree/bindings/arm/tegra.txt
> @@ -47,6 +47,8 @@ board-specific compatible values:
> nvidia,ventana
> toradex,apalis_t30
> toradex,apalis_t30-eval
> + toradex,apalis_t30-v1.1
> + toradex,apalis_t30-v1.1-eval
> toradex,apalis-tk1
> toradex,apalis-tk1-eval
> toradex,colibri_t20-512
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ea25a14f3bad..93de8ca32873 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1068,6 +1068,7 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
> tegra20-ventana.dtb
> dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
> tegra30-apalis-eval.dtb \
> + tegra30-apalis-v1.1-eval.dtb \
> tegra30-beaver.dtb \
> tegra30-cardhu-a02.dtb \
> tegra30-cardhu-a04.dtb \
> diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
> new file mode 100644
> index 000000000000..bf952a09c650
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
> @@ -0,0 +1,280 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include "tegra30-apalis-v1.1.dtsi"
> +
> +/ {
> + model = "Toradex Apalis T30 on Apalis Evaluation Board";
> + compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval",
> + "toradex,apalis_t30-v1.1", "toradex,apalis_t30",
> + "nvidia,tegra30";
> +
> + aliases {
> + rtc0 = "/i2c@7000c000/rtc@68";
> + rtc1 = "/i2c@7000d000/tps65911@2d";
> + rtc2 = "/rtc@7000e000";
> + serial0 = &uarta;
> + serial1 = &uartb;
> + serial2 = &uartc;
> + serial3 = &uartd;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + pcie@3000 {
> + status = "okay";
> +
> + pci@1,0 {
> + status = "okay";
> + };
> +
> + pci@2,0 {
> + status = "okay";
> + };
> +
> + pci@3,0 {
> + status = "okay";
> + };
> + };
> +
> + host1x@50000000 {
> + dc@54200000 {
> + rgb {
> + status = "okay";
> + nvidia,panel = <&panel>;
> + };
> + };
> + hdmi@54280000 {
> + status = "okay";
> + hdmi-supply = <®_5v0>;
> + };
> + };
> +
> + /* Apalis UART1 */
> + serial@70006000 {
> + status = "okay";
> + };
> +
> + /* Apalis UART2 */
> + serial@70006040 {
> + compatible = "nvidia,tegra30-hsuart";
> + status = "okay";
> + };
> +
> + /* Apalis UART3 */
> + serial@70006200 {
> + compatible = "nvidia,tegra30-hsuart";
> + status = "okay";
> + };
> +
> + /* Apalis UART4 */
> + serial@70006300 {
> + compatible = "nvidia,tegra30-hsuart";
> + status = "okay";
> + };
> +
> + pwm@7000a000 {
> + status = "okay";
> + };
> +
> + /*
> + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
> + * board)
> + */
> + i2c@7000c000 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + pcie-switch@58 {
> + compatible = "brcm,pex8605";
> + reg = <0x58>;
> + };
> +
> + /* M41T0M6 real time clock on carrier board */
> + rtc@68 {
> + compatible = "st,m41t0";
> + reg = <0x68>;
> + };
> + };
> +
> + /* GEN2_I2C: unused */
> +
> + /*
> + * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
> + * carrier board)
> + */
> + i2c@7000c500 {
> + status = "okay";
> + clock-frequency = <400000>;
> + };
> +
> + /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
> + hdmiddc: i2c@7000c700 {
> + status = "okay";
> + };
> +
> + /* SPI1: Apalis SPI1 */
> + spi@7000d400 {
> + status = "okay";
> + spi-max-frequency = <25000000>;
> +
> + spidev0: spidev@1 {
> + compatible = "spidev";
> + reg = <1>;
> + spi-max-frequency = <25000000>;
> + };
> + };
> +
> + /* SPI5: Apalis SPI2 */
> + spi@7000dc00 {
> + status = "okay";
> + spi-max-frequency = <25000000>;
> +
> + spidev1: spidev@2 {
> + compatible = "spidev";
> + reg = <2>;
> + spi-max-frequency = <25000000>;
> + };
> + };
> +
> + hda@70030000 {
> + status = "okay";
> + };
> +
> + /* Apalis SD1 */
> + sdhci@78000000 {
> + status = "okay";
> + bus-width = <4>;
> + /* SD1_CD# */
> + cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + };
> +
> + /* Apalis MMC1 */
> + sdhci@78000400 {
> + status = "okay";
> + bus-width = <8>;
> + /* MMC1_CD# */
> + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
> + vqmmc-supply = <®_vddio_sdmmc3>;
> + };
> +
> + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
> + usb@7d000000 {
> + status = "okay";
> + dr_mode = "otg";
> + };
> +
> + usb-phy@7d000000 {
> + status = "okay";
> + vbus-supply = <®_usbo1_vbus>;
> + };
> +
> + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
> + usb@7d004000 {
> + status = "okay";
> + };
> +
> + usb-phy@7d004000 {
> + status = "okay";
> + vbus-supply = <®_usbh_vbus>;
> + };
> +
> + /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
> + usb@7d008000 {
> + status = "okay";
> + };
> +
> + usb-phy@7d008000 {
> + status = "okay";
> + vbus-supply = <®_usbh_vbus>;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + brightness-levels = <255 231 223 207 191 159 127 0>;
> + default-brightness-level = <6>;
> + /* BKL1_ON */
> + enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
> + power-supply = <®_3v3>;
> + pwms = <&pwm 0 5000000>; /* BKL1_PWM */
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + wakeup {
> + label = "WAKE1_MICO";
> + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_WAKEUP>;
> + debounce-interval = <10>;
> + wakeup-source;
> + };
> + };
> +
> + panel: panel {
> + /*
> + * edt,et057090dhu: EDT 5.7" LCD TFT
> + * edt,et070080dh6: EDT 7.0" LCD TFT
> + */
> + compatible = "edt,et057090dhu", "simple-panel";
> + backlight = <&backlight>;
> + power-supply = <®_3v3>;
> + };
> +
> + reg_3v3: regulator-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "3.3V_SW";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_5v0: regulator-5v0 {
> + compatible = "regulator-fixed";
> + regulator-name = "5V_SW";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + /* USBO1_EN */
> + reg_usbo1_vbus: regulator-usbo1-vbus {
> + compatible = "regulator-fixed";
> + regulator-name = "VCC_USBO1";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <®_5v0>;
> + };
> +
> + /* USBH_EN */
> + reg_usbh_vbus: regulator-usbh-vbus {
> + compatible = "regulator-fixed";
> + regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <®_5v0>;
> + };
> +
> + /*
> + * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on
> + * EN_+3.3_SDMMC3 GPIO
> + */
> + reg_vddio_sdmmc3: regulator-vddio-sdmmc3 {
> + compatible = "regulator-gpio";
> + regulator-name = "VDDIO_SDMMC3";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-type = "voltage";
> + gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>;
> + states = <1800000 0x0
> + 3300000 0x1>;
> + startup-delay-us = <100000>;
> + vin-supply = <&vddio_sdmmc_1v8_reg>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
> new file mode 100644
> index 000000000000..8b69e9185cee
> --- /dev/null
> +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
> @@ -0,0 +1,1189 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +#include "tegra30.dtsi"
> +
> +/*
> + * Toradex Apalis T30 Module Device Tree
> + * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B;
> + * 2GB: V1.1A, V1.1B
> + */
> +/ {
> + model = "Toradex Apalis T30";
> + compatible = "toradex,apalis_t30", "nvidia,tegra30";
These should be dropped because they are overridden.
> +
> + memory@80000000 {
> + reg = <0x80000000 0x40000000>;
> + };
> +
> + pcie@3000 {
> + avdd-pexa-supply = <&vdd2_reg>;
> + avdd-pexb-supply = <&vdd2_reg>;
> + avdd-pex-pll-supply = <&vdd2_reg>;
> + avdd-plle-supply = <&ldo6_reg>;
> + hvdd-pex-supply = <®_module_3v3>;
> + vddio-pex-ctl-supply = <®_module_3v3>;
> + vdd-pexa-supply = <&vdd2_reg>;
> + vdd-pexb-supply = <&vdd2_reg>;
> +
> + /* Apalis type specific */
> + pci@1,0 {
> + nvidia,num-lanes = <4>;
> + };
> +
> + /* Apalis PCIe */
> + pci@2,0 {
> + nvidia,num-lanes = <1>;
> + };
> +
> + /* I210/I211 Gigabit Ethernet Controller (on-module) */
> + pci@3,0 {
> + nvidia,num-lanes = <1>;
> + pcie@0 {
> + reg = <0 0 0 0 0>;
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + };
> + };
> +
> + host1x@50000000 {
> + hdmi@54280000 {
> + nvidia,ddc-i2c-bus = <&hdmiddc>;
> + nvidia,hpd-gpio =
> + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
> + pll-supply = <®_1v8_avdd_hdmi_pll>;
> + vdd-supply = <®_3v3_avdd_hdmi>;
> + };
> + };
> +
> + pinmux@70000868 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&state_default>;
> +
> + state_default: pinmux {
> + /* Analogue Audio (On-module) */
> + clk1_out_pw4 {
> + nvidia,pins = "clk1_out_pw4";
> + nvidia,function = "extperiph1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + dap3_fs_pp0 {
> + nvidia,pins = "dap3_fs_pp0",
> + "dap3_sclk_pp3",
> + "dap3_din_pp1",
> + "dap3_dout_pp2";
> + nvidia,function = "i2s2";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis BKL1_ON */
> + pv2 {
> + nvidia,pins = "pv2";
> + nvidia,function = "rsvd4";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis BKL1_PWM */
> + uart3_rts_n_pc0 {
> + nvidia,pins = "uart3_rts_n_pc0";
> + nvidia,function = "pwm0";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
> + uart3_cts_n_pa1 {
> + nvidia,pins = "uart3_cts_n_pa1";
> + nvidia,function = "rsvd2";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis CAN1 on SPI6 */
> + spi2_cs0_n_px3 {
> + nvidia,pins = "spi2_cs0_n_px3",
> + "spi2_miso_px1",
> + "spi2_mosi_px0",
> + "spi2_sck_px2";
> + nvidia,function = "spi6";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + /* CAN_INT1 */
> + spi2_cs1_n_pw2 {
> + nvidia,pins = "spi2_cs1_n_pw2";
> + nvidia,function = "spi3";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis CAN2 on SPI4 */
> + gmi_a16_pj7 {
> + nvidia,pins = "gmi_a16_pj7",
> + "gmi_a17_pb0",
> + "gmi_a18_pb1",
> + "gmi_a19_pk7";
> + nvidia,function = "spi4";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + /* CAN_INT2 */
> + spi2_cs2_n_pw3 {
> + nvidia,pins = "spi2_cs2_n_pw3";
> + nvidia,function = "spi3";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis Digital Audio */
> + clk1_req_pee2 {
> + nvidia,pins = "clk1_req_pee2";
> + nvidia,function = "hda";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + clk2_out_pw5 {
> + nvidia,pins = "clk2_out_pw5";
> + nvidia,function = "extperiph2";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + dap1_fs_pn0 {
> + nvidia,pins = "dap1_fs_pn0",
> + "dap1_din_pn1",
> + "dap1_dout_pn2",
> + "dap1_sclk_pn3";
> + nvidia,function = "hda";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis GPIO */
> + kb_col0_pq0 {
> + nvidia,pins = "kb_col0_pq0",
> + "kb_col1_pq1",
> + "kb_row10_ps2",
> + "kb_row11_ps3",
> + "kb_row12_ps4",
> + "kb_row13_ps5",
> + "kb_row14_ps6",
> + "kb_row15_ps7";
> + nvidia,function = "kbc";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + /* Multiplexed and therefore disabled */
> + owr {
> + nvidia,pins = "owr";
> + nvidia,function = "rsvd3";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis HDMI1 */
> + hdmi_cec_pee3 {
> + nvidia,pins = "hdmi_cec_pee3";
> + nvidia,function = "cec";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,open-drain = <TEGRA_PIN_DISABLE>;
> + };
> + hdmi_int_pn7 {
> + nvidia,pins = "hdmi_int_pn7";
> + nvidia,function = "hdmi";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis I2C1 */
> + gen1_i2c_scl_pc4 {
> + nvidia,pins = "gen1_i2c_scl_pc4",
> + "gen1_i2c_sda_pc5";
> + nvidia,function = "i2c1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis I2C2 (DDC) */
> + ddc_scl_pv4 {
> + nvidia,pins = "ddc_scl_pv4",
> + "ddc_sda_pv5";
> + nvidia,function = "i2c4";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis I2C3 (CAM) */
> + cam_i2c_scl_pbb1 {
> + nvidia,pins = "cam_i2c_scl_pbb1",
> + "cam_i2c_sda_pbb2";
> + nvidia,function = "i2c3";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis LCD1 */
> + lcd_d0_pe0 {
> + nvidia,pins = "lcd_d0_pe0",
> + "lcd_d1_pe1",
> + "lcd_d2_pe2",
> + "lcd_d3_pe3",
> + "lcd_d4_pe4",
> + "lcd_d5_pe5",
> + "lcd_d6_pe6",
> + "lcd_d7_pe7",
> + "lcd_d8_pf0",
> + "lcd_d9_pf1",
> + "lcd_d10_pf2",
> + "lcd_d11_pf3",
> + "lcd_d12_pf4",
> + "lcd_d13_pf5",
> + "lcd_d14_pf6",
> + "lcd_d15_pf7",
> + "lcd_d16_pm0",
> + "lcd_d17_pm1",
> + "lcd_d18_pm2",
> + "lcd_d19_pm3",
> + "lcd_d20_pm4",
> + "lcd_d21_pm5",
> + "lcd_d22_pm6",
> + "lcd_d23_pm7",
> + "lcd_de_pj1",
> + "lcd_hsync_pj3",
> + "lcd_pclk_pb3",
> + "lcd_vsync_pj4";
> + nvidia,function = "displaya";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis MMC1 */
> + sdmmc3_clk_pa6 {
> + nvidia,pins = "sdmmc3_clk_pa6";
> + nvidia,function = "sdmmc3";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + sdmmc3_dat0_pb7 {
> + nvidia,pins = "sdmmc3_cmd_pa7",
> + "sdmmc3_dat0_pb7",
> + "sdmmc3_dat1_pb6",
> + "sdmmc3_dat2_pb5",
> + "sdmmc3_dat3_pb4",
> + "sdmmc3_dat4_pd1",
> + "sdmmc3_dat5_pd0",
> + "sdmmc3_dat6_pd3",
> + "sdmmc3_dat7_pd4";
> + nvidia,function = "sdmmc3";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + /* Apalis MMC1_CD# */
> + pv3 {
> + nvidia,pins = "pv3";
> + nvidia,function = "rsvd2";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis Parallel Camera */
> + cam_mclk_pcc0 {
> + nvidia,pins = "cam_mclk_pcc0";
> + nvidia,function = "vi_alt3";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + vi_vsync_pd6 {
> + nvidia,pins = "vi_d0_pt4",
> + "vi_d1_pd5",
> + "vi_d2_pl0",
> + "vi_d3_pl1",
> + "vi_d4_pl2",
> + "vi_d5_pl3",
> + "vi_d6_pl4",
> + "vi_d7_pl5",
> + "vi_d8_pl6",
> + "vi_d9_pl7",
> + "vi_d10_pt2",
> + "vi_d11_pt3",
> + "vi_hsync_pd7",
> + "vi_pclk_pt0",
> + "vi_vsync_pd6";
> + nvidia,function = "vi";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + /* Multiplexed and therefore disabled */
> + kb_col2_pq2 {
> + nvidia,pins = "kb_col2_pq2",
> + "kb_col3_pq3",
> + "kb_col4_pq4",
> + "kb_row4_pr4";
> + nvidia,function = "rsvd4";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + kb_row0_pr0 {
> + nvidia,pins = "kb_row0_pr0",
> + "kb_row1_pr1",
> + "kb_row2_pr2",
> + "kb_row3_pr3";
> + nvidia,function = "rsvd3";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + kb_row5_pr5 {
> + nvidia,pins = "kb_row5_pr5",
> + "kb_row6_pr6",
> + "kb_row7_pr7";
> + nvidia,function = "kbc";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + /*
> + * VI level-shifter direction
> + * (pull-down => default direction input)
> + */
> + vi_mclk_pt1 {
> + nvidia,pins = "vi_mclk_pt1";
> + nvidia,function = "vi_alt3";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis PWM1 */
> + pu6 {
> + nvidia,pins = "pu6";
> + nvidia,function = "pwm3";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis PWM2 */
> + pu5 {
> + nvidia,pins = "pu5";
> + nvidia,function = "pwm2";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis PWM3 */
> + pu4 {
> + nvidia,pins = "pu4";
> + nvidia,function = "pwm1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis PWM4 */
> + pu3 {
> + nvidia,pins = "pu3";
> + nvidia,function = "pwm0";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis RESET_MOCI# */
> + gmi_rst_n_pi4 {
> + nvidia,pins = "gmi_rst_n_pi4";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis SATA1_ACT# */
> + pex_l0_prsnt_n_pdd0 {
> + nvidia,pins = "pex_l0_prsnt_n_pdd0";
> + nvidia,function = "rsvd3";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis SD1 */
> + sdmmc1_clk_pz0 {
> + nvidia,pins = "sdmmc1_clk_pz0";
> + nvidia,function = "sdmmc1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + sdmmc1_cmd_pz1 {
> + nvidia,pins = "sdmmc1_cmd_pz1",
> + "sdmmc1_dat0_py7",
> + "sdmmc1_dat1_py6",
> + "sdmmc1_dat2_py5",
> + "sdmmc1_dat3_py4";
> + nvidia,function = "sdmmc1";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> + /* Apalis SD1_CD# */
> + clk2_req_pcc5 {
> + nvidia,pins = "clk2_req_pcc5";
> + nvidia,function = "rsvd2";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis SPDIF1 */
> + spdif_out_pk5 {
> + nvidia,pins = "spdif_out_pk5",
> + "spdif_in_pk6";
> + nvidia,function = "spdif";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis SPI1 */
> + spi1_sck_px5 {
> + nvidia,pins = "spi1_sck_px5",
> + "spi1_mosi_px4",
> + "spi1_miso_px7",
> + "spi1_cs0_n_px6";
> + nvidia,function = "spi1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis SPI2 */
> + lcd_sck_pz4 {
> + nvidia,pins = "lcd_sck_pz4",
> + "lcd_sdout_pn5",
> + "lcd_sdin_pz2",
> + "lcd_cs0_n_pn4";
> + nvidia,function = "spi5";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /*
> + * Apalis TS (Low-speed type specific)
> + * pins may be used as GPIOs
> + */
> + kb_col5_pq5 {
> + nvidia,pins = "kb_col5_pq5";
> + nvidia,function = "rsvd4";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + kb_col6_pq6 {
> + nvidia,pins = "kb_col6_pq6",
> + "kb_col7_pq7",
> + "kb_row8_ps0",
> + "kb_row9_ps1";
> + nvidia,function = "kbc";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis UART1 */
> + ulpi_data0 {
> + nvidia,pins = "ulpi_data0_po1",
> + "ulpi_data1_po2",
> + "ulpi_data2_po3",
> + "ulpi_data3_po4",
> + "ulpi_data4_po5",
> + "ulpi_data5_po6",
> + "ulpi_data6_po7",
> + "ulpi_data7_po0";
> + nvidia,function = "uarta";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis UART2 */
> + ulpi_clk_py0 {
> + nvidia,pins = "ulpi_clk_py0",
> + "ulpi_dir_py1",
> + "ulpi_nxt_py2",
> + "ulpi_stp_py3";
> + nvidia,function = "uartd";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis UART3 */
> + uart2_rxd_pc3 {
> + nvidia,pins = "uart2_rxd_pc3",
> + "uart2_txd_pc2";
> + nvidia,function = "uartb";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis UART4 */
> + uart3_rxd_pw7 {
> + nvidia,pins = "uart3_rxd_pw7",
> + "uart3_txd_pw6";
> + nvidia,function = "uartc";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis USBH_EN */
> + pex_l0_rst_n_pdd1 {
> + nvidia,pins = "pex_l0_rst_n_pdd1";
> + nvidia,function = "rsvd3";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis USBH_OC# */
> + pex_l0_clkreq_n_pdd2 {
> + nvidia,pins = "pex_l0_clkreq_n_pdd2";
> + nvidia,function = "rsvd3";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis USBO1_EN */
> + gen2_i2c_scl_pt5 {
> + nvidia,pins = "gen2_i2c_scl_pt5";
> + nvidia,function = "rsvd4";
> + nvidia,open-drain = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis USBO1_OC# */
> + gen2_i2c_sda_pt6 {
> + nvidia,pins = "gen2_i2c_sda_pt6";
> + nvidia,function = "rsvd4";
> + nvidia,open-drain = <TEGRA_PIN_DISABLE>;
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* Apalis VGA1 not supported and therefore disabled */
> + crt_hsync_pv6 {
> + nvidia,pins = "crt_hsync_pv6",
> + "crt_vsync_pv7";
> + nvidia,function = "rsvd2";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Apalis WAKE1_MICO */
> + pv1 {
> + nvidia,pins = "pv1";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* eMMC (On-module) */
> + sdmmc4_clk_pcc4 {
> + nvidia,pins = "sdmmc4_clk_pcc4",
> + "sdmmc4_cmd_pt7",
> + "sdmmc4_rst_n_pcc3";
> + nvidia,function = "sdmmc4";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + sdmmc4_dat0_paa0 {
> + nvidia,pins = "sdmmc4_dat0_paa0",
> + "sdmmc4_dat1_paa1",
> + "sdmmc4_dat2_paa2",
> + "sdmmc4_dat3_paa3",
> + "sdmmc4_dat4_paa4",
> + "sdmmc4_dat5_paa5",
> + "sdmmc4_dat6_paa6",
> + "sdmmc4_dat7_paa7";
> + nvidia,function = "sdmmc4";
> + nvidia,pull = <TEGRA_PIN_PULL_UP>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* EN_+3.3_SDMMC3 */
> + uart2_cts_n_pj5 {
> + nvidia,pins = "uart2_cts_n_pj5";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
> + pex_l2_prsnt_n_pdd7 {
> + nvidia,pins = "pex_l2_prsnt_n_pdd7",
> + "pex_l2_rst_n_pcc6";
> + nvidia,function = "pcie";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
> + pex_wake_n_pdd3 {
> + nvidia,pins = "pex_wake_n_pdd3",
> + "pex_l2_clkreq_n_pcc7";
> + nvidia,function = "pcie";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + /* LAN i210/i211 SMB_ALERT_N (On-module) */
> + sys_clk_req_pz5 {
> + nvidia,pins = "sys_clk_req_pz5";
> + nvidia,function = "rsvd2";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /* LVDS Transceiver Configuration */
> + pbb0 {
> + nvidia,pins = "pbb0",
> + "pbb7",
> + "pcc1",
> + "pcc2";
> + nvidia,function = "rsvd2";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + pbb3 {
> + nvidia,pins = "pbb3",
> + "pbb4",
> + "pbb5",
> + "pbb6";
> + nvidia,function = "displayb";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Not connected and therefore disabled */
> + clk_32k_out_pa0 {
> + nvidia,pins = "clk3_out_pee0",
> + "clk3_req_pee1",
> + "clk_32k_out_pa0",
> + "dap4_din_pp5",
> + "dap4_dout_pp6",
> + "dap4_fs_pp4",
> + "dap4_sclk_pp7";
> + nvidia,function = "rsvd2";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + dap2_fs_pa2 {
> + nvidia,pins = "dap2_fs_pa2",
> + "dap2_sclk_pa3",
> + "dap2_din_pa4",
> + "dap2_dout_pa5",
> + "lcd_dc0_pn6",
> + "lcd_m1_pw1",
> + "lcd_pwr1_pc1",
> + "pex_l1_clkreq_n_pdd6",
> + "pex_l1_prsnt_n_pdd4",
> + "pex_l1_rst_n_pdd5";
> + nvidia,function = "rsvd3";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + gmi_ad0_pg0 {
> + nvidia,pins = "gmi_ad0_pg0",
> + "gmi_ad2_pg2",
> + "gmi_ad3_pg3",
> + "gmi_ad4_pg4",
> + "gmi_ad5_pg5",
> + "gmi_ad6_pg6",
> + "gmi_ad7_pg7",
> + "gmi_ad8_ph0",
> + "gmi_ad9_ph1",
> + "gmi_ad10_ph2",
> + "gmi_ad11_ph3",
> + "gmi_ad12_ph4",
> + "gmi_ad13_ph5",
> + "gmi_ad14_ph6",
> + "gmi_ad15_ph7",
> + "gmi_adv_n_pk0",
> + "gmi_clk_pk1",
> + "gmi_cs4_n_pk2",
> + "gmi_cs2_n_pk3",
> + "gmi_dqs_pi2",
> + "gmi_iordy_pi5",
> + "gmi_oe_n_pi1",
> + "gmi_wait_pi7",
> + "gmi_wr_n_pi0",
> + "lcd_cs1_n_pw0",
> + "pu0",
> + "pu1",
> + "pu2";
> + nvidia,function = "rsvd4";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + gmi_cs0_n_pj0 {
> + nvidia,pins = "gmi_cs0_n_pj0",
> + "gmi_cs1_n_pj2",
> + "gmi_cs3_n_pk4";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + gmi_cs6_n_pi3 {
> + nvidia,pins = "gmi_cs6_n_pi3";
> + nvidia,function = "sata";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + gmi_cs7_n_pi6 {
> + nvidia,pins = "gmi_cs7_n_pi6";
> + nvidia,function = "gmi_alt";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + lcd_pwr0_pb2 {
> + nvidia,pins = "lcd_pwr0_pb2",
> + "lcd_pwr2_pc6",
> + "lcd_wr_n_pz3";
> + nvidia,function = "hdcp";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> + uart2_rts_n_pj6 {
> + nvidia,pins = "uart2_rts_n_pj6";
> + nvidia,function = "gmi";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* Power I2C (On-module) */
> + pwr_i2c_scl_pz6 {
> + nvidia,pins = "pwr_i2c_scl_pz6",
> + "pwr_i2c_sda_pz7";
> + nvidia,function = "i2cpwr";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + nvidia,open-drain = <TEGRA_PIN_ENABLE>;
> + };
> +
> + /*
> + * THERMD_ALERT#, unlatched I2C address pin of LM95245
> + * temperature sensor therefore requires disabling for
> + * now
> + */
> + lcd_dc1_pd2 {
> + nvidia,pins = "lcd_dc1_pd2";
> + nvidia,function = "rsvd3";
> + nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
> + nvidia,tristate = <TEGRA_PIN_ENABLE>;
> + nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> + };
> +
> + /* TOUCH_PEN_INT# (On-module) */
> + pv0 {
> + nvidia,pins = "pv0";
> + nvidia,function = "rsvd1";
> + nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> + nvidia,tristate = <TEGRA_PIN_DISABLE>;
> + nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> + };
> + };
> + };
> +
> + hdmiddc: i2c@7000c700 {
> + clock-frequency = <10000>;
> + };
> +
> + /*
> + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
> + * touch screen controller
> + */
> + i2c@7000d000 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + /* SGTL5000 audio codec */
> + sgtl5000: codec@a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + VDDA-supply = <®_module_3v3_audio>;
> + VDDD-supply = <®_1v8_vio>;
> + VDDIO-supply = <®_module_3v3>;
> + clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
> + };
> +
> + pmic: tps65911@2d {
pmic@2d
> + compatible = "ti,tps65911";
> + reg = <0x2d>;
> +
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> +
> + ti,system-power-controller;
> +
> + #gpio-cells = <2>;
> + gpio-controller;
> +
> + vcc1-supply = <®_module_3v3>;
> + vcc2-supply = <®_module_3v3>;
> + vcc3-supply = <®_1v8_vio>;
> + vcc4-supply = <®_module_3v3>;
> + vcc5-supply = <®_module_3v3>;
> + vcc6-supply = <®_1v8_vio>;
> + vcc7-supply = <®_5v0_charge_pump>;
> + vccio-supply = <®_module_3v3>;
> +
> + regulators {
> + vdd1_reg: vdd1 {
> + regulator-name = "+V1.35_VDDIO_DDR";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + };
> +
> + vdd2_reg: vdd2 {
> + regulator-name = "+V1.05";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + vddctrl_reg: vddctrl {
> + regulator-name = "+V1.0_VDD_CPU";
> + regulator-min-microvolt = <1150000>;
> + regulator-max-microvolt = <1150000>;
> + regulator-always-on;
> + };
> +
> + reg_1v8_vio: vio {
> + regulator-name = "+V1.8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + /*
> + * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3
> + * is off
> + */
> + vddio_sdmmc_1v8_reg: ldo1 {
> + regulator-name = "+VDDIO_SDMMC3_1V8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + /*
> + * EN_+V3.3 switching via FET:
> + * +V3.3_AUDIO_AVDD_S, +V3.3
> + * see also +V3.3 fixed supply
> + */
> + ldo2_reg: ldo2 {
> + regulator-name = "EN_+V3.3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + ldo3_reg: ldo3 {
> + regulator-name = "+V1.2_CSI";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo4_reg: ldo4 {
> + regulator-name = "+V1.2_VDD_RTC";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + /*
> + * +V2.8_AVDD_VDAC:
> + * only required for (unsupported) analog RGB
> + */
> + ldo5_reg: ldo5 {
> + regulator-name = "+V2.8_AVDD_VDAC";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> +
> + /*
> + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
> + * but LDO6 can't set voltage in 50mV
> + * granularity
> + */
> + ldo6_reg: ldo6 {
> + regulator-name = "+V1.05_AVDD_PLLE";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + };
> +
> + ldo7_reg: ldo7 {
> + regulator-name = "+V1.2_AVDD_PLL";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + ldo8_reg: ldo8 {
> + regulator-name = "+V1.0_VDD_DDR_HS";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + /* STMPE811 touch screen controller */
> + stmpe811@41 {
touchscreen@41
> + compatible = "st,stmpe811";
> + reg = <0x41>;
> + irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
> + interrupt-controller;
> + id = <0>;
> + blocks = <0x5>;
> + irq-trigger = <0x1>;
> +
> + stmpe_touchscreen {
> + compatible = "st,stmpe-ts";
> + /* 3.25 MHz ADC clock speed */
> + st,adc-freq = <1>;
> + /* 8 sample average control */
> + st,ave-ctrl = <3>;
> + /* 7 length fractional part in z */
> + st,fraction-z = <7>;
> + /*
> + * 50 mA typical 80 mA max touchscreen drivers
> + * current limit value
> + */
> + st,i-drive = <1>;
> + /* 12-bit ADC */
> + st,mod-12b = <1>;
> + /* internal ADC reference */
> + st,ref-sel = <0>;
> + /* ADC converstion time: 80 clocks */
> + st,sample-time = <4>;
> + /* 1 ms panel driver settling time */
> + st,settling = <3>;
> + /* 5 ms touch detect interrupt delay */
> + st,touch-det-delay = <5>;
> + };
> + };
> +
> + /*
> + * LM95245 temperature sensor
> + * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
> + */
> + temp-sensor@4c {
> + compatible = "national,lm95245";
> + reg = <0x4c>;
> + };
> +
> + /* SW: +V1.2_VDD_CORE */
> + tps62362@60 {
regulator@60
> + compatible = "ti,tps62362";
> + reg = <0x60>;
> +
> + regulator-name = "tps62362-vout";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1400000>;
> + regulator-boot-on;
> + regulator-always-on;
> + ti,vsel0-state-low;
> + /* VSEL1: EN_CORE_DVFS_N low for DVFS */
> + ti,vsel1-state-low;
> + };
> + };
> +
> + /* SPI4: CAN2 */
> + spi@7000da00 {
> + status = "okay";
> + spi-max-frequency = <10000000>;
> +
> + can@1 {
> + compatible = "microchip,mcp2515";
> + reg = <1>;
> + clocks = <&clk16m>;
> + interrupt-parent = <&gpio>;
> + interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_RISING>;
> + spi-max-frequency = <10000000>;
> + };
> + };
> +
> + /* SPI6: CAN1 */
> + spi@7000de00 {
> + status = "okay";
> + spi-max-frequency = <10000000>;
> +
> + can@0 {
> + compatible = "microchip,mcp2515";
> + reg = <0>;
> + clocks = <&clk16m>;
> + interrupt-parent = <&gpio>;
> + interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>;
> + spi-max-frequency = <10000000>;
> + };
> + };
> +
> + pmc@7000e400 {
> + nvidia,invert-interrupt;
> + nvidia,suspend-mode = <1>;
> + nvidia,cpu-pwr-good-time = <5000>;
> + nvidia,cpu-pwr-off-time = <5000>;
> + nvidia,core-pwr-good-time = <3845 3845>;
> + nvidia,core-pwr-off-time = <0>;
> + nvidia,core-power-req-active-high;
> + nvidia,sys-clock-req-active-high;
> +
> + /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
> + i2c-thermtrip {
> + nvidia,i2c-controller-id = <4>;
> + nvidia,bus-addr = <0x2d>;
> + nvidia,reg-addr = <0x3e>;
> + nvidia,reg-data = <0x1>;
> + };
> + };
> +
> + ahub@70080000 {
> + i2s@70080500 {
> + status = "okay";
> + };
> + };
> +
> + /* eMMC */
> + sdhci@78000600 {
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-width = <8>;
> + non-removable;
> + vmmc-supply = <®_module_3v3>; /* VCC */
> + vqmmc-supply = <®_1v8_vio>; /* VCCQ */
> + mmc-ddr-1_8v;
> +
> + emmc: emmc@0 {
> + reg = <0>;
> + compatible = "mmc-card";
> + broken-hpi;
> + };
> + };
> +
> + clocks {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
Drop this and move the child nodes up a level.
Really, it is all the SoC peripherals that should be under a simple-bus,
but Tegra didn't do that from the start and we just continue to
copy-n-paste.
> +
> + clk32k_in: clock@0 {
> + compatible = "fixed-clock";
> + reg = <0>;
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> +
> + clk16m: clock@1 {
> + compatible = "fixed-clock";
> + reg = <1>;
> + #clock-cells = <0>;
> + clock-frequency = <16000000>;
> + clock-output-names = "clk16m";
> + };
> + };
> +
> + reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
> + compatible = "regulator-fixed";
> + regulator-name = "+V1.8_AVDD_HDMI_PLL";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + enable-active-high;
> + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
> + vin-supply = <®_1v8_vio>;
> + };
> +
> + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
> + compatible = "regulator-fixed";
> + regulator-name = "+V3.3_AVDD_HDMI";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
> + vin-supply = <®_module_3v3>;
> + };
> +
> + reg_5v0_charge_pump: regulator-5v0-charge-pump {
> + compatible = "regulator-fixed";
> + regulator-name = "+V5.0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + reg_module_3v3: regulator-module-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "+V3.3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_module_3v3_audio: regulator-module-3v3-audio {
> + compatible = "regulator-fixed";
> + regulator-name = "+V3.3_AUDIO_AVDD_S";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + sound {
> + compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
> + "nvidia,tegra-audio-sgtl5000";
> + nvidia,model = "Toradex Apalis T30";
> + nvidia,audio-routing =
> + "Headphone Jack", "HP_OUT",
> + "LINE_IN", "Line In Jack",
> + "MIC_IN", "Mic Jack";
> + nvidia,i2s-controller = <&tegra_i2s2>;
> + nvidia,audio-codec = <&sgtl5000>;
> + clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
> + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
> + <&tegra_car TEGRA30_CLK_EXTERN1>;
> + clock-names = "pll_a", "pll_a_out0", "mclk";
> + };
> +};
> diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
> index ee6750247c57..4c0a313f6a9d 100644
> --- a/arch/arm/boot/dts/tegra30-apalis.dtsi
> +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
> @@ -3,8 +3,7 @@
>
> /*
> * Toradex Apalis T30 Module Device Tree
> - * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
> - * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
> + * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
> */
> / {
> model = "Toradex Apalis T30";
> --
> 2.14.4
>
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2018-07-31 21:06 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-22 16:49 [PATCH 00/28] ARM: dts: tegra: apalis_t30: major revamp incl. v1.1 hardware support Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 01/28] ARM: tegra: apalis_t30: enable broken-hpi on emmc Marcel Ziswiler
2018-07-24 14:03 ` Dmitry Osipenko
2018-07-24 14:26 ` Marcel Ziswiler
2018-07-24 14:55 ` Dmitry Osipenko
2018-07-25 8:40 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 02/28] ARM: tegra: apalis_t30: fix mmc1 cmd pull-up Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 03/28] ARM: tegra: apalis_t30: pull-up sd card detect pins Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 04/28] ARM: tegra: apalis_t30: add local-mac-address property Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 05/28] ARM: tegra: apalis_t30: reorder pcie properties Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 06/28] ARM: tegra: apalis_t30: annotate pcie port nodes Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 07/28] ARM: tegra: apalis_t30: reorder host1x/hdmi properties Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 08/28] ARM: tegra: apalis_t30: regulator clean-up Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 09/28] ARM: tegra: apalis_t30: add missing regulators Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 10/28] ARM: tegra: apalis_t30: annotate uarts Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 11/28] ARM: tegra: apalis_t30: drop unused cami2c label Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 12/28] ARM: tegra: apalis_t30: white-space clean-up Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 13/28] ARM: tegra: apalis_t30: drop unused mmc1/sd1 labels Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 14/28] ARM: tegra: apalis_t30: annotate mmc1/sd1 Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 15/28] ARM: tegra: apalis_t30: move dr_mode property from phy to controller Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 16/28] ARM: tegra: apalis_t30: reorder backlight properties Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 17/28] ARM: tegra: apalis_t30: drop pwmleds Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 18/28] ARM: tegra: apalis_t30: pinmux clean-up Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 19/28] ARM: tegra: apalis_t30: add missing pinmux Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 20/28] ARM: tegra: apalis_t30: use proper irq-gpio for stmpe811 Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 21/28] ARM: tegra: apalis_t30: further lm95245 temperature sensor annotation Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 22/28] ARM: tegra: apalis_t30: add i2c-thermtrip Marcel Ziswiler
2018-07-25 11:11 ` Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 23/28] ARM: tegra: apalis_t30: add proper emmc vmmc and vqmmc supplies Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 24/28] ARM: tegra: apalis_t30: enable emmc ddr52 mode Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 25/28] ARM: tegra: apalis_t30: rename clk to clock Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 26/28] ARM: tegra: apalis_t30: line break long compatible property line Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 27/28] ARM: tegra: apalis_t30: fix pcie switch vendor compatible Marcel Ziswiler
2018-07-22 16:49 ` [PATCH 28/28] ARM: tegra: apalis_t30: support v1.1 hardware revision Marcel Ziswiler
2018-07-31 21:06 ` Rob Herring
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