From: Songjun Wu <songjun.wu@linux.intel.com>
To: hua.ma@linux.intel.com, yixin.zhu@linux.intel.com,
chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com
Cc: linux-mips@linux-mips.org, linux-clk@vger.kernel.org,
linux-serial@vger.kernel.org, devicetree@vger.kernel.org,
Songjun Wu <songjun.wu@linux.intel.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-kernel@vger.kernel.org, Jiri Slaby <jslaby@suse.com>
Subject: [PATCH v2 09/18] serial: intel: Change ltq_w32_mask to asc_update_bits
Date: Fri, 3 Aug 2018 11:02:28 +0800 [thread overview]
Message-ID: <20180803030237.3366-10-songjun.wu@linux.intel.com> (raw)
In-Reply-To: <20180803030237.3366-1-songjun.wu@linux.intel.com>
ltq prefix is platform specific function, asc prefix
is more generic.
Signed-off-by: Songjun Wu <songjun.wu@linux.intel.com>
---
Changes in v2: None
drivers/tty/serial/lantiq.c | 33 ++++++++++++++++++++-------------
1 file changed, 20 insertions(+), 13 deletions(-)
diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c
index 836ca51460f2..e36e6a267e7a 100644
--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
@@ -114,6 +114,13 @@ struct ltq_uart_port {
unsigned int err_irq;
};
+static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
+{
+ u32 tmp = readl(reg);
+
+ writel((tmp & ~clear) | set, reg);
+}
+
static inline struct
ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
{
@@ -164,16 +171,16 @@ lqasc_rx_chars(struct uart_port *port)
if (rsr & ASCSTATE_ANY) {
if (rsr & ASCSTATE_PE) {
port->icount.parity++;
- ltq_w32_mask(0, ASCWHBSTATE_CLRPE,
+ asc_update_bits(0, ASCWHBSTATE_CLRPE,
port->membase + LTQ_ASC_WHBSTATE);
} else if (rsr & ASCSTATE_FE) {
port->icount.frame++;
- ltq_w32_mask(0, ASCWHBSTATE_CLRFE,
+ asc_update_bits(0, ASCWHBSTATE_CLRFE,
port->membase + LTQ_ASC_WHBSTATE);
}
if (rsr & ASCSTATE_ROE) {
port->icount.overrun++;
- ltq_w32_mask(0, ASCWHBSTATE_CLRROE,
+ asc_update_bits(0, ASCWHBSTATE_CLRROE,
port->membase + LTQ_ASC_WHBSTATE);
}
@@ -253,7 +260,7 @@ lqasc_err_int(int irq, void *_port)
struct uart_port *port = (struct uart_port *)_port;
spin_lock_irqsave(<q_asc_lock, flags);
/* clear any pending interrupts */
- ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
+ asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
spin_unlock_irqrestore(<q_asc_lock, flags);
return IRQ_HANDLED;
@@ -305,7 +312,7 @@ lqasc_startup(struct uart_port *port)
clk_enable(ltq_port->clk);
port->uartclk = clk_get_rate(ltq_port->fpiclk);
- ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
+ asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
port->membase + LTQ_ASC_CLC);
ltq_w32(0, port->membase + LTQ_ASC_PISEL);
@@ -321,7 +328,7 @@ lqasc_startup(struct uart_port *port)
* setting enable bits
*/
wmb();
- ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
+ asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
ASCCON_ROEN, port->membase + LTQ_ASC_CON);
retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
@@ -365,9 +372,9 @@ lqasc_shutdown(struct uart_port *port)
free_irq(ltq_port->err_irq, port);
ltq_w32(0, port->membase + LTQ_ASC_CON);
- ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
+ asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
port->membase + LTQ_ASC_RXFCON);
- ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
+ asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
port->membase + LTQ_ASC_TXFCON);
if (!IS_ERR(ltq_port->clk))
clk_disable(ltq_port->clk);
@@ -439,7 +446,7 @@ lqasc_set_termios(struct uart_port *port,
spin_lock_irqsave(<q_asc_lock, flags);
/* set up CON */
- ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON);
+ asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
/* Set baud rate - take a divider of 2 into account */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
@@ -447,19 +454,19 @@ lqasc_set_termios(struct uart_port *port,
divisor = divisor / 2 - 1;
/* disable the baudrate generator */
- ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
+ asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
/* make sure the fractional divider is off */
- ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
+ asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
/* set up to use divisor of 2 */
- ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
+ asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
/* now we can write the new baudrate into the register */
ltq_w32(divisor, port->membase + LTQ_ASC_BG);
/* turn the baudrate generator back on */
- ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON);
+ asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
/* enable rx */
ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
--
2.11.0
next prev parent reply other threads:[~2018-08-03 3:04 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-03 3:02 [PATCH v2 00/18] MIPS: intel: add initial support for Intel MIPS SoCs Songjun Wu
2018-08-03 3:02 ` [PATCH v2 01/18] MIPS: intel: Add " Songjun Wu
2018-08-03 17:49 ` Paul Burton
2018-08-06 9:12 ` Hua Ma
2018-08-03 3:02 ` [PATCH v2 02/18] clk: intel: Add clock driver " Songjun Wu
2018-08-06 15:19 ` Rob Herring
2018-08-08 2:51 ` yixin zhu
2018-08-08 5:50 ` Stephen Boyd
2018-08-08 8:52 ` yixin zhu
2018-08-27 19:09 ` Stephen Boyd
2018-08-29 6:56 ` Zhu, Yi Xin
2018-08-31 17:10 ` Stephen Boyd
2018-09-03 10:47 ` Zhu, Yi Xin
2018-08-29 10:34 ` Zhu, Yi Xin
2018-08-31 17:13 ` Stephen Boyd
2018-09-03 10:52 ` Zhu, Yi Xin
2018-08-03 3:02 ` [PATCH v2 03/18] dt-bindings: clk: Add documentation of grx500 clock controller Songjun Wu
2018-08-06 15:18 ` Rob Herring
2018-08-08 3:08 ` yixin zhu
2018-08-08 14:54 ` Rob Herring
2018-08-03 3:02 ` [PATCH v2 04/18] MIPS: dts: Add initial support for Intel MIPS SoCs Songjun Wu
2018-08-04 11:11 ` Hauke Mehrtens
2018-08-06 9:20 ` Hua Ma
2018-08-03 3:02 ` [PATCH v2 05/18] dt-binding: MIPS: Add documentation of " Songjun Wu
2018-08-06 15:16 ` Rob Herring
2018-08-03 3:02 ` [PATCH v2 06/18] MIPS: dts: Change upper case to lower case Songjun Wu
2018-08-06 15:14 ` Rob Herring
2018-08-03 3:02 ` [PATCH v2 07/18] MIPS: dts: Add aliases node for lantiq danube serial Songjun Wu
2018-08-03 3:02 ` [PATCH v2 08/18] serial: intel: Get serial id from dts Songjun Wu
2018-08-03 5:43 ` Greg Kroah-Hartman
2018-08-06 9:32 ` Wu, Songjun
2018-08-07 7:33 ` Geert Uytterhoeven
2018-08-08 4:05 ` Wu, Songjun
2018-08-08 8:33 ` Geert Uytterhoeven
2018-08-10 8:13 ` Wu, Songjun
2018-08-03 3:02 ` Songjun Wu [this message]
2018-08-03 3:02 ` [PATCH v2 10/18] MIPS: lantiq: Unselect SWAP_IO_SPACE when LANTIQ is selected Songjun Wu
2018-08-03 3:02 ` [PATCH v2 11/18] serial: intel: Use readl/writel instead of ltq_r32/ltq_w32 Songjun Wu
2018-08-03 3:02 ` [PATCH v2 12/18] serial: intel: Rename fpiclk to freqclk Songjun Wu
2018-08-03 3:02 ` [PATCH v2 13/18] serial: intel: Replace clk_enable/clk_disable with clk generic API Songjun Wu
2018-08-03 3:02 ` [PATCH v2 14/18] serial: intel: Add CCF support Songjun Wu
2018-08-03 5:56 ` Greg Kroah-Hartman
2018-08-03 7:33 ` Wu, Songjun
2018-08-03 10:30 ` Greg Kroah-Hartman
2018-08-04 10:54 ` Hauke Mehrtens
2018-08-04 12:43 ` Greg Kroah-Hartman
2018-08-04 21:03 ` Arnd Bergmann
2018-08-06 7:05 ` Wu, Songjun
2018-08-06 7:20 ` Geert Uytterhoeven
2018-08-06 8:58 ` Wu, Songjun
2018-08-06 9:29 ` Geert Uytterhoeven
2018-08-07 7:18 ` Wu, Songjun
2018-08-07 7:33 ` Geert Uytterhoeven
2018-08-03 3:02 ` [PATCH v2 15/18] serial: intel: Support more platform Songjun Wu
2018-08-03 5:57 ` Greg Kroah-Hartman
2018-08-03 7:21 ` Wu, Songjun
2018-08-05 8:37 ` Christoph Hellwig
2018-08-06 7:20 ` Wu, Songjun
2018-08-03 3:02 ` [PATCH v2 16/18] serial: intel: Reorder the head files Songjun Wu
2018-08-03 3:02 ` [PATCH v2 17/18] serial: intel: Change init_lqasc to static declaration Songjun Wu
2018-08-03 3:02 ` [PATCH v2 18/18] dt-bindings: serial: lantiq: Add optional properties for CCF Songjun Wu
2018-08-13 17:53 ` Rob Herring
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