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From: Paul Cercueil <paul@crapouillou.net>
To: Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Wim Van Sebroeck <wim@linux-watchdog.org>,
	Guenter Roeck <linux@roeck-us.net>,
	Ralf Baechle <ralf@linux-mips.org>,
	Paul Burton <paul.burton@mips.com>,
	James Hogan <jhogan@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
	Lee Jones <lee.jones@linaro.org>,
	Mathieu Malaterre <malat@debian.org>,
	Ezequiel Garcia <ezequiel@collabora.co.uk>
Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org,
	linux-mips@linux-mips.org, linux-doc@vger.kernel.org,
	linux-clk@vger.kernel.org, Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH v6 03/24] doc: Add doc for the Ingenic TCU hardware
Date: Thu,  9 Aug 2018 23:43:53 +0200
Message-ID: <20180809214414.20905-4-paul@crapouillou.net> (raw)
In-Reply-To: <20180809214414.20905-1-paul@crapouillou.net>

Add a documentation file about the Timer/Counter Unit (TCU) present in
the Ingenic JZ47xx SoCs.

The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
hardware block. It features up to to eight channels, that can be used as
counters, timers, or PWM.

- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
  have eight channels.

- JZ4725B introduced a separate channel, called Operating System Timer
  (OST). It is a 32-bit programmable timer. On JZ4770 and above, it is
  64-bit.

- Each one of the TCU channels has its own clock, which can be reparented
  to three different clocks (pclk, ext, rtc), gated, and reclocked, through
  their TCSR register.
  * The watchdog and OST hardware blocks also feature a TCSR register with
    the same format in their register space.
  * The TCU registers used to gate/ungate can also gate/ungate the watchdog
    and OST clocks.

- Each TCU channel works in one of two modes:
  * mode TCU1: channels cannot work in sleep mode, but are easier to
    operate.
  * mode TCU2: channels can work in sleep mode, but the operation is a bit
    more complicated than with TCU1 channels.

- The mode of each TCU channel depends on the SoC used:
  * On the oldest SoCs (up to JZ4740), all of the eight channels operate in
    TCU1 mode.
  * On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
  * On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
    others operate as TCU1.

- Each channel can generate an interrupt. Some channels share an interrupt
  line, some don't, and this changes between SoC versions:
  * on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
    own interrupt line; channels 2-7 share the last interrupt line.
  * On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
    interrupt line; the OST uses the last interrupt line.
  * on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
    channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
    the OST uses the last interrupt line.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 Documentation/mips/00-INDEX        |  3 ++
 Documentation/mips/ingenic-tcu.txt | 60 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/mips/ingenic-tcu.txt

 v4: New patch in this series

 v5: Added information about number of channels, and improved
     documentation about channel modes

 v6: Add info about OST (can be 32-bit on older SoCs)

diff --git a/Documentation/mips/00-INDEX b/Documentation/mips/00-INDEX
index 8ae9cffc2262..8ab8c3f83771 100644
--- a/Documentation/mips/00-INDEX
+++ b/Documentation/mips/00-INDEX
@@ -2,3 +2,6 @@
 	- this file.
 AU1xxx_IDE.README
 	- README for MIPS AU1XXX IDE driver.
+ingenic-tcu.txt
+	- Information file about the Timer/Counter Unit present
+	  in Ingenic JZ47xx SoCs.
diff --git a/Documentation/mips/ingenic-tcu.txt b/Documentation/mips/ingenic-tcu.txt
new file mode 100644
index 000000000000..0ea35b2a46da
--- /dev/null
+++ b/Documentation/mips/ingenic-tcu.txt
@@ -0,0 +1,60 @@
+Ingenic JZ47xx SoCs Timer/Counter Unit hardware
+-----------------------------------------------
+
+The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
+hardware block. It features up to to eight channels, that can be used as
+counters, timers, or PWM.
+
+- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
+  have eight channels.
+
+- JZ4725B introduced a separate channel, called Operating System Timer
+  (OST). It is a 32-bit programmable timer. On JZ4770 and above, it is
+  64-bit.
+
+- Each one of the TCU channels has its own clock, which can be reparented
+  to three different clocks (pclk, ext, rtc), gated, and reclocked, through
+  their TCSR register.
+  * The watchdog and OST hardware blocks also feature a TCSR register with
+    the same format in their register space.
+  * The TCU registers used to gate/ungate can also gate/ungate the watchdog
+    and OST clocks.
+
+- Each TCU channel works in one of two modes:
+  * mode TCU1: channels cannot work in sleep mode, but are easier to
+    operate.
+  * mode TCU2: channels can work in sleep mode, but the operation is a bit
+    more complicated than with TCU1 channels.
+
+- The mode of each TCU channel depends on the SoC used:
+  * On the oldest SoCs (up to JZ4740), all of the eight channels operate in
+    TCU1 mode.
+  * On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
+  * On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
+    others operate as TCU1.
+
+- Each channel can generate an interrupt. Some channels share an interrupt
+  line, some don't, and this changes between SoC versions:
+  * on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
+    own interrupt line; channels 2-7 share the last interrupt line.
+  * On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
+    interrupt line; the OST uses the last interrupt line.
+  * on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
+    channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
+    the OST uses the last interrupt line.
+
+Implementation
+--------------
+
+The functionalities of the TCU hardware are spread across multiple drivers:
+- clocks/irq/timer: drivers/clocksource/ingenic-timer.c
+- PWM:              drivers/pwm/pwm-jz4740.c
+- watchdog:         drivers/watchdog/jz4740_wdt.c
+- OST:              drivers/clocksource/ingenic-ost.c
+
+Because various functionalities of the TCU that belong to different drivers
+and frameworks can be controlled from the same registers, all of these
+drivers access their registers through the same regmap.
+
+For more information regarding the devicetree bindings of the TCU drivers,
+have a look at Documentation/devicetree/bindings/mfd/ingenic,tcu.txt.
-- 
2.11.0


  parent reply index

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-09 21:43 [PATCH v6 00/24] Ingenic TCU patchset v6 Paul Cercueil
2018-08-09 21:43 ` [PATCH v6 01/24] mfd: Add ingenic-tcu.h header Paul Cercueil
2018-08-09 21:43 ` [PATCH v6 02/24] dt-bindings: ingenic: Add DT bindings for TCU clocks Paul Cercueil
2018-08-09 21:43 ` Paul Cercueil [this message]
2018-08-09 21:43 ` [PATCH v6 04/24] dt-bindings: Add doc for the Ingenic TCU drivers Paul Cercueil
2018-08-13 15:24   ` Rob Herring
2018-08-09 21:43 ` [PATCH v6 05/24] clocksource: Add a new timer-ingenic driver Paul Cercueil
2018-08-09 21:43 ` [PATCH v6 06/24] clocksource: Add driver for the Ingenic JZ47xx OST Paul Cercueil
2018-08-14  9:42   ` Mathieu Malaterre
2018-08-16 16:07     ` Paul Cercueil
2018-08-09 21:43 ` [PATCH v6 07/24] MAINTAINERS: Add myself as maintainer for Ingenic TCU drivers Paul Cercueil
2018-08-09 21:43 ` [PATCH v6 08/24] watchdog: jz4740: Use WDT clock provided by TCU driver Paul Cercueil
2018-08-10 13:36   ` Guenter Roeck
2018-08-09 21:43 ` [PATCH v6 09/24] watchdog: jz4740: Use regmap " Paul Cercueil
2018-08-10 13:37   ` Guenter Roeck
2018-08-09 21:44 ` [PATCH v6 10/24] watchdog: jz4740: Avoid starting watchdog in set_timeout Paul Cercueil
2018-08-10 13:37   ` Guenter Roeck
2018-08-09 21:44 ` [PATCH v6 11/24] watchdog: jz4740: Drop dependency on MACH_JZ47xx, use COMPILE_TEST Paul Cercueil
2018-08-10 13:38   ` Guenter Roeck
2018-08-09 21:44 ` [PATCH v6 12/24] pwm: jz4740: Use regmap and clocks from TCU driver Paul Cercueil
2018-08-09 21:44 ` [PATCH v6 13/24] pwm: jz4740: Allow selection of PWM channels 0 and 1 Paul Cercueil
2018-08-09 21:44 ` [PATCH v6 14/24] pwm: jz4740: Drop dependency on MACH_INGENIC, use COMPILE_TEST Paul Cercueil
2018-08-09 21:44 ` [PATCH v6 15/24] pwm: jz4740: Remove unused devicetree compatible strings Paul Cercueil
2018-08-09 21:44 ` [PATCH v6 16/24] pwm: jz4740: Add support for the JZ4725B Paul Cercueil
2018-08-09 21:44 ` [PATCH v6 17/24] clk: jz4740: Add TCU clock Paul Cercueil
2018-08-09 21:44 ` [PATCH v6 18/24] MIPS: Kconfig: Select TCU timer driver when MACH_INGENIC is set Paul Cercueil
2018-08-09 21:44 ` [PATCH v6 19/24] MIPS: jz4740: Add DTS nodes for the TCU drivers Paul Cercueil
2018-08-09 21:44 ` [PATCH v6 20/24] MIPS: qi_lb60: Move PWM devices to devicetree Paul Cercueil
2018-08-09 21:46 ` [PATCH v6 21/24] MIPS: qi_lb60: Reduce system timer and clocksource to 750 kHz Paul Cercueil
2018-08-09 21:46 ` [PATCH v6 22/24] MIPS: CI20: Reduce system timer and clocksource to 3 MHz Paul Cercueil
2018-08-09 21:47 ` [PATCH v6 23/24] MIPS: CI20: defconfig: enable OST driver Paul Cercueil
2018-08-09 21:48 ` [PATCH v6 24/24] MIPS: jz4740: Drop obsolete code Paul Cercueil

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