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* [PATCH 1/3] clk: ingenic: Add proper Kconfig entries
@ 2018-08-21 12:38 Paul Cercueil
  2018-08-21 12:38 ` [PATCH 2/3] dt-bindings: clock: Add jz4725b-cgu.h header Paul Cercueil
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Paul Cercueil @ 2018-08-21 12:38 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland
  Cc: od, linux-kernel, linux-clk, devicetree, Paul Cercueil

Previously, the CGU code corresponding to the SoC for which we're
compiling the kernel was the only one enabled, which made it impossible
to build one kernel that supports them all.

Now, it is possible to select more than one SoC to support.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/clk/Kconfig          |  1 +
 drivers/clk/Makefile         |  2 +-
 drivers/clk/ingenic/Kconfig  | 37 ++++++++++++++++++++++++++++++++++++
 drivers/clk/ingenic/Makefile |  8 ++++----
 4 files changed, 43 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/ingenic/Kconfig

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 721572a8c429..95a9627cdf1d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -281,6 +281,7 @@ source "drivers/clk/actions/Kconfig"
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/imgtec/Kconfig"
+source "drivers/clk/ingenic/Kconfig"
 source "drivers/clk/keystone/Kconfig"
 source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0bb25dd009d1..3b3da7d84496 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -71,7 +71,7 @@ obj-$(CONFIG_H8300)			+= h8300/
 obj-$(CONFIG_ARCH_HISI)			+= hisilicon/
 obj-y					+= imgtec/
 obj-$(CONFIG_ARCH_MXC)			+= imx/
-obj-$(CONFIG_MACH_INGENIC)		+= ingenic/
+obj-y					+= ingenic/
 obj-$(CONFIG_ARCH_KEYSTONE)		+= keystone/
 obj-$(CONFIG_MACH_LOONGSON32)		+= loongson1/
 obj-y					+= mediatek/
diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
new file mode 100644
index 000000000000..851a5662f119
--- /dev/null
+++ b/drivers/clk/ingenic/Kconfig
@@ -0,0 +1,37 @@
+menu "Ingenic JZ47xx CGU drivers"
+	depends on MIPS || COMPILE_TEST
+
+config INGENIC_CGU_COMMON
+	bool
+
+config INGENIC_CGU_JZ4740
+	bool "Ingenic JZ4740 CGU driver"
+	default MACH_JZ4740
+	select INGENIC_CGU_COMMON
+	help
+	  Support the clocks provided by the CGU hardware on Ingenic JZ4740
+	  and compatible SoCs.
+
+	  If building for a JZ4740 SoC, you want to say Y here.
+
+config INGENIC_CGU_JZ4770
+	bool "Ingenic JZ4770 CGU driver"
+	default MACH_JZ4770
+	select INGENIC_CGU_COMMON
+	help
+	  Support the clocks provided by the CGU hardware on Ingenic JZ4770
+	  and compatible SoCs.
+
+	  If building for a JZ4770 SoC, you want to say Y here.
+
+config INGENIC_CGU_JZ4780
+	bool "Ingenic JZ4780 CGU driver"
+	default MACH_JZ4780
+	select INGENIC_CGU_COMMON
+	help
+	  Support the clocks provided by the CGU hardware on Ingenic JZ4780
+	  and compatible SoCs.
+
+	  If building for a JZ4780 SoC, you want to say Y here.
+
+endmenu
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index 1456e4cdb562..8b8dc79c7ce6 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -1,4 +1,4 @@
-obj-y				+= cgu.o
-obj-$(CONFIG_MACH_JZ4740)	+= jz4740-cgu.o
-obj-$(CONFIG_MACH_JZ4770)	+= jz4770-cgu.o
-obj-$(CONFIG_MACH_JZ4780)	+= jz4780-cgu.o
+obj-$(CONFIG_INGENIC_CGU_COMMON)	+= cgu.o
+obj-$(CONFIG_INGENIC_CGU_JZ4740)	+= jz4740-cgu.o
+obj-$(CONFIG_INGENIC_CGU_JZ4770)	+= jz4770-cgu.o
+obj-$(CONFIG_INGENIC_CGU_JZ4780)	+= jz4780-cgu.o
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 2/3] dt-bindings: clock: Add jz4725b-cgu.h header
  2018-08-21 12:38 [PATCH 1/3] clk: ingenic: Add proper Kconfig entries Paul Cercueil
@ 2018-08-21 12:38 ` Paul Cercueil
  2018-08-21 12:38 ` [PATCH 3/3] clk: Add Ingenic jz4725b CGU driver Paul Cercueil
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Paul Cercueil @ 2018-08-21 12:38 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland
  Cc: od, linux-kernel, linux-clk, devicetree, Paul Cercueil

This will be used from the devicetree bindings to specify the clocks
that should be obtained from the jz4725b-cgu driver.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 include/dt-bindings/clock/jz4725b-cgu.h | 35 +++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 include/dt-bindings/clock/jz4725b-cgu.h

diff --git a/include/dt-bindings/clock/jz4725b-cgu.h b/include/dt-bindings/clock/jz4725b-cgu.h
new file mode 100644
index 000000000000..460bbeff6ab8
--- /dev/null
+++ b/include/dt-bindings/clock/jz4725b-cgu.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
+
+#define JZ4725B_CLK_EXT		0
+#define JZ4725B_CLK_OSC32K	1
+#define JZ4725B_CLK_PLL		2
+#define JZ4725B_CLK_PLL_HALF	3
+#define JZ4725B_CLK_CCLK	4
+#define JZ4725B_CLK_HCLK	5
+#define JZ4725B_CLK_PCLK	6
+#define JZ4725B_CLK_MCLK	7
+#define JZ4725B_CLK_IPU		8
+#define JZ4725B_CLK_LCD		9
+#define JZ4725B_CLK_I2S		10
+#define JZ4725B_CLK_SPI		11
+#define JZ4725B_CLK_MMC_MUX	12
+#define JZ4725B_CLK_UDC		13
+#define JZ4725B_CLK_UART	14
+#define JZ4725B_CLK_DMA		15
+#define JZ4725B_CLK_ADC		16
+#define JZ4725B_CLK_I2C		17
+#define JZ4725B_CLK_AIC		18
+#define JZ4725B_CLK_MMC0	19
+#define JZ4725B_CLK_MMC1	20
+#define JZ4725B_CLK_BCH		21
+#define JZ4725B_CLK_TCU		22
+#define JZ4725B_CLK_EXT512	23
+#define JZ4725B_CLK_RTC		24
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 3/3] clk: Add Ingenic jz4725b CGU driver
  2018-08-21 12:38 [PATCH 1/3] clk: ingenic: Add proper Kconfig entries Paul Cercueil
  2018-08-21 12:38 ` [PATCH 2/3] dt-bindings: clock: Add jz4725b-cgu.h header Paul Cercueil
@ 2018-08-21 12:38 ` Paul Cercueil
  2018-08-21 18:11 ` [PATCH 1/3] clk: ingenic: Add proper Kconfig entries kbuild test robot
  2018-08-22  1:30 ` kbuild test robot
  3 siblings, 0 replies; 5+ messages in thread
From: Paul Cercueil @ 2018-08-21 12:38 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland
  Cc: od, linux-kernel, linux-clk, devicetree, Paul Cercueil

Add support for the clocks provided by the CGU in the Ingenic JZ4725B
SoC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/clk/ingenic/Kconfig       |  10 ++
 drivers/clk/ingenic/Makefile      |   1 +
 drivers/clk/ingenic/jz4725b-cgu.c | 225 ++++++++++++++++++++++++++++++
 3 files changed, 236 insertions(+)
 create mode 100644 drivers/clk/ingenic/jz4725b-cgu.c

diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index 851a5662f119..a3a158a0c946 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -14,6 +14,16 @@ config INGENIC_CGU_JZ4740
 
 	  If building for a JZ4740 SoC, you want to say Y here.
 
+config INGENIC_CGU_JZ4725B
+	bool "Ingenic JZ4725B CGU driver"
+	default MACH_JZ4725B
+	select INGENIC_CGU_COMMON
+	help
+	  Support the clocks provided by the CGU hardware on Ingenic JZ4725B
+	  and compatible SoCs.
+
+	  If building for a JZ4725B SoC, you want to say Y here.
+
 config INGENIC_CGU_JZ4770
 	bool "Ingenic JZ4770 CGU driver"
 	default MACH_JZ4770
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index 8b8dc79c7ce6..00a79b2fba10 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_INGENIC_CGU_COMMON)	+= cgu.o
 obj-$(CONFIG_INGENIC_CGU_JZ4740)	+= jz4740-cgu.o
+obj-$(CONFIG_INGENIC_CGU_JZ4725B)	+= jz4725b-cgu.o
 obj-$(CONFIG_INGENIC_CGU_JZ4770)	+= jz4770-cgu.o
 obj-$(CONFIG_INGENIC_CGU_JZ4780)	+= jz4780-cgu.o
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
new file mode 100644
index 000000000000..584ff4ff81c7
--- /dev/null
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Ingenic JZ4725B SoC CGU driver
+ *
+ * Copyright (C) 2018 Paul Cercueil
+ * Author: Paul Cercueil <paul@crapouillou.net>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <dt-bindings/clock/jz4725b-cgu.h>
+#include "cgu.h"
+
+/* CGU register offsets */
+#define CGU_REG_CPCCR		0x00
+#define CGU_REG_LCR		0x04
+#define CGU_REG_CPPCR		0x10
+#define CGU_REG_CLKGR		0x20
+#define CGU_REG_OPCR		0x24
+#define CGU_REG_I2SCDR		0x60
+#define CGU_REG_LPCDR		0x64
+#define CGU_REG_MSCCDR		0x68
+#define CGU_REG_SSICDR		0x74
+#define CGU_REG_CIMCDR		0x78
+
+/* bits within the LCR register */
+#define LCR_SLEEP		BIT(0)
+
+static struct ingenic_cgu *cgu;
+
+static const s8 pll_od_encoding[4] = {
+	0x0, 0x1, -1, 0x3,
+};
+
+static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
+
+	/* External clocks */
+
+	[JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
+	[JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
+
+	[JZ4725B_CLK_PLL] = {
+		"pll", CGU_CLK_PLL,
+		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
+		.pll = {
+			.reg = CGU_REG_CPPCR,
+			.m_shift = 23,
+			.m_bits = 9,
+			.m_offset = 2,
+			.n_shift = 18,
+			.n_bits = 5,
+			.n_offset = 2,
+			.od_shift = 16,
+			.od_bits = 2,
+			.od_max = 4,
+			.od_encoding = pll_od_encoding,
+			.stable_bit = 10,
+			.bypass_bit = 9,
+			.enable_bit = 8,
+		},
+	},
+
+	/* Muxes & dividers */
+
+	[JZ4725B_CLK_PLL_HALF] = {
+		"pll half", CGU_CLK_DIV,
+		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+		.div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
+	},
+
+	[JZ4725B_CLK_CCLK] = {
+		"cclk", CGU_CLK_DIV,
+		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+		.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
+	},
+
+	[JZ4725B_CLK_HCLK] = {
+		"hclk", CGU_CLK_DIV,
+		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+		.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
+	},
+
+	[JZ4725B_CLK_PCLK] = {
+		"pclk", CGU_CLK_DIV,
+		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+		.div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
+	},
+
+	[JZ4725B_CLK_MCLK] = {
+		"mclk", CGU_CLK_DIV,
+		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+		.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
+	},
+
+	[JZ4725B_CLK_IPU] = {
+		"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+		.div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 13 },
+	},
+
+	[JZ4725B_CLK_LCD] = {
+		"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
+		.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 9 },
+	},
+
+	[JZ4725B_CLK_I2S] = {
+		"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
+		.mux = { CGU_REG_CPCCR, 31, 1 },
+		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 6 },
+	},
+
+	[JZ4725B_CLK_SPI] = {
+		"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
+		.mux = { CGU_REG_SSICDR, 31, 1 },
+		.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 4 },
+	},
+
+	[JZ4725B_CLK_MMC_MUX] = {
+		"mmc_mux", CGU_CLK_DIV,
+		.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
+		.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
+	},
+
+	[JZ4725B_CLK_UDC] = {
+		"udc", CGU_CLK_MUX | CGU_CLK_DIV,
+		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
+		.mux = { CGU_REG_CPCCR, 29, 1 },
+		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
+	},
+
+	/* Gate-only clocks */
+
+	[JZ4725B_CLK_UART] = {
+		"uart", CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 0 },
+	},
+
+	[JZ4725B_CLK_DMA] = {
+		"dma", CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 12 },
+	},
+
+	[JZ4725B_CLK_ADC] = {
+		"adc", CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 7 },
+	},
+
+	[JZ4725B_CLK_I2C] = {
+		"i2c", CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 3 },
+	},
+
+	[JZ4725B_CLK_AIC] = {
+		"aic", CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 5 },
+	},
+
+	[JZ4725B_CLK_MMC0] = {
+		"mmc0", CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 6 },
+	},
+
+	[JZ4725B_CLK_MMC1] = {
+		"mmc1", CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 16 },
+	},
+
+	[JZ4725B_CLK_BCH] = {
+		"bch", CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 11 },
+	},
+
+	[JZ4725B_CLK_TCU] = {
+		"tcu", CGU_CLK_GATE,
+		.parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR, 1 },
+	},
+
+	[JZ4725B_CLK_EXT512] = {
+		"ext/512", CGU_CLK_FIXDIV,
+		.parents = { JZ4725B_CLK_EXT },
+
+		/* Doc calls it EXT512, but it seems to be /256... */
+		.fixdiv = { 256 },
+	},
+
+	[JZ4725B_CLK_RTC] = {
+		"rtc", CGU_CLK_MUX,
+		.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
+		.mux = { CGU_REG_OPCR, 2, 1},
+	},
+};
+
+static void __init jz4725b_cgu_init(struct device_node *np)
+{
+	int retval;
+
+	cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
+			      ARRAY_SIZE(jz4725b_cgu_clocks), np);
+	if (!cgu) {
+		pr_err("%s: failed to initialise CGU\n", __func__);
+		return;
+	}
+
+	retval = ingenic_cgu_register_clocks(cgu);
+	if (retval)
+		pr_err("%s: failed to register CGU Clocks\n", __func__);
+}
+CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/3] clk: ingenic: Add proper Kconfig entries
  2018-08-21 12:38 [PATCH 1/3] clk: ingenic: Add proper Kconfig entries Paul Cercueil
  2018-08-21 12:38 ` [PATCH 2/3] dt-bindings: clock: Add jz4725b-cgu.h header Paul Cercueil
  2018-08-21 12:38 ` [PATCH 3/3] clk: Add Ingenic jz4725b CGU driver Paul Cercueil
@ 2018-08-21 18:11 ` kbuild test robot
  2018-08-22  1:30 ` kbuild test robot
  3 siblings, 0 replies; 5+ messages in thread
From: kbuild test robot @ 2018-08-21 18:11 UTC (permalink / raw)
  To: Paul Cercueil
  Cc: kbuild-all, Michael Turquette, Stephen Boyd, Rob Herring,
	Mark Rutland, od, linux-kernel, linux-clk, devicetree,
	Paul Cercueil

[-- Attachment #1: Type: text/plain, Size: 1503 bytes --]

Hi Paul,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on clk/clk-next]
[also build test ERROR on v4.18 next-20180821]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Paul-Cercueil/clk-ingenic-Add-proper-Kconfig-entries/20180822-003241
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

>> drivers/clk/ingenic/jz4740-cgu.c:22:10: fatal error: asm/mach-jz4740/clock.h: No such file or directory
    #include <asm/mach-jz4740/clock.h>
             ^~~~~~~~~~~~~~~~~~~~~~~~~
   compilation terminated.

vim +22 drivers/clk/ingenic/jz4740-cgu.c

41dd641e Paul Burton 2015-05-24 @22  #include <asm/mach-jz4740/clock.h>
ff1930c6 Paul Burton 2015-05-24  23  #include "cgu.h"
ff1930c6 Paul Burton 2015-05-24  24  

:::::: The code at line 22 was first introduced by commit
:::::: 41dd641e9a1a7229383f9b342a57cb6720e7ea46 MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu

:::::: TO: Paul Burton <paul.burton@imgtec.com>
:::::: CC: Ralf Baechle <ralf@linux-mips.org>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 64124 bytes --]

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/3] clk: ingenic: Add proper Kconfig entries
  2018-08-21 12:38 [PATCH 1/3] clk: ingenic: Add proper Kconfig entries Paul Cercueil
                   ` (2 preceding siblings ...)
  2018-08-21 18:11 ` [PATCH 1/3] clk: ingenic: Add proper Kconfig entries kbuild test robot
@ 2018-08-22  1:30 ` kbuild test robot
  3 siblings, 0 replies; 5+ messages in thread
From: kbuild test robot @ 2018-08-22  1:30 UTC (permalink / raw)
  To: Paul Cercueil
  Cc: kbuild-all, Michael Turquette, Stephen Boyd, Rob Herring,
	Mark Rutland, od, linux-kernel, linux-clk, devicetree,
	Paul Cercueil

Hi Paul,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on v4.18 next-20180821]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Paul-Cercueil/clk-ingenic-Add-proper-Kconfig-entries/20180822-003241
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

>> drivers/clk/ingenic/cgu.c:137:13: sparse: expression using sizeof(void)
>> drivers/clk/ingenic/cgu.c:137:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:138:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:138:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:141:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:141:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:142:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:142:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:408:15: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:408:15: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:409:15: sparse: expression using sizeof(void)
   include/linux/slab.h:631:13: sparse: undefined identifier '__builtin_mul_overflow'

vim +137 drivers/clk/ingenic/cgu.c

b066303f Paul Burton 2015-05-24  120  
b066303f Paul Burton 2015-05-24  121  static unsigned long
b066303f Paul Burton 2015-05-24  122  ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
b066303f Paul Burton 2015-05-24  123  		 unsigned long rate, unsigned long parent_rate,
b066303f Paul Burton 2015-05-24  124  		 unsigned *pm, unsigned *pn, unsigned *pod)
b066303f Paul Burton 2015-05-24  125  {
b066303f Paul Burton 2015-05-24  126  	const struct ingenic_cgu_pll_info *pll_info;
b066303f Paul Burton 2015-05-24  127  	unsigned m, n, od;
b066303f Paul Burton 2015-05-24  128  
b066303f Paul Burton 2015-05-24  129  	pll_info = &clk_info->pll;
b066303f Paul Burton 2015-05-24  130  	od = 1;
b066303f Paul Burton 2015-05-24  131  
b066303f Paul Burton 2015-05-24  132  	/*
b066303f Paul Burton 2015-05-24  133  	 * The frequency after the input divider must be between 10 and 50 MHz.
b066303f Paul Burton 2015-05-24  134  	 * The highest divider yields the best resolution.
b066303f Paul Burton 2015-05-24  135  	 */
b066303f Paul Burton 2015-05-24  136  	n = parent_rate / (10 * MHZ);
b066303f Paul Burton 2015-05-24 @137  	n = min_t(unsigned, n, 1 << clk_info->pll.n_bits);
b066303f Paul Burton 2015-05-24  138  	n = max_t(unsigned, n, pll_info->n_offset);
b066303f Paul Burton 2015-05-24  139  
b066303f Paul Burton 2015-05-24  140  	m = (rate / MHZ) * od * n / (parent_rate / MHZ);
b066303f Paul Burton 2015-05-24  141  	m = min_t(unsigned, m, 1 << clk_info->pll.m_bits);
b066303f Paul Burton 2015-05-24  142  	m = max_t(unsigned, m, pll_info->m_offset);
b066303f Paul Burton 2015-05-24  143  
b066303f Paul Burton 2015-05-24  144  	if (pm)
b066303f Paul Burton 2015-05-24  145  		*pm = m;
b066303f Paul Burton 2015-05-24  146  	if (pn)
b066303f Paul Burton 2015-05-24  147  		*pn = n;
b066303f Paul Burton 2015-05-24  148  	if (pod)
b066303f Paul Burton 2015-05-24  149  		*pod = od;
b066303f Paul Burton 2015-05-24  150  
b066303f Paul Burton 2015-05-24  151  	return div_u64((u64)parent_rate * m, n * od);
b066303f Paul Burton 2015-05-24  152  }
b066303f Paul Burton 2015-05-24  153  

:::::: The code at line 137 was first introduced by commit
:::::: b066303fb3e72a902a1f94dc06636ce82c3a5577 clk: ingenic: add driver for Ingenic SoC CGU clocks

:::::: TO: Paul Burton <paul.burton@imgtec.com>
:::::: CC: Ralf Baechle <ralf@linux-mips.org>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2018-08-22  1:33 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-21 12:38 [PATCH 1/3] clk: ingenic: Add proper Kconfig entries Paul Cercueil
2018-08-21 12:38 ` [PATCH 2/3] dt-bindings: clock: Add jz4725b-cgu.h header Paul Cercueil
2018-08-21 12:38 ` [PATCH 3/3] clk: Add Ingenic jz4725b CGU driver Paul Cercueil
2018-08-21 18:11 ` [PATCH 1/3] clk: ingenic: Add proper Kconfig entries kbuild test robot
2018-08-22  1:30 ` kbuild test robot

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