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* [PATCH v13 00/13] Intel SGX1 support
@ 2018-08-27 18:53 Jarkko Sakkinen
  2018-08-27 18:53 ` [PATCH v13 01/13] x86/sgx: Update MAINTAINERS Jarkko Sakkinen
                   ` (12 more replies)
  0 siblings, 13 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Alexei Starovoitov, Andi Kleen,
	Andrew Morton, Andy Lutomirski, Arnd Bergmann, Borislav Petkov,
	David S. Miller, David Woodhouse, Eric Biggers,
	Greg Kroah-Hartman, Herbert Xu, H. Peter Anvin, Ingo Molnar,
	Janakarajan Natarajan, Kirill A. Shutemov, Konrad Rzeszutek Wilk,
	open list:KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86),
	open list:DOCUMENTATION, open list, Matt Turner,
	Mauro Carvalho Chehab, Paolo Bonzini, Peter Zijlstra,
	Rafael J. Wysocki, Reinette Chatre, Ricardo Neri, Serge Ayoun,
	Shay Katz-zamir, Suresh Siddha, Thomas Gleixner, Tom Lendacky

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Intel(R) SGX is a set of CPU instructions that can be used by applications
to set aside private regions of code and data. The code outside the enclave
is disallowed to access the memory inside the enclave by the CPU access
control.  In a way you can think that SGX provides inverted sandbox. It
protects the application from a malicious host.

There is a new hardware unit in the processor called Memory Encryption
Engine (MEE) starting from the Skylake microacrhitecture. BIOS can define
one or many MEE regions that can hold enclave data by configuring them with
PRMRR registers.

The MEE automatically encrypts the data leaving the processor package to
the MEE regions. The data is encrypted using a random key whose life-time
is exactly one power cycle.

The current implementation requires that the firmware sets
IA32_SGXLEPUBKEYHASH* MSRs as writable so that ultimately the kernel can
decide what enclaves it wants run. The implementation does not create
any bottlenecks to support read-only MSRs later on.

You can tell if your CPU supports SGX by looking into /proc/cpuinfo:

	cat /proc/cpuinfo  | grep sgx

v13:
* Always use SGX_CPUID constant instead of a hardcoded value.
* Simplified and documented the macros and functions for ENCLS leaves.
* Enable sgx_free_page() to free active enclave pages on demand
  in order to allow sgx_invalidate() to delete enclave pages.
  It no longer performs EREMOVE if a page is in the process of
  being reclaimed.
* Use PM notifier per enclave so that we don't have to traverse
  the global list of active EPC pages to find enclaves.
* Removed unused SGX_LE_ROLLBACK constant from uapi/asm/sgx.h
* Always use ioremap() to map EPC banks as we only support 64-bit kernel.
* Invalidate IA32_SGXLEPUBKEYHASH cache used by sgx_einit() when going
  to sleep.

v12:
* Split to more narrow scoped commits in order to ease the review process and
  use co-developed-by tag for co-authors of commits instead of listing them in
  the source files.
* Removed cruft EXPORT_SYMBOL() declarations and converted to static variables.
* Removed in-kernel LE i.e. this version of the SGX software stack only
  supports unlocked IA32_SGXLEPUBKEYHASHx MSRs.
* Refined documentation on launching enclaves, swapping and enclave
  construction.
* Refined sgx_arch.h to include alignment information for every struct that
  requires it and removed structs that are not needed without an LE.
* Got rid of SGX_CPUID.
* SGX detection now prints log messages about firmware configuration issues.

v11:
* Polished ENCLS wrappers with refined exception handling.
* ksgxswapd was not stopped (regression in v5) in
  sgx_page_cache_teardown(), which causes a leaked kthread after driver
  deinitialization.
* Shutdown sgx_le_proxy when going to suspend because its EPC pages will be
  invalidated when resuming, which will cause it not function properly
  anymore.
* Set EINITTOKEN.VALID to zero for a token that is passed when
  SGXLEPUBKEYHASH matches MRSIGNER as alloc_page() does not give a zero
  page.
* Fixed the check in sgx_edbgrd() for a TCS page. Allowed to read offsets
  around the flags field, which causes a #GP. Only flags read is readable.
* On read access memcpy() call inside sgx_vma_access() had src and dest
  parameters in wrong order.
* The build issue with CONFIG_KASAN is now fixed. Added undefined symbols
  to LE even if “KASAN_SANITIZE := false” was set in the makefile. 
* Fixed a regression in the #PF handler. If a page has
  SGX_ENCL_PAGE_RESERVED flag the #PF handler should unconditionally fail.
  It did not, which caused weird races when trying to change other parts of
  swapping code.
* EPC management has been refactored to a flat LRU cache and moved to
  arch/x86. The swapper thread reads a cluster of EPC pages and swaps all
  of them. It can now swap from multiple enclaves in the same round.
* For the sake of consistency with SGX_IOC_ENCLAVE_ADD_PAGE, return -EINVAL
  when an enclave is already initialized or dead instead of zero.

v10:
* Cleaned up anon inode based IPC between the ring-0 and ring-3 parts
  of the driver.
* Unset the reserved flag from an enclave page if EDBGRD/WR fails
  (regression in v6).
* Close the anon inode when LE is stopped (regression in v9).
* Update the documentation with a more detailed description of SGX.

v9:
* Replaced kernel-LE IPC based on pipes with an anonymous inode.
  The driver does not require anymore new exports.

v8:
* Check that public key MSRs match the LE public key hash in the
  driver initialization when the MSRs are read-only.
* Fix the race in VA slot allocation by checking the fullness
  immediately after succeesful allocation.
* Fix the race in hash mrsigner calculation between the launch
  enclave and user enclaves by having a separate lock for hash
  calculation.

v7:
* Fixed offset calculation in sgx_edbgr/wr(). Address was masked with PAGE_MASK
  when it should have been masked with ~PAGE_MASK.
* Fixed a memory leak in sgx_ioc_enclave_create().
* Simplified swapping code by using a pointer array for a cluster
  instead of a linked list.
* Squeezed struct sgx_encl_page to 32 bytes.
* Fixed deferencing of an RSA key on OpenSSL 1.1.0.
* Modified TC's CMAC to use kernel AES-NI. Restructured the code
  a bit in order to better align with kernel conventions.

v6:
* Fixed semaphore underrun when accessing /dev/sgx from the launch enclave.
* In sgx_encl_create() s/IS_ERR(secs)/IS_ERR(encl)/.
* Removed virtualization chapter from the documentation.
* Changed the default filename for the signing key as signing_key.pem.
* Reworked EPC management in a way that instead of a linked list of
  struct sgx_epc_page instances there is an array of integers that
  encodes address and bank of an EPC page (the same data as 'pa' field
  earlier). The locking has been moved to the EPC bank level instead
  of a global lock.
* Relaxed locking requirements for EPC management. EPC pages can be
  released back to the EPC bank concurrently.
* Cleaned up ptrace() code.
* Refined commit messages for new architectural constants.
* Sorted includes in every source file.
* Sorted local variable declarations according to the line length in
  every function.
* Style fixes based on Darren's comments to sgx_le.c.

v5:
* Described IPC between the Launch Enclave and kernel in the commit messages.
* Fixed all relevant checkpatch.pl issues that I have forgot fix in earlier
  versions except those that exist in the imported TinyCrypt code.
* Fixed spelling mistakes in the documentation.
* Forgot to check the return value of sgx_drv_subsys_init().
* Encapsulated properly page cache init and teardown.
* Collect epc pages to a temp list in sgx_add_epc_bank
* Removed SGX_ENCLAVE_INIT_ARCH constant.

v4:
* Tied life-cycle of the sgx_le_proxy process to /dev/sgx.
* Removed __exit annotation from sgx_drv_subsys_exit().
* Fixed a leak of a backing page in sgx_process_add_page_req() in the
  case when vm_insert_pfn() fails.
* Removed unused symbol exports for sgx_page_cache.c.
* Updated sgx_alloc_page() to require encl parameter and documented the
  behavior (Sean Christopherson).
* Refactored a more lean API for sgx_encl_find() and documented the behavior.
* Moved #PF handler to sgx_fault.c.
* Replaced subsys_system_register() with plain bus_register().
* Retry EINIT 2nd time only if MSRs are not locked.

v3:
* Check that FEATURE_CONTROL_LOCKED and FEATURE_CONTROL_SGX_ENABLE are set.
* Return -ERESTARTSYS in __sgx_encl_add_page() when sgx_alloc_page() fails.
* Use unused bits in epc_page->pa to store the bank number.
* Removed #ifdef for WQ_NONREENTRANT.
* If mmu_notifier_register() fails with -EINTR, return -ERESTARTSYS.
* Added --remove-section=.got.plt to objcopy flags in order to prevent a
  dummy .got.plt, which will cause an inconsistent size for the LE.
* Documented sgx_encl_* functions.
* Added remark about AES implementation used inside the LE.
* Removed redundant sgx_sys_exit() from le/main.c.
* Fixed struct sgx_secinfo alignment from 128 to 64 bytes.
* Validate miscselect in sgx_encl_create().
* Fixed SSA frame size calculation to take the misc region into account.
* Implemented consistent exception handling to __encls() and __encls_ret().
* Implemented a proper device model in order to allow sysfs attributes
  and in-kernel API.
* Cleaned up various "find enclave" implementations to the unified
  sgx_encl_find().
* Validate that vm_pgoff is zero.
* Discard backing pages with shmem_truncate_range() after EADD.
* Added missing EEXTEND operations to LE signing and launch.
* Fixed SSA size for GPRS region from 168 to 184 bytes.
* Fixed the checks for TCS flags. Now DBGOPTIN is allowed.
* Check that TCS addresses are in ELRANGE and not just page aligned.
* Require kernel to be compiled with X64_64 and CPU_SUP_INTEL.
* Fixed an incorrect value for SGX_ATTR_DEBUG from 0x01 to 0x02.

v2:
* get_rand_uint32() changed the value of the pointer instead of value
  where it is pointing at.
* Launch enclave incorrectly used sigstruct attributes-field instead of
  enclave attributes-field.
* Removed unused struct sgx_add_page_req from sgx_ioctl.c
* Removed unused sgx_has_sgx2.
* Updated arch/x86/include/asm/sgx.h so that it provides stub
  implementations when sgx in not enabled.
* Removed cruft rdmsr-calls from sgx_set_pubkeyhash_msrs().
* return -ENOMEM in sgx_alloc_page() when VA pages consume too much space
* removed unused global sgx_nr_pids
* moved sgx_encl_release to sgx_encl.c
* return -ERESTARTSYS instead of -EINTR in sgx_encl_init()

Jarkko Sakkinen (8):
  x86/sgx: Update MAINTAINERS
  x86/sgx: Architectural structures
  x86/sgx: Add data structures for tracking the EPC pages
  x86/sgx: Add wrappers for ENCLS leaf functions
  x86/sgx: Enclave Page Cache (EPC) memory manager
  platform/x86: Intel SGX driver
  platform/x86: ptrace() support for the SGX driver
  x86/sgx: Driver documentation

Kai Huang (1):
  x86/cpufeature: Add SGX and SGX_LC CPU features

Sean Christopherson (4):
  x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX
  x86/msr: Add SGX definitions to msr-index.h
  x86/sgx: Detect Intel SGX
  x86/sgx: Add sgx_einit() for initializing enclaves

 Documentation/index.rst                       |    1 +
 Documentation/x86/intel_sgx.rst               |  185 +++
 MAINTAINERS                                   |    7 +
 arch/x86/Kconfig                              |   19 +
 arch/x86/include/asm/cpufeature.h             |    7 +-
 arch/x86/include/asm/cpufeatures.h            |   10 +-
 arch/x86/include/asm/disabled-features.h      |    3 +-
 arch/x86/include/asm/msr-index.h              |    8 +
 arch/x86/include/asm/required-features.h      |    3 +-
 arch/x86/include/asm/sgx.h                    |  359 ++++++
 arch/x86/include/asm/sgx_arch.h               |  379 ++++++
 arch/x86/include/asm/sgx_pr.h                 |   13 +
 arch/x86/include/uapi/asm/sgx.h               |  112 ++
 arch/x86/include/uapi/asm/sgx_errno.h         |   91 ++
 arch/x86/kernel/cpu/Makefile                  |    1 +
 arch/x86/kernel/cpu/common.c                  |    7 +
 arch/x86/kernel/cpu/intel_sgx.c               |  551 +++++++++
 arch/x86/kvm/cpuid.h                          |    1 +
 drivers/platform/x86/Kconfig                  |    2 +
 drivers/platform/x86/Makefile                 |    1 +
 drivers/platform/x86/intel_sgx/Kconfig        |   22 +
 drivers/platform/x86/intel_sgx/Makefile       |   13 +
 drivers/platform/x86/intel_sgx/sgx.h          |  211 ++++
 drivers/platform/x86/intel_sgx/sgx_encl.c     | 1016 +++++++++++++++++
 .../platform/x86/intel_sgx/sgx_encl_page.c    |  288 +++++
 drivers/platform/x86/intel_sgx/sgx_fault.c    |  157 +++
 drivers/platform/x86/intel_sgx/sgx_ioctl.c    |  234 ++++
 drivers/platform/x86/intel_sgx/sgx_main.c     |  257 +++++
 drivers/platform/x86/intel_sgx/sgx_vma.c      |  167 +++
 29 files changed, 4120 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/x86/intel_sgx.rst
 create mode 100644 arch/x86/include/asm/sgx.h
 create mode 100644 arch/x86/include/asm/sgx_arch.h
 create mode 100644 arch/x86/include/asm/sgx_pr.h
 create mode 100644 arch/x86/include/uapi/asm/sgx.h
 create mode 100644 arch/x86/include/uapi/asm/sgx_errno.h
 create mode 100644 arch/x86/kernel/cpu/intel_sgx.c
 create mode 100644 drivers/platform/x86/intel_sgx/Kconfig
 create mode 100644 drivers/platform/x86/intel_sgx/Makefile
 create mode 100644 drivers/platform/x86/intel_sgx/sgx.h
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_encl.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_encl_page.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_fault.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_ioctl.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_main.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_vma.c

-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 01/13] x86/sgx: Update MAINTAINERS
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-09-03 12:56   ` Andy Shevchenko
  2018-08-27 18:53 ` [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features Jarkko Sakkinen
                   ` (11 subsequent siblings)
  12 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, David S. Miller,
	Mauro Carvalho Chehab, Greg Kroah-Hartman, Andrew Morton,
	Arnd Bergmann, open list

Add the maintainer information for the SGX subsystem.

Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 24b200d91b30..877fbc6ef7a7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7562,6 +7562,13 @@ L:	linux-gpio@vger.kernel.org
 S:	Maintained
 F:	drivers/gpio/gpio-intel-mid.c
 
+INTEL SGX
+M:	Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
+L:	linux-sgx@vger.kernel.org
+Q:	https://patchwork.kernel.org/project/intel-sgx/list/
+F:	drivers/platform/x86/intel_sgx/
+K:	\bSGX_
+
 INVENSENSE MPU-3050 GYROSCOPE DRIVER
 M:	Linus Walleij <linus.walleij@linaro.org>
 L:	linux-iio@vger.kernel.org
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
  2018-08-27 18:53 ` [PATCH v13 01/13] x86/sgx: Update MAINTAINERS Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-28  0:07   ` Huang, Kai
  2018-08-31 16:18   ` Dr. Greg
  2018-08-27 18:53 ` [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX Jarkko Sakkinen
                   ` (10 subsequent siblings)
  12 siblings, 2 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Kai Huang, Jarkko Sakkinen, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Borislav Petkov,
	Konrad Rzeszutek Wilk, David Woodhouse,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

From: Kai Huang <kai.huang@linux.intel.com>

Add X86_FEATURE_SGX and X86_FEATURE_SGX_LC that define the bits
determining whether the CPU supports SGX and user launch configuration
i.e. using a custom root key rather the Intel proprietary key for
enclave signing.

Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 89a048c2faec..7bb647f57d42 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -236,6 +236,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
 #define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
 #define X86_FEATURE_TSC_ADJUST		( 9*32+ 1) /* TSC adjustment MSR 0x3B */
+#define X86_FEATURE_SGX			( 9*32+ 2) /* Software Guard Extensions */
 #define X86_FEATURE_BMI1		( 9*32+ 3) /* 1st group bit manipulation extensions */
 #define X86_FEATURE_HLE			( 9*32+ 4) /* Hardware Lock Elision */
 #define X86_FEATURE_AVX2		( 9*32+ 5) /* AVX2 instructions */
@@ -331,6 +332,7 @@
 #define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */
 #define X86_FEATURE_RDPID		(16*32+22) /* RDPID instruction */
 #define X86_FEATURE_CLDEMOTE		(16*32+25) /* CLDEMOTE instruction */
+#define X86_FEATURE_SGX_LC		(16*32+30) /* supports SGX launch configuration */
 
 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
 #define X86_FEATURE_OVERFLOW_RECOV	(17*32+ 0) /* MCA overflow recovery support */
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
  2018-08-27 18:53 ` [PATCH v13 01/13] x86/sgx: Update MAINTAINERS Jarkko Sakkinen
  2018-08-27 18:53 ` [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-27 19:39   ` Dave Hansen
  2018-08-28 10:21   ` Borislav Petkov
  2018-08-27 18:53 ` [PATCH v13 04/13] x86/sgx: Architectural structures Jarkko Sakkinen
                   ` (9 subsequent siblings)
  12 siblings, 2 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Paolo Bonzini, Radim Krčmář,
	Peter Zijlstra, Borislav Petkov, Greg Kroah-Hartman,
	David Woodhouse, Alexei Starovoitov, Andi Kleen,
	Konrad Rzeszutek Wilk, Ricardo Neri, Kirill A. Shutemov,
	Andy Lutomirski, open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	open list:KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)

From: Sean Christopherson <sean.j.christopherson@intel.com>

CPUID_12_EAX is an Intel-defined feature bits leaf dedicated for SGX.
There are currently four documented feature bits, with more expected in
the not-too-distant future.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 arch/x86/include/asm/cpufeature.h        | 7 +++++--
 arch/x86/include/asm/cpufeatures.h       | 8 +++++++-
 arch/x86/include/asm/disabled-features.h | 3 ++-
 arch/x86/include/asm/required-features.h | 3 ++-
 arch/x86/kernel/cpu/common.c             | 7 +++++++
 arch/x86/kvm/cpuid.h                     | 1 +
 6 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index aced6c9290d6..940f0c01d5f8 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -30,6 +30,7 @@ enum cpuid_leafs
 	CPUID_7_ECX,
 	CPUID_8000_0007_EBX,
 	CPUID_7_EDX,
+	CPUID_12_EAX,
 };
 
 #ifdef CONFIG_X86_FEATURE_NAMES
@@ -81,8 +82,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
 	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) ||	\
 	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) ||	\
 	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) ||	\
+	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) ||	\
 	   REQUIRED_MASK_CHECK					  ||	\
-	   BUILD_BUG_ON_ZERO(NCAPINTS != 19))
+	   BUILD_BUG_ON_ZERO(NCAPINTS != 20))
 
 #define DISABLED_MASK_BIT_SET(feature_bit)				\
 	 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||	\
@@ -104,8 +106,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
 	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) ||	\
 	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) ||	\
 	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) ||	\
+	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) ||	\
 	   DISABLED_MASK_CHECK					  ||	\
-	   BUILD_BUG_ON_ZERO(NCAPINTS != 19))
+	   BUILD_BUG_ON_ZERO(NCAPINTS != 20))
 
 #define cpu_has(c, bit)							\
 	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 7bb647f57d42..4af60a0fdb20 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -13,7 +13,7 @@
 /*
  * Defines x86 CPU feature bits
  */
-#define NCAPINTS			19	   /* N 32-bit words worth of info */
+#define NCAPINTS			20	   /* N 32-bit words worth of info */
 #define NBUGINTS			1	   /* N 32-bit bug flags */
 
 /*
@@ -349,6 +349,12 @@
 #define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
 #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */
 
+/* Intel SGX CPU features, CPUID level 0x000000012:0 (EAX), word 19 */
+#define X86_FEATURE_SGX1		(19*32+ 0) /* SGX1 leaf functions */
+#define X86_FEATURE_SGX2		(19*32+ 1) /* SGX2 leaf functions */
+#define X86_FEATURE_SGX_ENCLV		(19*32+ 5) /* SGX ENCLV instruction, leafs E[INC|DEC]VIRTCHILD, ESETCONTEXT */
+#define X86_FEATURE_SGX_ENCLS_C		(19*32+ 6) /* SGX ENCLS leafs ERDINFO, ETRACK, ELDBC and ELDUC */
+
 /*
  * BUG word(s)
  */
diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
index 33833d1909af..c81b5d446a3e 100644
--- a/arch/x86/include/asm/disabled-features.h
+++ b/arch/x86/include/asm/disabled-features.h
@@ -78,6 +78,7 @@
 #define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP)
 #define DISABLED_MASK17	0
 #define DISABLED_MASK18	0
-#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
+#define DISABLED_MASK19	0
+#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
 
 #endif /* _ASM_X86_DISABLED_FEATURES_H */
diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index 6847d85400a8..fa5700097f64 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -101,6 +101,7 @@
 #define REQUIRED_MASK16	0
 #define REQUIRED_MASK17	0
 #define REQUIRED_MASK18	0
-#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
+#define REQUIRED_MASK19	0
+#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
 
 #endif /* _ASM_X86_REQUIRED_FEATURES_H */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 84dee5ab745a..211c76322ddf 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -866,6 +866,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
 		}
 	}
 
+	/* Intel SGX features: level 0x00000012 */
+	if (c->cpuid_level >= 0x00000012) {
+		cpuid(0x00000012, &eax, &ebx, &ecx, &edx);
+
+		c->x86_capability[CPUID_12_EAX] = eax;
+	}
+
 	/* AMD-defined flags: level 0x80000001 */
 	eax = cpuid_eax(0x80000000);
 	c->extended_cpuid_level = eax;
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index 9a327d5b6d1f..669c1774afdb 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -55,6 +55,7 @@ static const struct cpuid_reg reverse_cpuid[] = {
 	[CPUID_7_ECX]         = {         7, 0, CPUID_ECX},
 	[CPUID_8000_0007_EBX] = {0x80000007, 0, CPUID_EBX},
 	[CPUID_7_EDX]         = {         7, 0, CPUID_EDX},
+	[CPUID_12_EAX]        = {        12, 0, CPUID_EAX},
 };
 
 static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned x86_feature)
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 04/13] x86/sgx: Architectural structures
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (2 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-27 19:41   ` Dave Hansen
  2018-09-03 13:16   ` Andy Shevchenko
  2018-08-27 18:53 ` [PATCH v13 05/13] x86/msr: Add SGX definitions to msr-index.h Jarkko Sakkinen
                   ` (8 subsequent siblings)
  12 siblings, 2 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

Add arch/x86/include/asm/sgx_arch.h, which contains definitions for the
architectural data structures used by the CPU to implement the SGX.

Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 arch/x86/include/asm/sgx_arch.h       | 379 ++++++++++++++++++++++++++
 arch/x86/include/uapi/asm/sgx_errno.h |  91 +++++++
 2 files changed, 470 insertions(+)
 create mode 100644 arch/x86/include/asm/sgx_arch.h
 create mode 100644 arch/x86/include/uapi/asm/sgx_errno.h

diff --git a/arch/x86/include/asm/sgx_arch.h b/arch/x86/include/asm/sgx_arch.h
new file mode 100644
index 000000000000..395123d7c13f
--- /dev/null
+++ b/arch/x86/include/asm/sgx_arch.h
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-17 Intel Corporation.
+//
+// Contains the architectural data structures used by the CPU to implement SGX.
+// The data structures defined to be used by the Linux software stack should not
+// be placed here.
+
+#ifndef _ASM_X86_SGX_ARCH_H
+#define _ASM_X86_SGX_ARCH_H
+
+#include <linux/types.h>
+#include <uapi/asm/sgx_errno.h>
+
+#define SGX_CPUID 0x12
+
+/**
+ * enum sgx_encls_leaves - ENCLS leaf functions
+ * %ECREATE:	Create an enclave.
+ * %EADD:	Add a page to an enclave.
+ * %EINIT:	Launch an enclave.
+ * %EREMOVE:	Remove a page from an enclave.
+ * %EDBGRD:	Read a word from an enclve (peek).
+ * %EDBGWR:	Write a word to an enclave (poke).
+ * %EEXTEND:	Measure 256 bytes of an added enclave page.
+ * %ELDB:	Load a swapped page in blocked state.
+ * %ELDU:	Load a swapped page in unblocked state.
+ * %EBLOCK:	Change page state to blocked i.e. entering hardware threads
+ *		cannot access it and create new TLB entries.
+ * %EPA:	Create a Version Array (VA) page used to store isvsvn number
+ *		for a swapped EPC page.
+ * %EWB:	Swap an enclave page to the regular memory. Checks that all
+ *		threads have exited that were in the previous shoot-down
+ *		sequence.
+ * %ETRACK:	Start a new shoot down sequence. Used to together with EBLOCK
+ *		to make sure that a page is safe to swap.
+ */
+enum sgx_encls_leaves {
+	ECREATE	= 0x0,
+	EADD	= 0x1,
+	EINIT	= 0x2,
+	EREMOVE	= 0x3,
+	EDGBRD	= 0x4,
+	EDGBWR	= 0x5,
+	EEXTEND	= 0x6,
+	ELDB	= 0x7,
+	ELDU	= 0x8,
+	EBLOCK	= 0x9,
+	EPA	= 0xA,
+	EWB	= 0xB,
+	ETRACK	= 0xC,
+	EAUG	= 0xD,
+	EMODPR	= 0xE,
+	EMODT	= 0xF,
+};
+
+#define SGX_MODULUS_SIZE 384
+
+/**
+ * enum sgx_miscselect - additional information to an SSA frame
+ * %SGX_MISC_EXINFO:	Report #PF or #GP to the SSA frame.
+ *
+ * Save State Area (SSA) is a stack inside the enclave used to store processor
+ * state when an exception or interrupt occurs. This enum defines additional
+ * information stored to an SSA frame.
+ */
+enum sgx_miscselect {
+	SGX_MISC_EXINFO		= 0x01,
+};
+
+#define SGX_MISC_RESERVED_MASK 0xFFFFFFFFFFFFFFFEULL
+
+#define SGX_SSA_GPRS_SIZE		182
+#define SGX_SSA_MISC_EXINFO_SIZE	16
+
+/**
+ * enum sgx_attributes - attributes that define enclave privileges.
+ * %SGX_ATTR_DEBUG:		Allow ENCLS(EDBGRD) and ENCLS(EDBGWR).
+ * %SGX_ATTR_MODE64BIT:		Tell that this a 64-bit enclave.
+ * %SGX_ATTR_PROVISIONKEY:      Allow to use provisioning keys used in the
+ *				remote attestation.
+ * %SGX_EINITTOKENKEY:		Allow to use token signing key used to allow to
+ *				run enclaves.
+ */
+enum sgx_attribute {
+	SGX_ATTR_DEBUG		= 0x02,
+	SGX_ATTR_MODE64BIT	= 0x04,
+	SGX_ATTR_PROVISIONKEY	= 0x10,
+	SGX_ATTR_EINITTOKENKEY	= 0x20,
+};
+
+#define SGX_ATTR_RESERVED_MASK 0xFFFFFFFFFFFFFFC9ULL
+
+#define SGX_SECS_RESERVED1_SIZE 24
+#define SGX_SECS_RESERVED2_SIZE 32
+#define SGX_SECS_RESERVED3_SIZE 96
+#define SGX_SECS_RESERVED4_SIZE 3836
+
+/**
+ * struct sgx_secs - SGX Enclave Control Structure (SECS)
+ * @size:		size of the address space
+ * @base:		base address of the  address space
+ * @ssa_frame_size:	size of an SSA frame
+ * @miscselect:		additional information stored to an SSA frame
+ * @attributes:		attributes for enclave
+ * @xfrm:		XSave-Feature Request Mask (subset of XCR0)
+ * @mrenclave:		SHA256-hash of the enclave contents
+ * @mrsigner:		SHA256-hash of the public key used to sign the SIGSTRUCT
+ * @isvprodid:		a user-defined value that is used in key derivation
+ * @isvsvn:		a user-defined value that is used in key derivation
+ *
+ * SGX Enclave Control Structure (SECS) is a special enclave page that is not
+ * visible in the address space. In fact, this structure defines the address
+ * range and other global attributes for the enclave and it is the first EPC
+ * page created for any enclave. It is moved from a temporary buffer to an EPC
+ * by the means of ENCLS(ECREATE) leaf.
+ */
+struct sgx_secs {
+	u64 size;
+	u64 base;
+	u32 ssa_frame_size;
+	u32 miscselect;
+	u8  reserved1[SGX_SECS_RESERVED1_SIZE];
+	u64 attributes;
+	u64 xfrm;
+	u32 mrenclave[8];
+	u8  reserved2[SGX_SECS_RESERVED2_SIZE];
+	u32 mrsigner[8];
+	u8  reserved3[SGX_SECS_RESERVED3_SIZE];
+	u16 isvprodid;
+	u16 isvsvn;
+	u8  reserved4[SGX_SECS_RESERVED4_SIZE];
+} __packed;
+
+/**
+ * enum sgx_tcs_flags - execution flags for TCS
+ * %SGX_TCS_DBGOPTIN:	If enabled allows single-stepping and breakpoints
+ *			inside an enclave. It is cleared by EADD but can
+ *			be set later with EDBGWR.
+ */
+enum sgx_tcs_flags {
+	SGX_TCS_DBGOPTIN	= 0x01,
+};
+
+#define SGX_TCS_RESERVED_MASK 0xFFFFFFFFFFFFFFFEULL
+#define SGX_TCS_RESERVED_SIZE 503
+
+/**
+ * struct sgx_tcs - Thread Control Structure (TCS)
+ * @state:		used to mark an entered TCS
+ * @flags:		execution flags (cleared by EADD)
+ * @ssa_offset:		SSA stack offset relative to the enclave base
+ * @ssa_index:		the current SSA frame index (cleard by EADD)
+ * @nr_ssa_frames:	the number of frame in the SSA stack
+ * @entry_offset:	entry point offset relative to the enclave base
+ * @exit_addr:		address outside the enclave to exit on an exception or
+ *			interrupt
+ * @fs_offset:		offset relative to the enclave base to become FS
+ *			segment inside the enclave
+ * @gs_offset:		offset relative to the enclave base to become GS
+ *			segment inside the enclave
+ * @fs_limit:		size to become a new FS-limit (only 32-bit enclaves)
+ * @gs_limit:		size to become a new GS-limit (only 32-bit enclaves)
+ *
+ * Thread Control Structure (TCS) is an enclave page visible in its address
+ * space that defines an entry point inside the enclave. A thread enters inside
+ * an enclave by supplying address of TCS to ENCLU(EENTER). A TCS can be entered
+ * by only one thread at a time.
+ */
+struct sgx_tcs {
+	u64 state;
+	u64 flags;
+	u64 ssa_offset;
+	u32 ssa_index;
+	u32 nr_ssa_frames;
+	u64 entry_offset;
+	u64 exit_addr;
+	u64 fs_offset;
+	u64 gs_offset;
+	u32 fs_limit;
+	u32 gs_limit;
+	u64 reserved[SGX_TCS_RESERVED_SIZE];
+} __packed;
+
+/**
+ * struct sgx_pageinfo - an enclave page descriptor
+ * @addr:	address of the enclave page
+ * @contents:	pointer to the page contents
+ * @metadata:	pointer either to a SECINFO or PCMD instance
+ * @secs:	address of the SECS page
+ */
+struct sgx_pageinfo {
+	u64 addr;
+	u64 contents;
+	u64 metadata;
+	u64 secs;
+} __packed __aligned(32);
+
+
+#define SGX_SECINFO_PERMISSION_MASK	0x0000000000000007ULL
+#define SGX_SECINFO_PAGE_TYPE_MASK	0x000000000000FF00ULL
+#define SGX_SECINFO_RESERVED_MASK	0xFFFFFFFFFFFF00F8ULL
+
+/**
+ * enum sgx_page_type - bits in the SECINFO flags defining the page type
+ * %SGX_PAGE_TYPE_SECS:	a SECS page
+ * %SGX_PAGE_TYPE_TCS:	a TCS page
+ * %SGX_PAGE_TYPE_REG:	a regular page
+ * %SGX_PAGE_TYPE_VA:	a VA page
+ * %SGX_PAGE_TYPE_TRIM:	a page in trimmed state
+ */
+enum sgx_page_type {
+	SGX_PAGE_TYPE_SECS	= 0x00,
+	SGX_PAGE_TYPE_TCS	= 0x01,
+	SGX_PAGE_TYPE_REG	= 0x02,
+	SGX_PAGE_TYPE_VA	= 0x03,
+	SGX_PAGE_TYPE_TRIM	= 0x04,
+};
+
+/**
+ * enum sgx_secinfo_flags - SECINFO flags
+ * %SGX_SECINFO_R:	read permission
+ * %SGX_SECINFO_W:	write permission
+ * %SGX_SECINFO_X:	exec permission
+ * %SGX_SECINFO_SECS:	a SECS page
+ * %SGX_SECINFO_TCS:	a TCS page
+ * %SGX_SECINFO_REG:	a regular page
+ * %SGX_SECINFO_VA:	a VA page
+ * %SGX_SECINFO_TRIM:	a page in trimmed state
+ */
+enum sgx_secinfo_flags {
+	SGX_SECINFO_R		= 0x01,
+	SGX_SECINFO_W		= 0x02,
+	SGX_SECINFO_X		= 0x04,
+	SGX_SECINFO_SECS	= (SGX_PAGE_TYPE_SECS << 8),
+	SGX_SECINFO_TCS		= (SGX_PAGE_TYPE_TCS << 8),
+	SGX_SECINFO_REG		= (SGX_PAGE_TYPE_REG << 8),
+	SGX_SECINFO_VA          = (SGX_PAGE_TYPE_VA << 8),
+	SGX_SECINFO_TRIM	= (SGX_PAGE_TYPE_TRIM << 8),
+};
+
+#define SGX_SECINFO_RESERVED_SIZE 56
+
+/**
+ * struct sgx_secinfo - describes the class of an enclave page
+ * @flags:	permissions and type
+ */
+struct sgx_secinfo {
+	u64 flags;
+	u8  reserved[SGX_SECINFO_RESERVED_SIZE];
+} __packed __aligned(64);
+
+#define SGX_PCMD_RESERVED_SIZE 40
+
+/**
+ * struct sgx_pcmd - Paging Crypto Metadata (PCMD)
+ * @enclave_id:	enclave identifier
+ * @mac:	MAC over PCMD, page contents and isvsvn
+ *
+ * PCMD is stored for every swapped page to the regular memory. When ELDU loads
+ * the page back it recalculates the MAC by using a isvsvn number stored in a
+ * VA page. Together these two structures bring integrity and rollback
+ * protection.
+ */
+struct sgx_pcmd {
+	struct sgx_secinfo secinfo;
+	u64 enclave_id;
+	u8  reserved[SGX_PCMD_RESERVED_SIZE];
+	u8  mac[16];
+} __packed __aligned(128);
+
+#define SGX_SIGSTRUCT_RESERVED1_SIZE 84
+#define SGX_SIGSTRUCT_RESERVED2_SIZE 20
+#define SGX_SIGSTRUCT_RESERVED3_SIZE 32
+#define SGX_SIGSTRUCT_RESERVED4_SIZE 12
+
+/**
+ * struct sgx_sigstruct - an enclave signature
+ * @header1:		a constant byte string
+ * @vendor:		must be either 0x0000 or 0x8086
+ * @date:		YYYYMMDD in BCD
+ * @header2:		a costant byte string
+ * @application:	an application defined value
+ * @modulus:		the modulus of the public key
+ * @exponent:		the exponent of the public key
+ * @signature:		the signature calculated over the fields except modulus,
+ *			exponent, signature, reserved4, q1 and q2
+ * @miscselect:		additional information stored to an SSA frame
+ * @misc_mask:		required miscselect in SECS
+ * @attributes:		attributes for enclave
+ * @xfrm:		XSave-Feature Request Mask (subset of XCR0)
+ * @attributes_mask:	required attributes in SECS
+ * @xfrm_mask:		required XFRM in SECS
+ * @mrenclave:		SHA256-hash of the enclave contents
+ * @isvprodid:		a user-defined value that is used in key derivation
+ * @isvsvn:		a user-defined value that is used in key derivation
+ * @q1:			a value used in RSA signature verification
+ * @q2:			a value used in RSA signature verification
+ */
+struct sgx_sigstruct {
+	u64 header1[2];
+	u32 vendor;
+	u32 date;
+	u64 header2[2];
+	u32 application;
+	u8  reserved1[SGX_SIGSTRUCT_RESERVED1_SIZE];
+	u8  modulus[SGX_MODULUS_SIZE];
+	u32 exponent;
+	u8  signature[SGX_MODULUS_SIZE];
+	u32 miscselect;
+	u32 misc_mask;
+	u8  reserved2[SGX_SIGSTRUCT_RESERVED2_SIZE];
+	u64 attributes;
+	u64 xfrm;
+	u64 attributes_mask;
+	u64 xfrm_mask;
+	u8  mrenclave[32];
+	u8  reserved3[SGX_SIGSTRUCT_RESERVED3_SIZE];
+	u16 isvprodid;
+	u16 isvsvn;
+	u8  reserved4[SGX_SIGSTRUCT_RESERVED4_SIZE];
+	u8  q1[SGX_MODULUS_SIZE];
+	u8  q2[SGX_MODULUS_SIZE];
+} __packed __aligned(4096);
+
+#define SGX_EINITTOKEN_RESERVED1_SIZE 11
+#define SGX_EINITTOKEN_RESERVED2_SIZE 32
+#define SGX_EINITTOKEN_RESERVED3_SIZE 32
+#define SGX_EINITTOKEN_RESERVED4_SIZE 24
+
+/**
+ * struct sgx_einittoken - a token permitting to launch an enclave
+ * @valid:			one if valid and zero if invalid
+ * @attributes:			attributes for enclave
+ * @xfrm:			XSave-Feature Request Mask (subset of XCR0)
+ * @mrenclave:			SHA256-hash of the enclave contents
+ * @mrsigner:			SHA256-hash of the public key used to sign the
+ *				SIGSTRUCT
+ * @le_cpusvn:			a value that reflects the SGX implementation
+ *				running in in the CPU
+ * @le_isvprodid:		a user-defined value that is used in key
+ *				derivation
+ * @le_isvsvn:			a user-defined value that is used in key
+ *				derivation
+ * @le_keyed_miscselect:	LE's miscselect masked with the token keys
+ *				miscselect
+ * @le_keyed_attributes:	LE's attributes masked with the token keys
+ *				attributes
+ * @le_keyed_xfrm:		LE's XFRM masked with the token keys xfrm
+ * @salt:			random salt for wear-out protection
+ * @mac:			CMAC over the preceding fields
+ *
+ * An enclave with EINITTOKENKEY attribute can access a key with the same name
+ * by using ENCLS(EGETKEY) and use this to sign cryptographic tokens that can
+ * be passed to ENCLS(EINIT) to permit the launch of other enclaves. This is
+ * the only viable way to launch enclaves if IA32_SGXLEPUBKEYHASHn MSRs are
+ * locked assuming that there is a Launch Enclave (LE) available that can be
+ * used for generating these tokens.
+ */
+struct sgx_einittoken {
+	u32 valid;
+	u32 reserved1[SGX_EINITTOKEN_RESERVED1_SIZE];
+	u64 attributes;
+	u64 xfrm;
+	u8  mrenclave[32];
+	u8  reserved2[SGX_EINITTOKEN_RESERVED2_SIZE];
+	u8  mrsigner[32];
+	u8  reserved3[SGX_EINITTOKEN_RESERVED3_SIZE];
+	u8  le_cpusvn[16];
+	u16 le_isvprodid;
+	u16 le_isvsvn;
+	u8  reserved4[SGX_EINITTOKEN_RESERVED4_SIZE];
+	u32 le_keyed_miscselect;
+	u64 le_keyed_attributes;
+	u64 le_keyed_xfrm;
+	u8  salt[32];
+	u8  mac[16];
+} __packed __aligned(512);
+
+#endif /* _ASM_X86_SGX_ARCH_H */
diff --git a/arch/x86/include/uapi/asm/sgx_errno.h b/arch/x86/include/uapi/asm/sgx_errno.h
new file mode 100644
index 000000000000..48b87aed58d7
--- /dev/null
+++ b/arch/x86/include/uapi/asm/sgx_errno.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * Copyright(c) 2018 Intel Corporation.
+ *
+ * Contains the architecturally defined error codes that are returned by SGX
+ * instructions, e.g. ENCLS, and may be propagated to userspace via errno.
+ */
+
+#ifndef _UAPI_ASM_X86_SGX_ERRNO_H
+#define _UAPI_ASM_X86_SGX_ERRNO_H
+
+/**
+ * enum sgx_encls_leaves - return codes for ENCLS, ENCLU and ENCLV
+ * %SGX_SUCCESS:		No error.
+ * %SGX_INVALID_SIG_STRUCT:	SIGSTRUCT contains an invalid value.
+ * %SGX_INVALID_ATTRIBUTE:	Enclave is not attempting to access a resource
+ *				for which it is not authorized.
+ * %SGX_BLKSTATE:		EPC page is already blocked.
+ * %SGX_INVALID_MEASUREMENT:	SIGSTRUCT or EINITTOKEN contains an incorrect
+ *				measurement.
+ * %SGX_NOTBLOCKABLE:		EPC page type is not one which can be blocked.
+ * %SGX_PG_INVLD:		EPC page is invalid (and cannot be blocked).
+ * %SGX_EPC_PAGE_CONFLICT:	EPC page in use by another SGX instruction.
+ * %SGX_INVALID_SIGNATURE:	Enclave's signature does not validate with
+ *				public key enclosed in SIGSTRUCT.
+ * %SGX_MAC_COMPARE_FAIL:	MAC check failed when reloading EPC page.
+ * %SGX_PAGE_NOT_BLOCKED:	EPC page is not marked as blocked.
+ * %SGX_NOT_TRACKED:		ETRACK has not been completed on the EPC page.
+ * %SGX_VA_SLOT_OCCUPIED:	Version array slot contains a valid entry.
+ * %SGX_CHILD_PRESENT:		Enclave has child pages present in the EPC.
+ * %SGX_ENCLAVE_ACT:		Logical processors are currently executing
+ *				inside the enclave.
+ * %SGX_ENTRYEPOCH_LOCKED:	SECS locked for EPOCH update, i.e. an ETRACK is
+ *				currently executing on the SECS.
+ * %SGX_INVALID_EINITTOKEN:	EINITTOKEN is invalid and enclave signer's
+ *				public key does not match IA32_SGXLEPUBKEYHASH.
+ * %SGX_PREV_TRK_INCMPL:	All processors did not complete the previous
+ *				tracking sequence.
+ * %SGX_PG_IS_SECS:		Target EPC page is an SECS and cannot be
+ *				blocked.
+ * %SGX_PAGE_ATTRIBUTES_MISMATCH:	Attributes of the EPC page do not match
+ *					the expected values.
+ * %SGX_PAGE_NOT_MODIFIABLE:	EPC page cannot be modified because it is in
+ *				the PENDING or MODIFIED state.
+ * %SGX_PAGE_NOT_DEBUGGABLE:	EPC page cannot be modified because it is in
+ *				the PENDING or MODIFIED state.
+ * %SGX_INVALID_COUNTER:	{In,De}crementing a counter would cause it to
+ *				{over,under}flow.
+ * %SGX_PG_NONEPC:		Target page is not an EPC page.
+ * %SGX_TRACK_NOT_REQUIRED:	Target page type does not require tracking.
+ * %SGX_INVALID_CPUSVN:		Security version number reported by CPU is less
+ *				than what is required by the enclave.
+ * %SGX_INVALID_ISVSVN:		Security version number of enclave is less than
+ *				what is required by the KEYREQUEST struct.
+ * %SGX_UNMASKED_EVENT:		An unmasked event, e.g. INTR, was received
+ *				while the instruction was executing.
+ * %SGX_INVALID_KEYNAME:	Requested key is not supported by hardware.
+ */
+enum sgx_return_codes {
+	SGX_SUCCESS			= 0,
+	SGX_INVALID_SIG_STRUCT		= 1,
+	SGX_INVALID_ATTRIBUTE		= 2,
+	SGX_BLKSTATE			= 3,
+	SGX_INVALID_MEASUREMENT		= 4,
+	SGX_NOTBLOCKABLE		= 5,
+	SGX_PG_INVLD			= 6,
+	SGX_EPC_PAGE_CONFLICT		= 7,
+	SGX_INVALID_SIGNATURE		= 8,
+	SGX_MAC_COMPARE_FAIL		= 9,
+	SGX_PAGE_NOT_BLOCKED		= 10,
+	SGX_NOT_TRACKED			= 11,
+	SGX_VA_SLOT_OCCUPIED		= 12,
+	SGX_CHILD_PRESENT		= 13,
+	SGX_ENCLAVE_ACT			= 14,
+	SGX_ENTRYEPOCH_LOCKED		= 15,
+	SGX_INVALID_EINITTOKEN		= 16,
+	SGX_PREV_TRK_INCMPL		= 17,
+	SGX_PG_IS_SECS			= 18,
+	SGX_PAGE_ATTRIBUTES_MISMATCH	= 19,
+	SGX_PAGE_NOT_MODIFIABLE		= 20,
+	SGX_PAGE_NOT_DEBUGGABLE		= 21,
+	SGX_INVALID_COUNTER		= 25,
+	SGX_PG_NONEPC			= 26,
+	SGX_TRACK_NOT_REQUIRED		= 27,
+	SGX_INVALID_CPUSVN		= 32,
+	SGX_INVALID_ISVSVN		= 64,
+	SGX_UNMASKED_EVENT		= 128,
+	SGX_INVALID_KEYNAME		= 256,
+};
+
+#endif /* _UAPI_ASM_X86_SGX_ERRNO_H */
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 05/13] x86/msr: Add SGX definitions to msr-index.h
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (3 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 04/13] x86/sgx: Architectural structures Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-27 19:42   ` Dave Hansen
  2018-08-27 18:53 ` [PATCH v13 06/13] x86/sgx: Detect Intel SGX Jarkko Sakkinen
                   ` (7 subsequent siblings)
  12 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Haim Cohen, Jarkko Sakkinen, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Borislav Petkov,
	Konrad Rzeszutek Wilk, Tom Lendacky, Paolo Bonzini,
	David Woodhouse, Greg Kroah-Hartman, Janakarajan Natarajan,
	Matt Turner, Andy Lutomirski,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

From: Sean Christopherson <sean.j.christopherson@intel.com>

ENCLS and ENCLU are usable if and only if SGX_ENABLE is set and After
SGX is activated the IA32_SGXLEPUBKEYHASHn MSRs are writable if
SGX_LC_WR is set and the feature control is locked.

SGX related bits in IA32_FEATURE_CONTROL cannot be set before SGX is
activated by the pre-boot firmware. SGX activation is triggered by
setting bit 0 in the MSR 0x7a. Until SGX is activated, the LE hash MSRs
are writable to allow pre-boot firmware to lock down the LE root key
with a non-Intel value.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Co-developed-by: Haim Cohen <haim.cohen@intel.com>
Signed-off-by: Haim Cohen <haim.cohen@intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 arch/x86/include/asm/msr-index.h | 8 ++++++++
 arch/x86/kernel/cpu/common.c     | 8 ++++----
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4731f0cf97c5..44d7b68e7f52 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -486,6 +486,8 @@
 #define FEATURE_CONTROL_LOCKED				(1<<0)
 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)
+#define FEATURE_CONTROL_SGX_ENABLE			(1<<18)
+#define FEATURE_CONTROL_SGX_LE_WR			(1<<17)
 #define FEATURE_CONTROL_LMCE				(1<<20)
 
 #define MSR_IA32_APICBASE		0x0000001b
@@ -552,6 +554,12 @@
 #define PACKAGE_THERM_INT_LOW_ENABLE		(1 << 1)
 #define PACKAGE_THERM_INT_PLN_ENABLE		(1 << 24)
 
+/* Intel SGX MSRs */
+#define MSR_IA32_SGXLEPUBKEYHASH0	0x0000008C
+#define MSR_IA32_SGXLEPUBKEYHASH1	0x0000008D
+#define MSR_IA32_SGXLEPUBKEYHASH2	0x0000008E
+#define MSR_IA32_SGXLEPUBKEYHASH3	0x0000008F
+
 /* Thermal Thresholds Support */
 #define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
 #define THERM_SHIFT_THRESHOLD0        8
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 211c76322ddf..282ceef992b0 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -52,6 +52,7 @@
 #include <asm/microcode_intel.h>
 #include <asm/intel-family.h>
 #include <asm/cpu_device_id.h>
+#include <asm/sgx_arch.h>
 
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/uv/uv.h>
@@ -866,10 +867,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
 		}
 	}
 
-	/* Intel SGX features: level 0x00000012 */
-	if (c->cpuid_level >= 0x00000012) {
-		cpuid(0x00000012, &eax, &ebx, &ecx, &edx);
-
+	/* Intel SGX features */
+	if (c->cpuid_level >= SGX_CPUID) {
+		cpuid(SGX_CPUID,  &eax, &ebx, &ecx, &edx);
 		c->x86_capability[CPUID_12_EAX] = eax;
 	}
 
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 06/13] x86/sgx: Detect Intel SGX
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (4 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 05/13] x86/msr: Add SGX definitions to msr-index.h Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-27 19:53   ` Dave Hansen
  2018-09-03 14:26   ` Andy Shevchenko
  2018-08-27 18:53 ` [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages Jarkko Sakkinen
                   ` (6 subsequent siblings)
  12 siblings, 2 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Suresh Siddha, Jarkko Sakkinen, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Serge Ayoun, Rafael J. Wysocki,
	Borislav Petkov, Reinette Chatre, Andi Kleen, Greg Kroah-Hartman,
	Kirill A. Shutemov,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

From: Sean Christopherson <sean.j.christopherson@intel.com>

Intel(R) SGX is a set of CPU instructions that can be used by applications
to set aside private regions of code and data. The code outside the enclave
is disallowed to access the memory inside the enclave by the CPU access
control.

Add a check for SGX to arch/x86 and a new config option, INTEL_SGX_CORE.
Expose a boolean variable 'sgx_enabled' to query whether or not the SGX
support is available.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Co-developed-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 arch/x86/Kconfig                | 19 +++++++++++++
 arch/x86/include/asm/sgx.h      | 12 +++++++++
 arch/x86/include/asm/sgx_pr.h   | 13 +++++++++
 arch/x86/kernel/cpu/Makefile    |  1 +
 arch/x86/kernel/cpu/intel_sgx.c | 47 +++++++++++++++++++++++++++++++++
 5 files changed, 92 insertions(+)
 create mode 100644 arch/x86/include/asm/sgx.h
 create mode 100644 arch/x86/include/asm/sgx_pr.h
 create mode 100644 arch/x86/kernel/cpu/intel_sgx.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index b0312f8947ce..3c7571422a07 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1911,6 +1911,25 @@ config X86_INTEL_MEMORY_PROTECTION_KEYS
 
 	  If unsure, say y.
 
+config INTEL_SGX_CORE
+	prompt "Intel SGX core functionality"
+	def_bool n
+	depends on X86_64 && CPU_SUP_INTEL
+	help
+	Intel Software Guard eXtensions (SGX) is a set of CPU instructions
+	that allows ring 3 applications to create enclaves, private regions
+	of memory that are protected, by hardware, from unauthorized access
+	and/or modification.
+
+	This option enables kernel recognition of SGX, high-level management
+	of the Enclave Page Cache (EPC), tracking and writing of SGX Launch
+	Enclave Hash MSRs, and allows for virtualization of SGX via KVM. By
+	iteslf, this option does not provide SGX support to userspace.
+
+	For details, see Documentation/x86/intel_sgx.rst
+
+	If unsure, say N.
+
 config EFI
 	bool "EFI runtime service support"
 	depends on ACPI
diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
new file mode 100644
index 000000000000..2130e639ab49
--- /dev/null
+++ b/arch/x86/include/asm/sgx.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-18 Intel Corporation.
+
+#ifndef _ASM_X86_SGX_H
+#define _ASM_X86_SGX_H
+
+#include <linux/types.h>
+
+extern bool sgx_enabled;
+extern bool sgx_lc_enabled;
+
+#endif /* _ASM_X86_SGX_H */
diff --git a/arch/x86/include/asm/sgx_pr.h b/arch/x86/include/asm/sgx_pr.h
new file mode 100644
index 000000000000..c68578127620
--- /dev/null
+++ b/arch/x86/include/asm/sgx_pr.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-17 Intel Corporation.
+
+#ifndef _ASM_X86_SGX_PR_H
+#define _ASM_X86_SGX_PR_H
+
+#include <linux/printk.h>
+#include <linux/ratelimit.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "sgx: " fmt
+
+#endif /* _ASM_X86_SGX_PR_H */
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 347137e80bf5..71876f2b35fc 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CPU_SUP_UMC_32)		+= umc.o
 obj-$(CONFIG_INTEL_RDT)	+= intel_rdt.o intel_rdt_rdtgroup.o intel_rdt_monitor.o
 obj-$(CONFIG_INTEL_RDT)	+= intel_rdt_ctrlmondata.o intel_rdt_pseudo_lock.o
 CFLAGS_intel_rdt_pseudo_lock.o = -I$(src)
+obj-$(CONFIG_INTEL_SGX_CORE)		+= intel_sgx.o
 
 obj-$(CONFIG_X86_MCE)			+= mcheck/
 obj-$(CONFIG_MTRR)			+= mtrr/
diff --git a/arch/x86/kernel/cpu/intel_sgx.c b/arch/x86/kernel/cpu/intel_sgx.c
new file mode 100644
index 000000000000..17b46bec9c54
--- /dev/null
+++ b/arch/x86/kernel/cpu/intel_sgx.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-17 Intel Corporation.
+
+#include <asm/sgx.h>
+#include <asm/sgx_pr.h>
+#include <linux/freezer.h>
+#include <linux/highmem.h>
+#include <linux/kthread.h>
+#include <linux/ratelimit.h>
+#include <linux/sched/signal.h>
+#include <linux/slab.h>
+
+bool sgx_enabled __ro_after_init;
+EXPORT_SYMBOL_GPL(sgx_enabled);
+bool sgx_lc_enabled __ro_after_init;
+EXPORT_SYMBOL_GPL(sgx_lc_enabled);
+
+static __init int sgx_init(void)
+{
+	unsigned long fc;
+
+	if (!boot_cpu_has(X86_FEATURE_SGX))
+		return false;
+
+	if (!boot_cpu_has(X86_FEATURE_SGX1))
+		return false;
+
+	rdmsrl(MSR_IA32_FEATURE_CONTROL, fc);
+	if (!(fc & FEATURE_CONTROL_LOCKED)) {
+		pr_info("IA32_FEATURE_CONTROL MSR is not locked\n");
+		return false;
+	}
+
+	if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) {
+		pr_info("disabled by the firmware\n");
+		return false;
+	}
+
+	if (!(fc & FEATURE_CONTROL_SGX_LE_WR))
+		pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not writable\n");
+
+	sgx_enabled = true;
+	sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR);
+	return 0;
+}
+
+arch_initcall(sgx_init);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (5 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 06/13] x86/sgx: Detect Intel SGX Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-27 21:07   ` Dave Hansen
  2018-09-03 14:41   ` Andy Shevchenko
  2018-08-27 18:53 ` [PATCH v13 08/13] x86/sgx: Add wrappers for ENCLS leaf functions Jarkko Sakkinen
                   ` (5 subsequent siblings)
  12 siblings, 2 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Serge Ayoun, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Suresh Siddha,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

Add data structures to track Enclave Page Cache (EPC) pages.  EPC is
divided into multiple banks (1-N) of which addresses and sizes can be
enumerated with CPUID by the OS.

On NUMA systems a node can have at most bank. A bank can be at most part of
two nodes. SGX supports both nodes with a single memory controller and also
sub-cluster nodes with severals memory controllers on a single die.

Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Co-developed-by: Serge Ayoun <serge.ayoun@intel.com>
Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Serge Ayoun <serge.ayoun@intel.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
 arch/x86/include/asm/sgx.h      |  60 ++++++++++++++++++
 arch/x86/kernel/cpu/intel_sgx.c | 106 +++++++++++++++++++++++++++++++-
 2 files changed, 164 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
index 2130e639ab49..17b7b3aa66bf 100644
--- a/arch/x86/include/asm/sgx.h
+++ b/arch/x86/include/asm/sgx.h
@@ -4,9 +4,69 @@
 #ifndef _ASM_X86_SGX_H
 #define _ASM_X86_SGX_H
 
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/rwsem.h>
 #include <linux/types.h>
+#include <asm/sgx_arch.h>
+#include <asm/asm.h>
+
+#define SGX_MAX_EPC_BANKS 8
+
+struct sgx_epc_page {
+	unsigned long desc;
+	struct list_head list;
+};
+
+struct sgx_epc_bank {
+	unsigned long pa;
+	void *va;
+	unsigned long size;
+	struct sgx_epc_page *pages_data;
+	struct sgx_epc_page **pages;
+	unsigned long free_cnt;
+	spinlock_t lock;
+};
 
 extern bool sgx_enabled;
 extern bool sgx_lc_enabled;
+extern struct sgx_epc_bank sgx_epc_banks[SGX_MAX_EPC_BANKS];
+
+/*
+ * enum sgx_epc_page_desc - defines bits and masks for an EPC page's desc
+ * @SGX_EPC_BANK_MASK:	      SGX allows a system to multiple EPC banks (at
+ *			      different physical locations).  The index of a
+ *			      page's bank in its desc so that we can do a quick
+ *			      lookup of its virtual address (EPC is mapped via
+ *			      ioremap_cache() because it's non-standard memory).
+ *			      Current and near-future hardware defines at most
+ *			      eight banks, hence three bits to hold the bank.
+ *			      sgx_page_cache_init() asserts that the max bank
+ *			      index doesn't exceed SGX_EPC_BANK_MASK.
+ * @SGX_EPC_PAGE_RECLAIMABLE: When set, indicates a page is reclaimable.  Used
+ *			      when freeing a page to know that we also need to
+ *			      remove the page from the active page list.
+ *
+ * Defines the layout of the desc field in the &struct sgx_epc_page, which
+ * contains EPC bank number, physical address of the page and the page status
+ * flag.
+ */
+enum sgx_epc_page_desc {
+	SGX_EPC_BANK_MASK			= GENMASK_ULL(3, 0),
+	SGX_EPC_PAGE_RECLAIMABLE		= BIT(4),
+	/* bits 12-63 are reserved for the physical page address of the page */
+};
+
+static inline struct sgx_epc_bank *sgx_epc_bank(struct sgx_epc_page *page)
+{
+	return &sgx_epc_banks[page->desc & SGX_EPC_BANK_MASK];
+}
+
+static inline void *sgx_epc_addr(struct sgx_epc_page *page)
+{
+	struct sgx_epc_bank *bank = sgx_epc_bank(page);
+
+	return (void *)(bank->va + (page->desc & PAGE_MASK) - bank->pa);
+}
 
 #endif /* _ASM_X86_SGX_H */
diff --git a/arch/x86/kernel/cpu/intel_sgx.c b/arch/x86/kernel/cpu/intel_sgx.c
index 17b46bec9c54..53ac172e8006 100644
--- a/arch/x86/kernel/cpu/intel_sgx.c
+++ b/arch/x86/kernel/cpu/intel_sgx.c
@@ -1,23 +1,121 @@
 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
 // Copyright(c) 2016-17 Intel Corporation.
 
-#include <asm/sgx.h>
-#include <asm/sgx_pr.h>
 #include <linux/freezer.h>
 #include <linux/highmem.h>
 #include <linux/kthread.h>
+#include <linux/pagemap.h>
 #include <linux/ratelimit.h>
 #include <linux/sched/signal.h>
+#include <linux/shmem_fs.h>
 #include <linux/slab.h>
+#include <asm/sgx.h>
+#include <asm/sgx_pr.h>
 
 bool sgx_enabled __ro_after_init;
 EXPORT_SYMBOL_GPL(sgx_enabled);
 bool sgx_lc_enabled __ro_after_init;
 EXPORT_SYMBOL_GPL(sgx_lc_enabled);
+struct sgx_epc_bank sgx_epc_banks[SGX_MAX_EPC_BANKS];
+EXPORT_SYMBOL_GPL(sgx_epc_banks);
+
+static int sgx_nr_epc_banks;
+
+static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned long index,
+				    struct sgx_epc_bank *bank)
+{
+	unsigned long nr_pages = size >> PAGE_SHIFT;
+	struct sgx_epc_page *pages_data;
+	unsigned long i;
+	void *va;
+
+	va = ioremap_cache(addr, size);
+	if (!va)
+		return -ENOMEM;
+
+	pages_data = kcalloc(nr_pages, sizeof(struct sgx_epc_page), GFP_KERNEL);
+	if (!pages_data)
+		goto out_iomap;
+
+	bank->pages = kcalloc(nr_pages, sizeof(struct sgx_epc_page *),
+			      GFP_KERNEL);
+	if (!bank->pages)
+		goto out_pdata;
+
+	for (i = 0; i < nr_pages; i++) {
+		bank->pages[i] = &pages_data[i];
+		bank->pages[i]->desc = (addr + (i << PAGE_SHIFT)) | index;
+	}
+
+	bank->pa = addr;
+	bank->size = size;
+	bank->va = va;
+	bank->free_cnt = nr_pages;
+	bank->pages_data = pages_data;
+	spin_lock_init(&bank->lock);
+	return 0;
+out_pdata:
+	kfree(pages_data);
+out_iomap:
+	iounmap(va);
+	return -ENOMEM;
+}
+
+static __init void sgx_page_cache_teardown(void)
+{
+	struct sgx_epc_bank *bank;
+	int i;
+
+	for (i = 0; i < sgx_nr_epc_banks; i++) {
+		bank = &sgx_epc_banks[i];
+		iounmap((void *)bank->va);
+		kfree(bank->pages);
+		kfree(bank->pages_data);
+	}
+}
+
+static inline u64 sgx_combine_bank_regs(u64 low, u64 high)
+{
+	return (low & 0xFFFFF000) + ((high & 0xFFFFF) << 32);
+}
+
+static __init int sgx_page_cache_init(void)
+{
+	u32 eax, ebx, ecx, edx;
+	u64 pa, size;
+	int ret;
+	int i;
+
+	for (i = 0; i < SGX_MAX_EPC_BANKS; i++) {
+		cpuid_count(SGX_CPUID, 2 + i, &eax, &ebx, &ecx, &edx);
+		if (!(eax & 0xF))
+			break;
+
+		pa = sgx_combine_bank_regs(eax, ebx);
+		size = sgx_combine_bank_regs(ecx, edx);
+		pr_info("EPC bank 0x%llx-0x%llx\n", pa, pa + size - 1);
+
+		ret = sgx_init_epc_bank(pa, size, i, &sgx_epc_banks[i]);
+		if (ret) {
+			sgx_page_cache_teardown();
+			return ret;
+		}
+
+		sgx_nr_epc_banks++;
+	}
+
+	if (!sgx_nr_epc_banks) {
+		pr_err("There are zero EPC banks.\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
 
 static __init int sgx_init(void)
 {
 	unsigned long fc;
+	int ret;
 
 	if (!boot_cpu_has(X86_FEATURE_SGX))
 		return false;
@@ -39,6 +137,10 @@ static __init int sgx_init(void)
 	if (!(fc & FEATURE_CONTROL_SGX_LE_WR))
 		pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not writable\n");
 
+	ret = sgx_page_cache_init();
+	if (ret)
+		return ret;
+
 	sgx_enabled = true;
 	sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR);
 	return 0;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 08/13] x86/sgx: Add wrappers for ENCLS leaf functions
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (6 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-09-03 15:01   ` Andy Shevchenko
  2018-08-27 18:53 ` [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager Jarkko Sakkinen
                   ` (4 subsequent siblings)
  12 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Serge Ayoun, Suresh Siddha,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

Add wrappers for Intel(R) SGX ENCLS opcode leaf functions except
ENCLS(EINIT). ENCLS invokes privileged functions for managing (creation,
initialization and swapping) and debugging enclaves.

Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
 arch/x86/include/asm/sgx.h | 261 +++++++++++++++++++++++++++++++++++++
 1 file changed, 261 insertions(+)

diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
index 17b7b3aa66bf..f8e419378f30 100644
--- a/arch/x86/include/asm/sgx.h
+++ b/arch/x86/include/asm/sgx.h
@@ -69,4 +69,265 @@ static inline void *sgx_epc_addr(struct sgx_epc_page *page)
 	return (void *)(bank->va + (page->desc & PAGE_MASK) - bank->pa);
 }
 
+/**
+ * ENCLS_FAULT_FLAG - flag signifying an ENCLS return code is a trapnr
+ *
+ * ENCLS has its own (positive value) error codes and also generates
+ * ENCLS specific #GP and #PF faults.  And the ENCLS values get munged
+ * with system error codes as everything percolates back up the stack.
+ * Unfortunately (for us), we need to precisely identify each unique
+ * error code, e.g. the action taken if EWB fails varies based on the
+ * type of fault and on the exact SGX error code, i.e. we can't simply
+ * convert all faults to -EFAULT.
+ *
+ * To make all three error types coexist, we set bit 30 to identify an
+ * ENCLS fault.  Bit 31 (technically bits N:31) is used to differentiate
+ * between positive (faults and SGX error codes) and negative (system
+ * error codes) values.
+ */
+#define ENCLS_FAULT_FLAG 0x40000000UL
+#define ENCLS_FAULT_FLAG_ASM "$0x40000000"
+
+/**
+ * IS_ENCLS_FAULT - check if a return code indicates an ENCLS fault
+ *
+ * Check for a fault by looking for a postive value with the fault
+ * flag set.  The postive value check is needed to filter out system
+ * error codes since negative values will have all higher order bits
+ * set, including ENCLS_FAULT_FLAG.
+ */
+#define IS_ENCLS_FAULT(r) ((int)(r) > 0 && ((r) & ENCLS_FAULT_FLAG))
+
+/**
+ * ENCLS_TRAPNR - retrieve the trapnr exactly as passed via _ASM_EXTABLE_FAULT
+ *
+ * Retrieve the encoded trapnr from the specified return code, keeping
+ * any error code bits that were included in trapnr when it was supplied
+ * to the _ASM_EXTABLE_FAULT handler.
+ */
+#define ENCLS_TRAPNR(r) ((r) & ~ENCLS_FAULT_FLAG)
+
+/**
+ * ENCLS_FAULT_VECTOR - retrieve the fault vector from a return code
+ *
+ * Retrieve the encoded fault vector, e.g. #GP or #PF, from the specified
+ * return code, dropping any potential error code bits in trapnr.
+ */
+#define ENCLS_FAULT_VECTOR(r) (ENCLS_TRAPNR(r) & 0x1f)
+
+/**
+ * encls_to_err - translate an ENCLS fault or SGX code into a system error code
+ * @ret:	positive value return code
+ *
+ * Returns:
+ *	-EFAULT for faults
+ *	-EINTR for unmasked events
+ *	-EINVAL for SGX_INVALID_* error codes
+ *	-EBUSY for non-fatal resource contention errors
+ *	-EIO for all other errors
+ *
+ * Translate a postive return code, e.g. from ENCLS, into a system error
+ * code.  Primarily used by functions that cannot return a non-negative
+ * error code, e.g. kernel callbacks.
+ */
+static inline int encls_to_err(int ret)
+{
+	if (IS_ENCLS_FAULT(ret))
+		return -EFAULT;
+
+	switch (ret) {
+	case SGX_UNMASKED_EVENT:
+		return -EINTR;
+	case SGX_INVALID_SIG_STRUCT:
+	case SGX_INVALID_ATTRIBUTE:
+	case SGX_INVALID_MEASUREMENT:
+	case SGX_INVALID_EINITTOKEN:
+	case SGX_INVALID_CPUSVN:
+	case SGX_INVALID_ISVSVN:
+	case SGX_INVALID_KEYNAME:
+		return -EINVAL;
+	case SGX_ENCLAVE_ACT:
+	case SGX_CHILD_PRESENT:
+	case SGX_ENTRYEPOCH_LOCKED:
+	case SGX_PREV_TRK_INCMPL:
+	case SGX_PAGE_NOT_MODIFIABLE:
+	case SGX_PAGE_NOT_DEBUGGABLE:
+		return -EBUSY;
+	default:
+		return -EIO;
+	};
+}
+
+/**
+ * __encls_ret_N - encode an ENCLS leaf that returns an error code in EAX
+ * @rax:	leaf number
+ * @inputs:	asm inputs for the leaf
+ *
+ * Returns:
+ *	0 on success
+ *	SGX error code on failure
+ *	trapnr with ENCLS_FAULT_FLAG set on fault
+ *
+ * Emit assembly for an ENCLS leaf that returns an error code, e.g. EREMOVE.
+ * And because SGX isn't complex enough as it is, leafs that return an error
+ * code also modify flags.
+ */
+#define __encls_ret_N(rax, inputs...)			\
+	({						\
+	int ret;					\
+	asm volatile(					\
+	"1: .byte 0x0f, 0x01, 0xcf;\n\t"		\
+	"2:\n"						\
+	".section .fixup,\"ax\"\n"			\
+	"3: orl "ENCLS_FAULT_FLAG_ASM",%%eax\n"		\
+	"   jmp 2b\n"					\
+	".previous\n"					\
+	_ASM_EXTABLE_FAULT(1b, 3b)			\
+	: "=a"(ret)					\
+	: "a"(rax), inputs				\
+	: "memory", "cc");				\
+	ret;						\
+	})
+
+#define __encls_ret_1(rax, rcx)				\
+	({						\
+	__encls_ret_N(rax, "c"(rcx));			\
+	})
+
+#define __encls_ret_2(rax, rbx, rcx)			\
+	({						\
+	__encls_ret_N(rax, "b"(rbx), "c"(rcx));		\
+	})
+
+#define __encls_ret_3(rax, rbx, rcx, rdx)			\
+	({							\
+	__encls_ret_N(rax, "b"(rbx), "c"(rcx), "d"(rdx));	\
+	})
+
+/**
+ * __encls_N - encode an ENCLS leaf that doesn't return an error code
+ * @rax:	leaf number
+ * @rbx_out:	optional output variable
+ * @inputs:	asm inputs for the leaf
+ *
+ * Returns:
+ *	0 on success
+ *	trapnr with ENCLS_FAULT_FLAG set on fault
+ *
+ * Emit assembly for an ENCLS leaf that does not return an error code,
+ * e.g. ECREATE.  Leaves without error codes either succeed or fault.
+ * @rbx_out is an optional parameter for use by EDGBRD, which returns
+ * the the requested value in RBX.
+ */
+#define __encls_N(rax, rbx_out, inputs...)		\
+	({						\
+	int ret;					\
+	asm volatile(					\
+	"1: .byte 0x0f, 0x01, 0xcf;\n\t"		\
+	"   xor %%eax,%%eax;\n"				\
+	"2:\n"						\
+	".section .fixup,\"ax\"\n"			\
+	"3: orl "ENCLS_FAULT_FLAG_ASM",%%eax\n"		\
+	"   jmp 2b\n"					\
+	".previous\n"					\
+	_ASM_EXTABLE_FAULT(1b, 3b)			\
+	: "=a"(ret), "=b"(rbx_out)			\
+	: "a"(rax), inputs				\
+	: "memory");					\
+	ret;						\
+	})
+
+#define __encls_2(rax, rbx, rcx)				\
+	({							\
+	unsigned long ign_rbx_out;				\
+	__encls_N(rax, ign_rbx_out, "b"(rbx), "c"(rcx));	\
+	})
+
+#define __encls_1_1(rax, data, rcx)			\
+	({						\
+	unsigned long rbx_out;				\
+	int ret = __encls_N(rax, rbx_out, "c"(rcx));	\
+	if (!ret)					\
+		data = rbx_out;				\
+	ret;						\
+	})
+
+static inline int __ecreate(struct sgx_pageinfo *pginfo, void *secs)
+{
+	return __encls_2(ECREATE, pginfo, secs);
+}
+
+static inline int __eextend(void *secs, void *epc)
+{
+	return __encls_2(EEXTEND, secs, epc);
+}
+
+static inline int __eadd(struct sgx_pageinfo *pginfo, void *epc)
+{
+	return __encls_2(EADD, pginfo, epc);
+}
+
+static inline int __einit(void *sigstruct, struct sgx_einittoken *einittoken,
+			  void *secs)
+{
+	return __encls_ret_3(EINIT, sigstruct, secs, einittoken);
+}
+
+static inline int __eremove(void *epc)
+{
+	return __encls_ret_1(EREMOVE, epc);
+}
+
+static inline int __edbgwr(void *addr, unsigned long *data)
+{
+	return __encls_2(EDGBWR, *data, addr);
+}
+
+static inline int __edbgrd(void *addr, unsigned long *data)
+{
+	return __encls_1_1(EDGBRD, *data, addr);
+}
+
+static inline int __etrack(void *epc)
+{
+	return __encls_ret_1(ETRACK, epc);
+}
+
+static inline int __eldu(struct sgx_pageinfo *pginfo, void *epc, void *va)
+{
+	return __encls_ret_3(ELDU, pginfo, epc, va);
+}
+
+static inline int __eblock(void *epc)
+{
+	return __encls_ret_1(EBLOCK, epc);
+}
+
+static inline int __epa(void *epc)
+{
+	unsigned long rbx = SGX_PAGE_TYPE_VA;
+
+	return __encls_2(EPA, rbx, epc);
+}
+
+static inline int __ewb(struct sgx_pageinfo *pginfo, void *epc, void *va)
+{
+	return __encls_ret_3(EWB, pginfo, epc, va);
+}
+
+static inline int __eaug(struct sgx_pageinfo *pginfo, void *epc)
+{
+	return __encls_2(EAUG, pginfo, epc);
+}
+
+static inline int __emodpr(struct sgx_secinfo *secinfo, void *epc)
+{
+	return __encls_ret_2(EMODPR, secinfo, epc);
+}
+
+static inline int __emodt(struct sgx_secinfo *secinfo, void *epc)
+{
+	return __encls_ret_2(EMODT, secinfo, epc);
+}
+
 #endif /* _ASM_X86_SGX_H */
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (7 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 08/13] x86/sgx: Add wrappers for ENCLS leaf functions Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-27 21:14   ` Dave Hansen
                     ` (3 more replies)
  2018-08-27 18:53 ` [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves Jarkko Sakkinen
                   ` (3 subsequent siblings)
  12 siblings, 4 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

Add a Enclave Page Cache (EPC) memory manager that can be used to
allocate and free EPC pages. The swapper thread ksgxswapd reclaims pages
on the event when the number of free EPC pages goes below
%SGX_NR_LOW_PAGES up until it reaches %SGX_NR_HIGH_PAGES.

Pages are reclaimed in LRU fashion from a global list. The consumers
take care of calling EBLOCK (block page from new accesses), ETRACK
(restart counting the entering hardware threads) and EWB (write page to
the regular memory) because executing these operations usually (if not
always) requires to do some subsystem-internal locking operations.

Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
 arch/x86/include/asm/sgx.h      |  56 ++++--
 arch/x86/kernel/cpu/intel_sgx.c | 322 ++++++++++++++++++++++++++++++++
 2 files changed, 362 insertions(+), 16 deletions(-)

diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
index f8e419378f30..baf30d49b71f 100644
--- a/arch/x86/include/asm/sgx.h
+++ b/arch/x86/include/asm/sgx.h
@@ -13,8 +13,36 @@
 
 #define SGX_MAX_EPC_BANKS 8
 
+struct sgx_epc_page;
+
+/**
+ * struct sgx_epc_page_ops - operations to reclaim an EPC page
+ * @get:	Pin the page. Returns false when the consumer is freeing the
+ *		page itself.
+ * @put:	Unpin the page.
+ * @reclaim:	Try to reclaim the page. Returns false when the consumer is
+ *		actively using needs the page.
+ * @block:	Perform EBLOCK on the page.
+ * @write:	Perform ETRACK (when required) and EWB on the page.
+ *
+ * These operations must be implemented by the EPC consumer to assist to reclaim
+ * EPC pages.
+ */
+struct sgx_epc_page_ops {
+	bool (*get)(struct sgx_epc_page *epc_page);
+	void (*put)(struct sgx_epc_page *epc_page);
+	bool (*reclaim)(struct sgx_epc_page *epc_page);
+	void (*block)(struct sgx_epc_page *epc_page);
+	void (*write)(struct sgx_epc_page *epc_page);
+};
+
+struct sgx_epc_page_impl {
+	const struct sgx_epc_page_ops *ops;
+};
+
 struct sgx_epc_page {
 	unsigned long desc;
+	struct sgx_epc_page_impl *impl;
 	struct list_head list;
 };
 
@@ -32,6 +60,10 @@ extern bool sgx_enabled;
 extern bool sgx_lc_enabled;
 extern struct sgx_epc_bank sgx_epc_banks[SGX_MAX_EPC_BANKS];
 
+enum sgx_alloc_flags {
+	SGX_ALLOC_ATOMIC	= BIT(0),
+};
+
 /*
  * enum sgx_epc_page_desc - defines bits and masks for an EPC page's desc
  * @SGX_EPC_BANK_MASK:	      SGX allows a system to multiple EPC banks (at
@@ -69,22 +101,14 @@ static inline void *sgx_epc_addr(struct sgx_epc_page *page)
 	return (void *)(bank->va + (page->desc & PAGE_MASK) - bank->pa);
 }
 
-/**
- * ENCLS_FAULT_FLAG - flag signifying an ENCLS return code is a trapnr
- *
- * ENCLS has its own (positive value) error codes and also generates
- * ENCLS specific #GP and #PF faults.  And the ENCLS values get munged
- * with system error codes as everything percolates back up the stack.
- * Unfortunately (for us), we need to precisely identify each unique
- * error code, e.g. the action taken if EWB fails varies based on the
- * type of fault and on the exact SGX error code, i.e. we can't simply
- * convert all faults to -EFAULT.
- *
- * To make all three error types coexist, we set bit 30 to identify an
- * ENCLS fault.  Bit 31 (technically bits N:31) is used to differentiate
- * between positive (faults and SGX error codes) and negative (system
- * error codes) values.
- */
+struct sgx_epc_page *sgx_alloc_page(struct sgx_epc_page_impl *impl,
+				    unsigned int flags);
+int __sgx_free_page(struct sgx_epc_page *page);
+void sgx_free_page(struct sgx_epc_page *page);
+void sgx_page_reclaimable(struct sgx_epc_page *page);
+struct page *sgx_get_backing(struct file *file, pgoff_t index);
+void sgx_put_backing(struct page *backing_page, bool write);
+
 #define ENCLS_FAULT_FLAG 0x40000000UL
 #define ENCLS_FAULT_FLAG_ASM "$0x40000000"
 
diff --git a/arch/x86/kernel/cpu/intel_sgx.c b/arch/x86/kernel/cpu/intel_sgx.c
index 53ac172e8006..1046478a3ab9 100644
--- a/arch/x86/kernel/cpu/intel_sgx.c
+++ b/arch/x86/kernel/cpu/intel_sgx.c
@@ -12,6 +12,20 @@
 #include <asm/sgx.h>
 #include <asm/sgx_pr.h>
 
+/**
+ * enum sgx_swap_constants - the constants used by the swapping code
+ * %SGX_NR_TO_SCAN:	the number of pages to scan in a single round
+ * %SGX_NR_LOW_PAGES:	the low watermark for ksgxswapd when it starts to swap
+ *			pages.
+ * %SGX_NR_HIGH_PAGES:	the high watermark for ksgxswapd what it stops swapping
+ *			pages.
+ */
+enum sgx_swap_constants {
+	SGX_NR_TO_SCAN		= 16,
+	SGX_NR_LOW_PAGES	= 32,
+	SGX_NR_HIGH_PAGES	= 64,
+};
+
 bool sgx_enabled __ro_after_init;
 EXPORT_SYMBOL_GPL(sgx_enabled);
 bool sgx_lc_enabled __ro_after_init;
@@ -20,6 +34,299 @@ struct sgx_epc_bank sgx_epc_banks[SGX_MAX_EPC_BANKS];
 EXPORT_SYMBOL_GPL(sgx_epc_banks);
 
 static int sgx_nr_epc_banks;
+static LIST_HEAD(sgx_active_page_list);
+static DEFINE_SPINLOCK(sgx_active_page_list_lock);
+static struct task_struct *ksgxswapd_tsk;
+static DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
+
+/**
+ * sgx_reclaim_pages - reclaim EPC pages from the consumers
+ *
+ * Takes a fixed chunk of pages from the global list of consumed EPC pages and
+ * tries to swap them. Only the pages that are either being freed by the
+ * consumer or actively used are skipped.
+ */
+static void sgx_reclaim_pages(void)
+{
+	struct sgx_epc_page *chunk[SGX_NR_TO_SCAN + 1];
+	struct sgx_epc_page *epc_page;
+	struct sgx_epc_bank *bank;
+	int i, j;
+
+	spin_lock(&sgx_active_page_list_lock);
+	for (i = 0, j = 0; i < SGX_NR_TO_SCAN; i++) {
+		if (list_empty(&sgx_active_page_list))
+			break;
+
+		epc_page = list_first_entry(&sgx_active_page_list,
+					    struct sgx_epc_page, list);
+		list_del_init(&epc_page->list);
+
+		if (epc_page->impl->ops->get(epc_page))
+			chunk[j++] = epc_page;
+		else
+			epc_page->desc &= ~SGX_EPC_PAGE_RECLAIMABLE;
+	}
+	spin_unlock(&sgx_active_page_list_lock);
+
+	for (i = 0; i < j; i++) {
+		epc_page = chunk[i];
+		if (epc_page->impl->ops->reclaim(epc_page))
+			continue;
+
+		spin_lock(&sgx_active_page_list_lock);
+		list_add_tail(&epc_page->list, &sgx_active_page_list);
+		spin_unlock(&sgx_active_page_list_lock);
+
+		epc_page->impl->ops->put(epc_page);
+		chunk[i] = NULL;
+	}
+
+	for (i = 0; i < j; i++) {
+		epc_page = chunk[i];
+		if (epc_page)
+			epc_page->impl->ops->block(epc_page);
+	}
+
+	for (i = 0; i < j; i++) {
+		epc_page = chunk[i];
+		if (epc_page) {
+			epc_page->impl->ops->write(epc_page);
+			epc_page->impl->ops->put(epc_page);
+
+			/*
+			 * Put the page back on the free list only after we
+			 * have put() our reference to the owner of the EPC
+			 * page, otherwise the page could be re-allocated and
+			 * we'd call put() on the wrong impl.
+			 */
+			epc_page->desc &= ~SGX_EPC_PAGE_RECLAIMABLE;
+
+			bank = sgx_epc_bank(epc_page);
+			spin_lock(&bank->lock);
+			bank->pages[bank->free_cnt++] = epc_page;
+			spin_unlock(&bank->lock);
+		}
+	}
+}
+
+static unsigned long sgx_calc_free_cnt(void)
+{
+	struct sgx_epc_bank *bank;
+	unsigned long free_cnt = 0;
+	int i;
+
+	for (i = 0; i < sgx_nr_epc_banks; i++) {
+		bank = &sgx_epc_banks[i];
+		free_cnt += bank->free_cnt;
+	}
+
+	return free_cnt;
+}
+
+static inline bool sgx_should_reclaim(void)
+{
+	return sgx_calc_free_cnt() < SGX_NR_HIGH_PAGES &&
+	       !list_empty(&sgx_active_page_list);
+}
+
+static int ksgxswapd(void *p)
+{
+	set_freezable();
+
+	while (!kthread_should_stop()) {
+		if (try_to_freeze())
+			continue;
+
+		wait_event_freezable(ksgxswapd_waitq, kthread_should_stop() ||
+						      sgx_should_reclaim());
+
+		if (sgx_should_reclaim())
+			sgx_reclaim_pages();
+
+		cond_resched();
+	}
+
+	return 0;
+}
+
+static struct sgx_epc_page *sgx_try_alloc_page(struct sgx_epc_page_impl *impl)
+{
+	struct sgx_epc_bank *bank;
+	struct sgx_epc_page *page;
+	int i;
+
+	for (i = 0; i < sgx_nr_epc_banks; i++) {
+		bank = &sgx_epc_banks[i];
+		spin_lock(&bank->lock);
+		if (bank->free_cnt) {
+			page = bank->pages[bank->free_cnt - 1];
+			bank->free_cnt--;
+		}
+		spin_unlock(&bank->lock);
+
+		if (page) {
+			page->impl = impl;
+			return page;
+		}
+	}
+
+	return NULL;
+}
+
+/**
+ * sgx_alloc_page - Allocate an EPC page
+ * @flags:	allocation flags
+ * @impl:	implementation for the EPC page
+ *
+ * Try to grab a page from the free EPC page list. If there is a free page
+ * available, it is returned to the caller. If called with SGX_ALLOC_ATOMIC,
+ * the function will return immediately if the list is empty. Otherwise, it
+ * will swap pages up until there is a free page available. Upon returning the
+ * low watermark is checked and ksgxswapd is waken up if we are below it.
+ *
+ * Return:
+ *   a pointer to a &struct sgx_epc_page instace,
+ *   -ENOMEM if all pages are unreclaimable,
+ *   -EBUSY when called with SGX_ALLOC_ATOMIC and out of free pages
+ */
+struct sgx_epc_page *sgx_alloc_page(struct sgx_epc_page_impl *impl,
+				    unsigned int flags)
+{
+	struct sgx_epc_page *entry;
+
+	for ( ; ; ) {
+		entry = sgx_try_alloc_page(impl);
+		if (entry)
+			break;
+
+		if (list_empty(&sgx_active_page_list))
+			return ERR_PTR(-ENOMEM);
+
+		if (flags & SGX_ALLOC_ATOMIC) {
+			entry = ERR_PTR(-EBUSY);
+			break;
+		}
+
+		if (signal_pending(current)) {
+			entry = ERR_PTR(-ERESTARTSYS);
+			break;
+		}
+
+		sgx_reclaim_pages();
+		schedule();
+	}
+
+	if (sgx_calc_free_cnt() < SGX_NR_LOW_PAGES)
+		wake_up(&ksgxswapd_waitq);
+
+	return entry;
+}
+EXPORT_SYMBOL_GPL(sgx_alloc_page);
+
+/**
+ * __sgx_free_page - Free an EPC page
+ * @page:	pointer a previously allocated EPC page
+ *
+ * EREMOVE an EPC page and insert it back to the list of free pages.
+ * If the page is reclaimable, deletes it from the active page list.
+ *
+ * Return:
+ *   0 on success
+ *   -EBUSY if the page cannot be removed from the active list
+ *   SGX error code if EREMOVE fails
+ */
+int __sgx_free_page(struct sgx_epc_page *page)
+{
+	struct sgx_epc_bank *bank = sgx_epc_bank(page);
+	int ret;
+
+	/*
+	 * Remove the page from the active list if necessary.  If the page
+	 * is actively being reclaimed, i.e. RECLAIMABLE is set but the
+	 * page isn't on the active list, return -EBUSY as we can't free
+	 * the page at this time since it is "owned" by the reclaimer.
+	 */
+	if (page->desc & SGX_EPC_PAGE_RECLAIMABLE) {
+		spin_lock(&sgx_active_page_list_lock);
+		if (page->desc & SGX_EPC_PAGE_RECLAIMABLE) {
+			if (list_empty(&page->list)) {
+				spin_unlock(&sgx_active_page_list_lock);
+				return -EBUSY;
+			}
+			list_del(&page->list);
+			page->desc &= ~SGX_EPC_PAGE_RECLAIMABLE;
+		}
+		spin_unlock(&sgx_active_page_list_lock);
+	}
+
+	ret = __eremove(sgx_epc_addr(page));
+	if (ret)
+		return ret;
+
+	spin_lock(&bank->lock);
+	bank->pages[bank->free_cnt++] = page;
+	spin_unlock(&bank->lock);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(__sgx_free_page);
+
+/**
+ * sgx_free_page - Free an EPC page and WARN on failure
+ * @page:	pointer to a previously allocated EPC page
+ *
+ * EREMOVE an EPC page and insert it back to the list of free pages.
+ * If the page is reclaimable, deletes it from the active page list.
+ * WARN on any failure.  For use when the call site cannot (or chooses
+ * not to) handle failure, i.e. the page is leaked on failure.
+ */
+void sgx_free_page(struct sgx_epc_page *page)
+{
+	int ret;
+
+	ret = __sgx_free_page(page);
+	WARN(ret < 0, "sgx: cannot free page, reclaim in-progress");
+	WARN(ret > 0, "sgx: EREMOVE returned %d (0x%x)", ret, ret);
+}
+EXPORT_SYMBOL_GPL(sgx_free_page);
+
+
+/**
+ * sgx_page_reclaimable - mark a page as reclaimable
+ *
+ * @page:	EPC page
+ *
+ * Mark a page as reclaimable and add it to the active page list.  Pages
+ * are automatically removed from the active list when freed.
+ */
+void sgx_page_reclaimable(struct sgx_epc_page *page)
+{
+	spin_lock(&sgx_active_page_list_lock);
+	page->desc |= SGX_EPC_PAGE_RECLAIMABLE;
+	list_add_tail(&page->list, &sgx_active_page_list);
+	spin_unlock(&sgx_active_page_list_lock);
+}
+EXPORT_SYMBOL_GPL(sgx_page_reclaimable);
+
+struct page *sgx_get_backing(struct file *file, pgoff_t index)
+{
+	struct inode *inode = file->f_path.dentry->d_inode;
+	struct address_space *mapping = inode->i_mapping;
+	gfp_t gfpmask = mapping_gfp_mask(mapping);
+
+	return shmem_read_mapping_page_gfp(mapping, index, gfpmask);
+}
+EXPORT_SYMBOL_GPL(sgx_get_backing);
+
+void sgx_put_backing(struct page *backing_page, bool write)
+{
+	if (write)
+		set_page_dirty(backing_page);
+
+	put_page(backing_page);
+}
+EXPORT_SYMBOL_GPL(sgx_put_backing);
 
 static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned long index,
 				    struct sgx_epc_bank *bank)
@@ -66,6 +373,11 @@ static __init void sgx_page_cache_teardown(void)
 	struct sgx_epc_bank *bank;
 	int i;
 
+	if (ksgxswapd_tsk) {
+		kthread_stop(ksgxswapd_tsk);
+		ksgxswapd_tsk = NULL;
+	}
+
 	for (i = 0; i < sgx_nr_epc_banks; i++) {
 		bank = &sgx_epc_banks[i];
 		iounmap((void *)bank->va);
@@ -86,6 +398,8 @@ static __init int sgx_page_cache_init(void)
 	int ret;
 	int i;
 
+	BUILD_BUG_ON(SGX_MAX_EPC_BANKS > (SGX_EPC_BANK_MASK + 1));
+
 	for (i = 0; i < SGX_MAX_EPC_BANKS; i++) {
 		cpuid_count(SGX_CPUID, 2 + i, &eax, &ebx, &ecx, &edx);
 		if (!(eax & 0xF))
@@ -114,6 +428,7 @@ static __init int sgx_page_cache_init(void)
 
 static __init int sgx_init(void)
 {
+	struct task_struct *tsk;
 	unsigned long fc;
 	int ret;
 
@@ -141,6 +456,13 @@ static __init int sgx_init(void)
 	if (ret)
 		return ret;
 
+	tsk = kthread_run(ksgxswapd, NULL, "ksgxswapd");
+	if (IS_ERR(tsk)) {
+		sgx_page_cache_teardown();
+		return PTR_ERR(tsk);
+	}
+	ksgxswapd_tsk = tsk;
+
 	sgx_enabled = true;
 	sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR);
 	return 0;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (8 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-27 21:41   ` Huang, Kai
                     ` (2 more replies)
  2018-08-27 18:53 ` [PATCH v13 11/13] platform/x86: Intel SGX driver Jarkko Sakkinen
                   ` (2 subsequent siblings)
  12 siblings, 3 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

From: Sean Christopherson <sean.j.christopherson@intel.com>

Add a function to perform ENCLS(EINIT), which initializes an enclave,
which can be used by a driver for running enclaves and VMMs.

Writing the LE hash MSRs is extraordinarily expensive, e.g. 3-4x slower
than normal MSRs, so we use a per-cpu cache to track the last known value
of the MSRs to avoid unnecessarily writing the MSRs with the current value.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 arch/x86/include/asm/sgx.h      |  2 +
 arch/x86/kernel/cpu/intel_sgx.c | 86 +++++++++++++++++++++++++++++++--
 2 files changed, 85 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
index baf30d49b71f..c15c156436be 100644
--- a/arch/x86/include/asm/sgx.h
+++ b/arch/x86/include/asm/sgx.h
@@ -108,6 +108,8 @@ void sgx_free_page(struct sgx_epc_page *page);
 void sgx_page_reclaimable(struct sgx_epc_page *page);
 struct page *sgx_get_backing(struct file *file, pgoff_t index);
 void sgx_put_backing(struct page *backing_page, bool write);
+int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken *token,
+	      struct sgx_epc_page *secs_page, u64 lepubkeyhash[4]);
 
 #define ENCLS_FAULT_FLAG 0x40000000UL
 #define ENCLS_FAULT_FLAG_ASM "$0x40000000"
diff --git a/arch/x86/kernel/cpu/intel_sgx.c b/arch/x86/kernel/cpu/intel_sgx.c
index 1046478a3ab9..fe25e6805680 100644
--- a/arch/x86/kernel/cpu/intel_sgx.c
+++ b/arch/x86/kernel/cpu/intel_sgx.c
@@ -9,6 +9,7 @@
 #include <linux/sched/signal.h>
 #include <linux/shmem_fs.h>
 #include <linux/slab.h>
+#include <linux/suspend.h>
 #include <asm/sgx.h>
 #include <asm/sgx_pr.h>
 
@@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);
 static DEFINE_SPINLOCK(sgx_active_page_list_lock);
 static struct task_struct *ksgxswapd_tsk;
 static DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
+static struct notifier_block sgx_pm_notifier;
+static u64 sgx_pm_cnt;
+
+/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx MSRs for each
+ * CPU. The entries are initialized when they are first used by sgx_einit().
+ */
+struct sgx_lepubkeyhash {
+	u64 msrs[4];
+	u64 pm_cnt;
+};
+
+static DEFINE_PER_CPU(struct sgx_lepubkeyhash *, sgx_lepubkeyhash_cache);
 
 /**
  * sgx_reclaim_pages - reclaim EPC pages from the consumers
@@ -328,6 +341,54 @@ void sgx_put_backing(struct page *backing_page, bool write)
 }
 EXPORT_SYMBOL_GPL(sgx_put_backing);
 
+/**
+ * sgx_einit - initialize an enclave
+ * @sigstruct:		a pointer to the SIGSTRUCT
+ * @token:		a pointer to the EINITTOKEN
+ * @secs_page:		a pointer to the SECS EPC page
+ * @lepubkeyhash:	the desired value for IA32_SGXLEPUBKEYHASHx MSRs
+ *
+ * Try to perform EINIT operation. If the MSRs are writable, they are updated
+ * according to @lepubkeyhash.
+ *
+ * Return:
+ *   0 on success,
+ *   -errno on failure
+ *   SGX error code if EINIT fails
+ */
+int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken *token,
+	      struct sgx_epc_page *secs_page, u64 lepubkeyhash[4])
+{
+	struct sgx_lepubkeyhash __percpu *cache;
+	bool cache_valid;
+	int i, ret;
+
+	if (!sgx_lc_enabled)
+		return __einit(sigstruct, token, sgx_epc_addr(secs_page));
+
+	cache = per_cpu(sgx_lepubkeyhash_cache, smp_processor_id());
+	if (!cache) {
+		cache = kzalloc(sizeof(struct sgx_lepubkeyhash), GFP_KERNEL);
+		if (!cache)
+			return -ENOMEM;
+	}
+
+	cache_valid = cache->pm_cnt == sgx_pm_cnt;
+	cache->pm_cnt = sgx_pm_cnt;
+	preempt_disable();
+	for (i = 0; i < 4; i++) {
+		if (cache_valid && lepubkeyhash[i] == cache->msrs[i])
+			continue;
+
+		wrmsrl(MSR_IA32_SGXLEPUBKEYHASH0 + i, lepubkeyhash[i]);
+		cache->msrs[i] = lepubkeyhash[i];
+	}
+	ret = __einit(sigstruct, token, sgx_epc_addr(secs_page));
+	preempt_enable();
+	return ret;
+}
+EXPORT_SYMBOL(sgx_einit);
+
 static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned long index,
 				    struct sgx_epc_bank *bank)
 {
@@ -426,6 +487,15 @@ static __init int sgx_page_cache_init(void)
 	return 0;
 }
 
+static int sgx_pm_notifier_cb(struct notifier_block *nb, unsigned long action,
+			      void *data)
+{
+	if (action == PM_SUSPEND_PREPARE || action == PM_HIBERNATION_PREPARE)
+		sgx_pm_cnt++;
+
+	return NOTIFY_DONE;
+}
+
 static __init int sgx_init(void)
 {
 	struct task_struct *tsk;
@@ -452,20 +522,30 @@ static __init int sgx_init(void)
 	if (!(fc & FEATURE_CONTROL_SGX_LE_WR))
 		pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not writable\n");
 
-	ret = sgx_page_cache_init();
+	sgx_pm_notifier.notifier_call = sgx_pm_notifier_cb;
+	ret = register_pm_notifier(&sgx_pm_notifier);
 	if (ret)
 		return ret;
 
+	ret = sgx_page_cache_init();
+	if (ret)
+		goto out_pm;
+
 	tsk = kthread_run(ksgxswapd, NULL, "ksgxswapd");
 	if (IS_ERR(tsk)) {
-		sgx_page_cache_teardown();
-		return PTR_ERR(tsk);
+		ret = PTR_ERR(tsk);
+		goto out_pcache;
 	}
 	ksgxswapd_tsk = tsk;
 
 	sgx_enabled = true;
 	sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR);
 	return 0;
+out_pcache:
+	sgx_page_cache_teardown();
+out_pm:
+	unregister_pm_notifier(&sgx_pm_notifier);
+	return ret;
 }
 
 arch_initcall(sgx_init);
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (9 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-09-04 17:59   ` Andy Shevchenko
  2018-08-27 18:53 ` [PATCH v13 12/13] platform/x86: ptrace() support for the " Jarkko Sakkinen
  2018-08-27 18:53 ` [PATCH v13 13/13] x86/sgx: Driver documentation Jarkko Sakkinen
  12 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Serge Ayoun, Shay Katz-zamir,
	Suresh Siddha, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, Eric Biggers,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

Intel Software Guard eXtensions (SGX) is a set of CPU instructions that
can be used by applications to set aside private regions of code and
data. The code outside the enclave is disallowed to access the memory
inside the enclave by the CPU access control.

SGX driver provides a ioctl API for loading and initializing enclaves.
Address range for enclaves is reserved with mmap() and they are
destroyed with munmap(). Enclave construction, measurement and
initialization is done with the provided the ioctl API.

Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Co-developed-by: Serge Ayoun <serge.ayoun@intel.com>
Co-developed-by: Shay Katz-zamir <shay.katz-zamir@intel.com>
Co-developed-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Serge Ayoun <serge.ayoun@intel.com>
Signed-off-by: Shay Katz-zamir <shay.katz-zamir@intel.com>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
---
 arch/x86/include/uapi/asm/sgx.h               |  112 ++
 drivers/platform/x86/Kconfig                  |    2 +
 drivers/platform/x86/Makefile                 |    1 +
 drivers/platform/x86/intel_sgx/Kconfig        |   22 +
 drivers/platform/x86/intel_sgx/Makefile       |   13 +
 drivers/platform/x86/intel_sgx/sgx.h          |  211 ++++
 drivers/platform/x86/intel_sgx/sgx_encl.c     | 1016 +++++++++++++++++
 .../platform/x86/intel_sgx/sgx_encl_page.c    |  288 +++++
 drivers/platform/x86/intel_sgx/sgx_fault.c    |  157 +++
 drivers/platform/x86/intel_sgx/sgx_ioctl.c    |  234 ++++
 drivers/platform/x86/intel_sgx/sgx_main.c     |  257 +++++
 drivers/platform/x86/intel_sgx/sgx_vma.c      |   58 +
 12 files changed, 2371 insertions(+)
 create mode 100644 arch/x86/include/uapi/asm/sgx.h
 create mode 100644 drivers/platform/x86/intel_sgx/Kconfig
 create mode 100644 drivers/platform/x86/intel_sgx/Makefile
 create mode 100644 drivers/platform/x86/intel_sgx/sgx.h
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_encl.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_encl_page.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_fault.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_ioctl.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_main.c
 create mode 100644 drivers/platform/x86/intel_sgx/sgx_vma.c

diff --git a/arch/x86/include/uapi/asm/sgx.h b/arch/x86/include/uapi/asm/sgx.h
new file mode 100644
index 000000000000..498daac0d756
--- /dev/null
+++ b/arch/x86/include/uapi/asm/sgx.h
@@ -0,0 +1,112 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2016-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * Contact Information:
+ * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
+ * Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Intel Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *
+ * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
+ * Suresh Siddha <suresh.b.siddha@intel.com>
+ */
+
+#ifndef _UAPI_ASM_X86_SGX_H
+#define _UAPI_ASM_X86_SGX_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define SGX_MAGIC 0xA4
+
+#define SGX_IOC_ENCLAVE_CREATE \
+	_IOW(SGX_MAGIC, 0x00, struct sgx_enclave_create)
+#define SGX_IOC_ENCLAVE_ADD_PAGE \
+	_IOW(SGX_MAGIC, 0x01, struct sgx_enclave_add_page)
+#define SGX_IOC_ENCLAVE_INIT \
+	_IOW(SGX_MAGIC, 0x02, struct sgx_enclave_init)
+
+/* IOCTL return values */
+#define SGX_POWER_LOST_ENCLAVE		0x40000000
+
+/**
+ * struct sgx_enclave_create - parameter structure for the
+ *                             %SGX_IOC_ENCLAVE_CREATE ioctl
+ * @src:	address for the SECS page data
+ */
+struct sgx_enclave_create  {
+	__u64	src;
+};
+
+/**
+ * struct sgx_enclave_add_page - parameter structure for the
+ *                               %SGX_IOC_ENCLAVE_ADD_PAGE ioctl
+ * @addr:	address within the ELRANGE
+ * @src:	address for the page data
+ * @secinfo:	address for the SECINFO data
+ * @mrmask:	bitmask for the measured 256 byte chunks
+ */
+struct sgx_enclave_add_page {
+	__u64	addr;
+	__u64	src;
+	__u64	secinfo;
+	__u16	mrmask;
+} __attribute__((__packed__));
+
+
+/**
+ * struct sgx_enclave_init - parameter structure for the
+ *                           %SGX_IOC_ENCLAVE_INIT ioctl
+ * @addr:	address within the ELRANGE
+ * @sigstruct:	address for the SIGSTRUCT data
+ */
+struct sgx_enclave_init {
+	__u64	addr;
+	__u64	sigstruct;
+};
+
+#endif /* _UAPI_ASM_X86_SGX_H */
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 107d336453b2..d5954badbc7c 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1229,6 +1229,8 @@ config I2C_MULTI_INSTANTIATE
 	  To compile this driver as a module, choose M here: the module
 	  will be called i2c-multi-instantiate.
 
+source "drivers/platform/x86/intel_sgx/Kconfig"
+
 endif # X86_PLATFORM_DEVICES
 
 config PMC_ATOM
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 50dc8f280914..f4c2c6734767 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -92,3 +92,4 @@ obj-$(CONFIG_MLX_PLATFORM)	+= mlx-platform.o
 obj-$(CONFIG_INTEL_TURBO_MAX_3) += intel_turbo_max_3.o
 obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN)	+= intel_chtdc_ti_pwrbtn.o
 obj-$(CONFIG_I2C_MULTI_INSTANTIATE)	+= i2c-multi-instantiate.o
+obj-$(CONFIG_INTEL_SGX) += intel_sgx/
diff --git a/drivers/platform/x86/intel_sgx/Kconfig b/drivers/platform/x86/intel_sgx/Kconfig
new file mode 100644
index 000000000000..8e6c57c28443
--- /dev/null
+++ b/drivers/platform/x86/intel_sgx/Kconfig
@@ -0,0 +1,22 @@
+#
+# Intel SGX
+#
+
+config INTEL_SGX
+	tristate "Intel(R) SGX Driver"
+	default n
+	depends on X86_64 && CPU_SUP_INTEL
+	select INTEL_SGX_CORE
+	select MMU_NOTIFIER
+	select CRYPTO
+	select CRYPTO_SHA256
+	help
+	Intel(R) SGX is a set of CPU instructions that can be used by
+	applications to set aside private regions of code and data.  The code
+	outside the enclave is disallowed to access the memory inside the
+	enclave by the CPU access control.
+
+	The firmware uses PRMRR registers to reserve an area of physical memory
+	called Enclave Page Cache (EPC). There is a hardware unit in the
+	processor called Memory Encryption Engine. The MEE encrypts and decrypts
+	the EPC pages as they enter and leave the processor package.
diff --git a/drivers/platform/x86/intel_sgx/Makefile b/drivers/platform/x86/intel_sgx/Makefile
new file mode 100644
index 000000000000..95f254e30a8b
--- /dev/null
+++ b/drivers/platform/x86/intel_sgx/Makefile
@@ -0,0 +1,13 @@
+#
+# Intel SGX
+#
+
+obj-$(CONFIG_INTEL_SGX) += intel_sgx.o
+
+intel_sgx-$(CONFIG_INTEL_SGX) += \
+	sgx_ioctl.o \
+	sgx_encl.o \
+	sgx_encl_page.o \
+	sgx_main.o \
+	sgx_fault.o \
+	sgx_vma.o \
diff --git a/drivers/platform/x86/intel_sgx/sgx.h b/drivers/platform/x86/intel_sgx/sgx.h
new file mode 100644
index 000000000000..2323469cf081
--- /dev/null
+++ b/drivers/platform/x86/intel_sgx/sgx.h
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-18 Intel Corporation.
+
+#ifndef __ARCH_INTEL_SGX_H__
+#define __ARCH_INTEL_SGX_H__
+
+#include <crypto/hash.h>
+#include <linux/kref.h>
+#include <linux/mmu_notifier.h>
+#include <linux/mmu_notifier.h>
+#include <linux/radix-tree.h>
+#include <linux/radix-tree.h>
+#include <linux/rbtree.h>
+#include <linux/rwsem.h>
+#include <linux/sched.h>
+#include <linux/workqueue.h>
+#include <asm/sgx.h>
+#include <asm/sgx_pr.h>
+#include <uapi/asm/sgx.h>
+
+#define sgx_pr_ratelimited(level, encl, fmt, ...)			\
+	pr_ ## level ## _ratelimited("[%d:0x%p] " fmt,			\
+				     pid_nr((encl)->tgid),		\
+				     (void *)(encl)->base, ##__VA_ARGS__)
+#define sgx_dbg(encl, fmt, ...) \
+	sgx_pr_ratelimited(debug, encl, fmt, ##__VA_ARGS__)
+#define sgx_info(encl, fmt, ...) \
+	sgx_pr_ratelimited(info, encl, fmt, ##__VA_ARGS__)
+#define sgx_warn(encl, fmt, ...) \
+	sgx_pr_ratelimited(warn, encl, fmt, ##__VA_ARGS__)
+#define sgx_err(encl, fmt, ...) \
+	sgx_pr_ratelimited(err, encl, fmt, ##__VA_ARGS__)
+#define sgx_crit(encl, fmt, ...) \
+	sgx_pr_ratelimited(crit, encl, fmt, ##__VA_ARGS__)
+
+#define SGX_EINIT_SPIN_COUNT	20
+#define SGX_EINIT_SLEEP_COUNT	50
+#define SGX_EINIT_SLEEP_TIME	20
+
+#define SGX_VA_SLOT_COUNT 512
+
+struct sgx_va_page {
+	struct sgx_epc_page *epc_page;
+	DECLARE_BITMAP(slots, SGX_VA_SLOT_COUNT);
+	struct list_head list;
+};
+
+/**
+ * enum sgx_encl_page_desc - defines bits and masks for an enclave page's desc
+ *
+ * @SGX_ENCL_PAGE_TCS:
+ * @SGX_ENCL_PAGE_LOADED:
+ * @SGX_ENCL_PAGE_RESERVED:  Set when we need to temporarily prevent reclaim,
+ *			     e.g. the page is being directly accessed for debug
+ *			     purposes.
+ * @SGX_ENCL_PAGE_RECLAIMED: Set when a LOADED page is in the process of being
+ *			     reclaimed by the EPC manager.  Once RECLAIMED is
+ *			     set we no longer "own" the EPC page; we're still
+ *			     involved in evicting the page, but we cannot free
+ *			     the EPC page or rely on its contents in any way.
+ *
+ * @SGX_ENCL_PAGE_VA_OFFSET_MASK: Holds the offset into the VA page that was
+ *				  used to evict the page.
+ * @SGX_ENCL_PAGE_ADDR_MASK:	  Holds the userspace virtual address of the
+ *				  page.  Primarily used to manipulate PTEs and
+ *				  retrieve an enclave from a given page.
+ *
+ * enum sgx_encl_page_desc defines the layout of struct sgx_encl_page's @desc.
+ * The metadata for an enclave page is compressed into a single variable to
+ * reduce memory consumption as the size of enclaves are effectively unbounded,
+ * e.g. a userspace process can create a 512gb enclave regardless of the actual
+ * amount of EPC in the system.
+ *
+ * WARNING: Bits 11:3 are effectively a union, similar to how a union is used
+ * to store either a pointer to an EPC page or VA page depending on whether or
+ * not a struct sgx_encl_page is resident in the EPC.  When the page is evicted
+ * from the EPC, bits 11:3 are used to hold the VA offset.  Flags that may be
+ * set/cleared at any time must not reside in bits 11:3.
+ */
+enum sgx_encl_page_desc {
+	SGX_ENCL_PAGE_TCS		= BIT(0),
+	SGX_ENCL_PAGE_LOADED		= BIT(1),
+	/* Bit 2 is free, may be used at any time */
+
+	SGX_ENCL_PAGE_RESERVED		= BIT(3),
+	SGX_ENCL_PAGE_RECLAIMED		= BIT(4),
+	/* Bits 11:5 are free, may only be used when page is resident in EPC */
+
+	SGX_ENCL_PAGE_VA_OFFSET_MASK	= GENMASK_ULL(11, 3),
+
+	SGX_ENCL_PAGE_ADDR_MASK		= PAGE_MASK,
+};
+
+#define SGX_ENCL_PAGE_ADDR(encl_page) \
+	((encl_page)->desc & SGX_ENCL_PAGE_ADDR_MASK)
+#define SGX_ENCL_PAGE_VA_OFFSET(encl_page) \
+	((encl_page)->desc & SGX_ENCL_PAGE_VA_OFFSET_MASK)
+#define SGX_ENCL_PAGE_BACKING_INDEX(encl_page, encl)		\
+({								\
+	pgoff_t index;						\
+	if (!PFN_DOWN(encl_page->desc))				\
+		index = PFN_DOWN(encl->size);			\
+	else							\
+		index = PFN_DOWN(encl_page->desc - encl->base);	\
+	index;							\
+})
+#define SGX_ENCL_PAGE_PCMD_OFFSET(encl_page, encl)		\
+({								\
+	unsigned long ret;					\
+	ret = SGX_ENCL_PAGE_BACKING_INDEX(encl_page, encl);	\
+	((ret & 31) * 128);					\
+})
+
+struct sgx_encl_page {
+	unsigned long desc;
+	union {
+		struct sgx_epc_page *epc_page;
+		struct sgx_va_page *va_page;
+	};
+	struct sgx_encl *encl;
+	struct sgx_epc_page_impl impl;
+};
+
+enum sgx_encl_flags {
+	SGX_ENCL_INITIALIZED	= BIT(0),
+	SGX_ENCL_DEBUG		= BIT(1),
+	SGX_ENCL_SUSPEND	= BIT(2),
+	SGX_ENCL_DEAD		= BIT(3),
+};
+
+struct sgx_encl {
+	unsigned int flags;
+	uint64_t attributes;
+	uint64_t xfrm;
+	unsigned int page_cnt;
+	unsigned int secs_child_cnt;
+	struct mutex lock;
+	struct mm_struct *mm;
+	struct file *backing;
+	struct file *pcmd;
+	struct kref refcount;
+	unsigned long base;
+	unsigned long size;
+	unsigned long ssaframesize;
+	struct list_head va_pages;
+	struct radix_tree_root page_tree;
+	struct list_head add_page_reqs;
+	struct work_struct add_page_work;
+	struct sgx_encl_page secs;
+	struct pid *tgid;
+	struct mmu_notifier mmu_notifier;
+	struct notifier_block pm_notifier;
+};
+
+extern struct workqueue_struct *sgx_add_page_wq;
+extern u64 sgx_encl_size_max_32;
+extern u64 sgx_encl_size_max_64;
+extern u64 sgx_xfrm_mask;
+extern u32 sgx_misc_reserved;
+extern u32 sgx_xsave_size_tbl[64];
+
+extern const struct vm_operations_struct sgx_vm_ops;
+
+int sgx_encl_find(struct mm_struct *mm, unsigned long addr,
+		  struct vm_area_struct **vma);
+void sgx_invalidate(struct sgx_encl *encl, bool flush_cpus);
+#define SGX_INVD(ret, encl, fmt, ...)		\
+do {						\
+	if (WARN(ret, "sgx: " fmt, ##__VA_ARGS__))	\
+		sgx_invalidate(encl, true);	\
+} while (0)
+
+struct sgx_encl *sgx_encl_alloc(struct sgx_secs *secs);
+int sgx_encl_create(struct sgx_encl *encl, struct sgx_secs *secs);
+struct sgx_encl_page *sgx_encl_alloc_page(struct sgx_encl *encl,
+					  unsigned long addr);
+void sgx_encl_free_page(struct sgx_encl_page *encl_page);
+int sgx_encl_add_page(struct sgx_encl *encl, unsigned long addr, void *data,
+		      struct sgx_secinfo *secinfo, unsigned int mrmask);
+int sgx_encl_init(struct sgx_encl *encl, struct sgx_sigstruct *sigstruct,
+		  struct sgx_einittoken *einittoken);
+void sgx_encl_block(struct sgx_encl_page *encl_page);
+void sgx_encl_track(struct sgx_encl *encl);
+int sgx_encl_load_page(struct sgx_encl_page *encl_page,
+		       struct sgx_epc_page *epc_page);
+void sgx_encl_release(struct kref *ref);
+
+long sgx_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
+#ifdef CONFIG_COMPAT
+long sgx_compat_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
+#endif
+
+/* Utility functions */
+int sgx_test_and_clear_young(struct sgx_encl_page *page);
+void sgx_flush_cpus(struct sgx_encl *encl);
+
+struct sgx_encl_page *sgx_fault_page(struct vm_area_struct *vma,
+				     unsigned long addr,
+				     bool do_reserve);
+
+extern const struct sgx_epc_page_ops sgx_encl_page_ops;
+
+void sgx_set_epc_page(struct sgx_encl_page *encl_page,
+		      struct sgx_epc_page *epc_page);
+void sgx_set_page_reclaimable(struct sgx_encl_page *encl_page);
+struct sgx_epc_page *sgx_alloc_va_page(unsigned int flags);
+unsigned int sgx_alloc_va_slot(struct sgx_va_page *va_page);
+void sgx_free_va_slot(struct sgx_va_page *va_page, unsigned int offset);
+bool sgx_va_page_full(struct sgx_va_page *va_page);
+
+#endif /* __ARCH_X86_INTEL_SGX_H__ */
diff --git a/drivers/platform/x86/intel_sgx/sgx_encl.c b/drivers/platform/x86/intel_sgx/sgx_encl.c
new file mode 100644
index 000000000000..c1a0065c4710
--- /dev/null
+++ b/drivers/platform/x86/intel_sgx/sgx_encl.c
@@ -0,0 +1,1016 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-18 Intel Corporation.
+
+#include <asm/mman.h>
+#include <linux/delay.h>
+#include <linux/file.h>
+#include <linux/hashtable.h>
+#include <linux/highmem.h>
+#include <linux/ratelimit.h>
+#include <linux/sched/signal.h>
+#include <linux/shmem_fs.h>
+#include <linux/slab.h>
+#include <linux/suspend.h>
+#include "sgx.h"
+
+struct sgx_add_page_req {
+	struct sgx_encl *encl;
+	struct sgx_encl_page *encl_page;
+	struct sgx_secinfo secinfo;
+	u16 mrmask;
+	struct list_head list;
+};
+
+/**
+ * sgx_encl_find - find an enclave
+ * @mm:		mm struct of the current process
+ * @addr:	address in the ELRANGE
+ * @vma:	the resulting VMA
+ *
+ * Finds an enclave identified by the given address. Gives back the VMA, that
+ * is part of the enclave, located in that address. The VMA is given back if it
+ * is a proper enclave VMA even if an &sgx_encl instance does not exist
+ * yet (enclave creation has not been performed).
+ *
+ * Return:
+ *   0 on success,
+ *   -EINVAL if an enclave was not found,
+ *   -ENOENT if the enclave has not been created yet
+ */
+int sgx_encl_find(struct mm_struct *mm, unsigned long addr,
+		  struct vm_area_struct **vma)
+{
+	struct vm_area_struct *result;
+	struct sgx_encl *encl;
+
+	result = find_vma(mm, addr);
+	if (!result || result->vm_ops != &sgx_vm_ops || addr < result->vm_start)
+		return -EINVAL;
+
+	encl = result->vm_private_data;
+	*vma = result;
+
+	return encl ? 0 : -ENOENT;
+}
+
+/**
+ * sgx_invalidate - kill an enclave
+ * @encl:	an &sgx_encl instance
+ * @flush_cpus	Set if there can be active threads inside the enclave.
+ *
+ * Mark the enclave as dead and immediately free its EPC pages (but not
+ * its resources).  For active enclaves, the entry points to the enclave
+ * are destroyed first and hardware threads are kicked out so that the
+ * EPC pages can be safely manipulated.
+ */
+void sgx_invalidate(struct sgx_encl *encl, bool flush_cpus)
+{
+	struct sgx_encl_page *entry;
+	struct radix_tree_iter iter;
+	struct vm_area_struct *vma;
+	unsigned long addr;
+	void **slot;
+
+	if (encl->flags & SGX_ENCL_DEAD)
+		return;
+
+	encl->flags |= SGX_ENCL_DEAD;
+	if (flush_cpus) {
+		radix_tree_for_each_slot(slot, &encl->page_tree, &iter, 0) {
+			entry = *slot;
+			addr = SGX_ENCL_PAGE_ADDR(entry);
+			if ((entry->desc & SGX_ENCL_PAGE_LOADED) &&
+			    (entry->desc & SGX_ENCL_PAGE_TCS) &&
+			    !sgx_encl_find(encl->mm, addr, &vma))
+				zap_vma_ptes(vma, addr, PAGE_SIZE);
+		}
+		sgx_flush_cpus(encl);
+	}
+	radix_tree_for_each_slot(slot, &encl->page_tree, &iter, 0) {
+		entry = *slot;
+		/* If the page has RECLAIMED set, it is being reclaimed so we
+		 * need to check that and let the swapper thread to free the
+		 * page if this is the case.
+		 */
+		if ((entry->desc & SGX_ENCL_PAGE_LOADED) &&
+		    !(entry->desc & SGX_ENCL_PAGE_RECLAIMED)) {
+			if (!__sgx_free_page(entry->epc_page))
+				entry->desc &= ~SGX_ENCL_PAGE_LOADED;
+		}
+	}
+}
+
+static int sgx_measure(struct sgx_epc_page *secs_page,
+		       struct sgx_epc_page *epc_page,
+		       u16 mrmask)
+{
+	int ret = 0;
+	void *secs;
+	void *epc;
+	int i;
+	int j;
+
+	if (!mrmask)
+		return ret;
+
+	secs = sgx_epc_addr(secs_page);
+	epc = sgx_epc_addr(epc_page);
+
+	for (i = 0, j = 1; i < 0x1000 && !ret; i += 0x100, j <<= 1) {
+		if (!(j & mrmask))
+			continue;
+
+		ret = __eextend(secs, (void *)((unsigned long)epc + i));
+	}
+
+	return ret;
+}
+
+static int sgx_eadd(struct sgx_epc_page *secs_page,
+		    struct sgx_epc_page *epc_page,
+		    unsigned long linaddr,
+		    struct sgx_secinfo *secinfo,
+		    struct page *backing)
+{
+	struct sgx_pageinfo pginfo;
+	int ret;
+
+	pginfo.secs = (unsigned long)sgx_epc_addr(secs_page);
+	pginfo.addr = linaddr;
+	pginfo.metadata = (unsigned long)secinfo;
+
+	pginfo.contents = (unsigned long)kmap_atomic(backing);
+	ret = __eadd(&pginfo, sgx_epc_addr(epc_page));
+	kunmap_atomic((void *)(unsigned long)pginfo.contents);
+
+	return ret;
+}
+
+static bool sgx_process_add_page_req(struct sgx_add_page_req *req,
+				     struct sgx_epc_page *epc_page)
+{
+	struct sgx_encl_page *encl_page = req->encl_page;
+	struct sgx_encl *encl = req->encl;
+	struct sgx_secinfo secinfo;
+	struct vm_area_struct *vma;
+	pgoff_t backing_index;
+	struct page *backing;
+	unsigned long addr;
+	int ret;
+
+	if (encl->flags & (SGX_ENCL_SUSPEND | SGX_ENCL_DEAD))
+		return false;
+
+	addr = SGX_ENCL_PAGE_ADDR(encl_page);
+	ret = sgx_encl_find(encl->mm, addr, &vma);
+	if (ret)
+		return false;
+
+	backing_index = SGX_ENCL_PAGE_BACKING_INDEX(encl_page, encl);
+	backing = sgx_get_backing(encl->backing, backing_index);
+	if (IS_ERR(backing))
+		return false;
+
+	ret = vm_insert_pfn(vma, addr, PFN_DOWN(epc_page->desc));
+	if (ret) {
+		sgx_err(encl, "%s: vm_insert_pfn() returned %d\n", __func__,
+			ret);
+		sgx_put_backing(backing, false);
+		return false;
+	}
+
+	/*
+	 * The SECINFO field must be 64-byte aligned, copy it to a local
+	 * variable that is guaranteed to be aligned as req->secinfo may
+	 * or may not be 64-byte aligned, e.g. req may have been allocated
+	 * via kzalloc which is not aware of __aligned attributes.
+	 */
+	memcpy(&secinfo, &req->secinfo, sizeof(secinfo));
+
+	ret = sgx_eadd(encl->secs.epc_page, epc_page, addr, &secinfo, backing);
+
+	sgx_put_backing(backing, false);
+	if (ret) {
+		sgx_err(encl, "EADD returned %d\n", ret);
+		zap_vma_ptes(vma, addr, PAGE_SIZE);
+		return false;
+	}
+
+	ret = sgx_measure(encl->secs.epc_page, epc_page, req->mrmask);
+	if (ret) {
+		sgx_err(encl, "EEXTEND returned %d\n", ret);
+		zap_vma_ptes(vma, addr, PAGE_SIZE);
+		return false;
+	}
+
+	encl_page->encl = encl;
+	encl->secs_child_cnt++;
+	sgx_set_epc_page(encl_page, epc_page);
+	sgx_set_page_reclaimable(encl_page);
+	return true;
+}
+
+static void sgx_add_page_worker(struct work_struct *work)
+{
+	struct sgx_add_page_req *req;
+	bool skip_rest = false;
+	bool is_empty = false;
+	struct sgx_encl *encl;
+	struct sgx_epc_page *epc_page;
+
+	encl = container_of(work, struct sgx_encl, add_page_work);
+
+	do {
+		schedule();
+
+		mutex_lock(&encl->lock);
+		if (encl->flags & SGX_ENCL_DEAD)
+			skip_rest = true;
+
+		req = list_first_entry(&encl->add_page_reqs,
+				       struct sgx_add_page_req, list);
+		list_del(&req->list);
+		is_empty = list_empty(&encl->add_page_reqs);
+		mutex_unlock(&encl->lock);
+
+		if (skip_rest)
+			goto next;
+
+		epc_page = sgx_alloc_page(&req->encl_page->impl, 0);
+		down_read(&encl->mm->mmap_sem);
+		mutex_lock(&encl->lock);
+
+		if (IS_ERR(epc_page)) {
+			sgx_invalidate(encl, false);
+			skip_rest = true;
+		} else	if (!sgx_process_add_page_req(req, epc_page)) {
+			sgx_free_page(epc_page);
+			sgx_invalidate(encl, false);
+			skip_rest = true;
+		}
+
+		mutex_unlock(&encl->lock);
+		up_read(&encl->mm->mmap_sem);
+
+next:
+		kfree(req);
+	} while (!kref_put(&encl->refcount, sgx_encl_release) && !is_empty);
+}
+
+static u32 sgx_calc_ssaframesize(u32 miscselect, u64 xfrm)
+{
+	u32 size_max = PAGE_SIZE;
+	u32 size;
+	int i;
+
+	for (i = 2; i < 64; i++) {
+		if (!((1 << i) & xfrm))
+			continue;
+
+		size = SGX_SSA_GPRS_SIZE + sgx_xsave_size_tbl[i];
+		if (miscselect & SGX_MISC_EXINFO)
+			size += SGX_SSA_MISC_EXINFO_SIZE;
+
+		if (size > size_max)
+			size_max = size;
+	}
+
+	return (size_max + PAGE_SIZE - 1) >> PAGE_SHIFT;
+}
+
+static int sgx_validate_secs(const struct sgx_secs *secs,
+			     unsigned long ssaframesize)
+{
+	int i;
+
+	if (secs->size < (2 * PAGE_SIZE) ||
+	    (secs->size & (secs->size - 1)) != 0)
+		return -EINVAL;
+
+	if (secs->base & (secs->size - 1))
+		return -EINVAL;
+
+	if (secs->attributes & SGX_ATTR_RESERVED_MASK ||
+	    secs->miscselect & sgx_misc_reserved)
+		return -EINVAL;
+
+	if (secs->attributes & SGX_ATTR_MODE64BIT) {
+		if (secs->size > sgx_encl_size_max_64)
+			return -EINVAL;
+	} else {
+		/* On 64-bit architecture allow 32-bit encls only in
+		 * the compatibility mode.
+		 */
+		if (!test_thread_flag(TIF_ADDR32))
+			return -EINVAL;
+		if (secs->size > sgx_encl_size_max_32)
+			return -EINVAL;
+	}
+
+	if ((secs->xfrm & 0x3) != 0x3 || (secs->xfrm & ~sgx_xfrm_mask))
+		return -EINVAL;
+
+	/* Check that BNDREGS and BNDCSR are equal. */
+	if (((secs->xfrm >> 3) & 1) != ((secs->xfrm >> 4) & 1))
+		return -EINVAL;
+
+	if (!secs->ssa_frame_size || ssaframesize > secs->ssa_frame_size)
+		return -EINVAL;
+
+	for (i = 0; i < SGX_SECS_RESERVED1_SIZE; i++)
+		if (secs->reserved1[i])
+			return -EINVAL;
+
+	for (i = 0; i < SGX_SECS_RESERVED2_SIZE; i++)
+		if (secs->reserved2[i])
+			return -EINVAL;
+
+	for (i = 0; i < SGX_SECS_RESERVED3_SIZE; i++)
+		if (secs->reserved3[i])
+			return -EINVAL;
+
+	for (i = 0; i < SGX_SECS_RESERVED4_SIZE; i++)
+		if (secs->reserved4[i])
+			return -EINVAL;
+
+	return 0;
+}
+
+static void sgx_mmu_notifier_release(struct mmu_notifier *mn,
+				     struct mm_struct *mm)
+{
+	struct sgx_encl *encl =
+		container_of(mn, struct sgx_encl, mmu_notifier);
+
+	mutex_lock(&encl->lock);
+	encl->flags |= SGX_ENCL_DEAD;
+	mutex_unlock(&encl->lock);
+}
+
+static const struct mmu_notifier_ops sgx_mmu_notifier_ops = {
+	.release	= sgx_mmu_notifier_release,
+};
+
+static int sgx_encl_grow(struct sgx_encl *encl)
+{
+	struct sgx_va_page *va_page;
+	int ret;
+
+	BUILD_BUG_ON(SGX_VA_SLOT_COUNT !=
+		(SGX_ENCL_PAGE_VA_OFFSET_MASK >> 3) + 1);
+
+	mutex_lock(&encl->lock);
+	if (!(encl->page_cnt % SGX_VA_SLOT_COUNT)) {
+		mutex_unlock(&encl->lock);
+
+		va_page = kzalloc(sizeof(*va_page), GFP_KERNEL);
+		if (!va_page)
+			return -ENOMEM;
+		va_page->epc_page = sgx_alloc_va_page(0);
+		if (IS_ERR(va_page->epc_page)) {
+			ret = PTR_ERR(va_page->epc_page);
+			kfree(va_page);
+			return ret;
+		}
+
+		mutex_lock(&encl->lock);
+		if (encl->page_cnt % SGX_VA_SLOT_COUNT) {
+			sgx_free_page(va_page->epc_page);
+			kfree(va_page);
+		} else {
+			list_add(&va_page->list, &encl->va_pages);
+		}
+	}
+	encl->page_cnt++;
+	mutex_unlock(&encl->lock);
+	return 0;
+}
+
+/**
+ * sgx_encl_alloc - allocate memory for an enclave and set attributes
+ *
+ * @secs:	SECS data (must be page aligned)
+ *
+ * Allocates a new &sgx_encl instance. Validates SECS attributes, creates
+ * backing storage for the enclave and sets enclave attributes to sane initial
+ * values.
+ *
+ * Return:
+ *   an &sgx_encl instance,
+ *   -errno otherwise
+ */
+struct sgx_encl *sgx_encl_alloc(struct sgx_secs *secs)
+{
+	unsigned long ssaframesize;
+	struct sgx_encl *encl;
+	struct file *backing;
+	struct file *pcmd;
+
+	ssaframesize = sgx_calc_ssaframesize(secs->miscselect, secs->xfrm);
+	if (sgx_validate_secs(secs, ssaframesize))
+		return ERR_PTR(-EINVAL);
+
+	backing = shmem_file_setup("[dev/sgx]", secs->size + PAGE_SIZE,
+				   VM_NORESERVE);
+	if (IS_ERR(backing))
+		return (void *)backing;
+
+	pcmd = shmem_file_setup("[dev/sgx]", (secs->size + PAGE_SIZE) >> 5,
+				VM_NORESERVE);
+	if (IS_ERR(pcmd)) {
+		fput(backing);
+		return (void *)pcmd;
+	}
+
+	encl = kzalloc(sizeof(*encl), GFP_KERNEL);
+	if (!encl) {
+		fput(backing);
+		fput(pcmd);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	encl->attributes = secs->attributes;
+	encl->xfrm = secs->xfrm;
+
+	kref_init(&encl->refcount);
+	INIT_LIST_HEAD(&encl->add_page_reqs);
+	INIT_LIST_HEAD(&encl->va_pages);
+	INIT_RADIX_TREE(&encl->page_tree, GFP_KERNEL);
+	mutex_init(&encl->lock);
+	INIT_WORK(&encl->add_page_work, sgx_add_page_worker);
+
+	encl->mm = current->mm;
+	encl->base = secs->base;
+	encl->size = secs->size;
+	encl->ssaframesize = secs->ssa_frame_size;
+	encl->backing = backing;
+	encl->pcmd = pcmd;
+
+	return encl;
+}
+
+static int sgx_encl_pm_notifier(struct notifier_block *nb,
+				unsigned long action, void *data)
+{
+	struct sgx_encl *encl = container_of(nb, struct sgx_encl, pm_notifier);
+
+	if (action != PM_SUSPEND_PREPARE && action != PM_HIBERNATION_PREPARE)
+		return NOTIFY_DONE;
+
+	mutex_lock(&encl->lock);
+	sgx_invalidate(encl, false);
+	encl->flags |= SGX_ENCL_SUSPEND;
+	mutex_unlock(&encl->lock);
+	flush_work(&encl->add_page_work);
+	return NOTIFY_DONE;
+}
+
+/**
+ * sgx_encl_create - create an enclave
+ *
+ * @encl:	an enclave
+ * @secs:	page aligned SECS data
+ *
+ * Validates SECS attributes, allocates an EPC page for the SECS and creates
+ * the enclave by performing ECREATE.
+ *
+ * Return:
+ *   0 on success,
+ *   -errno otherwise
+ */
+int sgx_encl_create(struct sgx_encl *encl, struct sgx_secs *secs)
+{
+	struct vm_area_struct *vma;
+	struct sgx_pageinfo pginfo;
+	struct sgx_secinfo secinfo;
+	struct sgx_epc_page *secs_epc;
+	long ret;
+
+	secs_epc = sgx_alloc_page(&encl->secs.impl, 0);
+	if (IS_ERR(secs_epc)) {
+		ret = PTR_ERR(secs_epc);
+		return ret;
+	}
+
+	sgx_set_epc_page(&encl->secs, secs_epc);
+	encl->secs.encl = encl;
+	encl->secs.impl.ops = &sgx_encl_page_ops;
+	encl->tgid = get_pid(task_tgid(current));
+
+	ret = sgx_encl_grow(encl);
+	if (ret)
+		return ret;
+
+	pginfo.addr = 0;
+	pginfo.contents = (unsigned long)secs;
+	pginfo.metadata = (unsigned long)&secinfo;
+	pginfo.secs = 0;
+	memset(&secinfo, 0, sizeof(secinfo));
+	ret = __ecreate((void *)&pginfo, sgx_epc_addr(secs_epc));
+
+	if (ret) {
+		sgx_dbg(encl, "ECREATE returned %ld\n", ret);
+		return ret;
+	}
+
+	if (secs->attributes & SGX_ATTR_DEBUG)
+		encl->flags |= SGX_ENCL_DEBUG;
+
+	encl->mmu_notifier.ops = &sgx_mmu_notifier_ops;
+	ret = mmu_notifier_register(&encl->mmu_notifier, encl->mm);
+	if (ret) {
+		if (ret == -EINTR)
+			ret = -ERESTARTSYS;
+		encl->mmu_notifier.ops = NULL;
+		return ret;
+	}
+
+	encl->pm_notifier.notifier_call = &sgx_encl_pm_notifier;
+	ret = register_pm_notifier(&encl->pm_notifier);
+	if (ret) {
+		encl->pm_notifier.notifier_call = NULL;
+		return ret;
+	}
+
+	down_read(&current->mm->mmap_sem);
+	ret = sgx_encl_find(current->mm, secs->base, &vma);
+	if (ret != -ENOENT) {
+		if (!ret)
+			ret = -EINVAL;
+		up_read(&current->mm->mmap_sem);
+		return ret;
+	}
+
+	if (vma->vm_start != secs->base ||
+	    vma->vm_end != (secs->base + secs->size) ||
+	    vma->vm_pgoff != 0) {
+		ret = -EINVAL;
+		up_read(&current->mm->mmap_sem);
+		return ret;
+	}
+
+	vma->vm_private_data = encl;
+	up_read(&current->mm->mmap_sem);
+	return 0;
+}
+
+static int sgx_validate_secinfo(struct sgx_secinfo *secinfo)
+{
+	u64 page_type = secinfo->flags & SGX_SECINFO_PAGE_TYPE_MASK;
+	u64 perm = secinfo->flags & SGX_SECINFO_PERMISSION_MASK;
+	int i;
+
+	if ((secinfo->flags & SGX_SECINFO_RESERVED_MASK) ||
+	    ((perm & SGX_SECINFO_W) && !(perm & SGX_SECINFO_R)) ||
+	    (page_type != SGX_SECINFO_TCS &&
+	     page_type != SGX_SECINFO_REG))
+		return -EINVAL;
+
+	for (i = 0; i < SGX_SECINFO_RESERVED_SIZE; i++)
+		if (secinfo->reserved[i])
+			return -EINVAL;
+
+	return 0;
+}
+
+static bool sgx_validate_offset(struct sgx_encl *encl, unsigned long offset)
+{
+	if (offset & (PAGE_SIZE - 1))
+		return false;
+
+	if (offset >= encl->size)
+		return false;
+
+	return true;
+}
+
+static int sgx_validate_tcs(struct sgx_encl *encl, struct sgx_tcs *tcs)
+{
+	int i;
+
+	if (tcs->flags & SGX_TCS_RESERVED_MASK)
+		return -EINVAL;
+
+	if (tcs->flags & SGX_TCS_DBGOPTIN)
+		return -EINVAL;
+
+	if (!sgx_validate_offset(encl, tcs->ssa_offset))
+		return -EINVAL;
+
+	if (!sgx_validate_offset(encl, tcs->fs_offset))
+		return -EINVAL;
+
+	if (!sgx_validate_offset(encl, tcs->gs_offset))
+		return -EINVAL;
+
+	if ((tcs->fs_limit & 0xFFF) != 0xFFF)
+		return -EINVAL;
+
+	if ((tcs->gs_limit & 0xFFF) != 0xFFF)
+		return -EINVAL;
+
+	for (i = 0; i < SGX_TCS_RESERVED_SIZE; i++)
+		if (tcs->reserved[i])
+			return -EINVAL;
+
+	return 0;
+}
+
+static int __sgx_encl_add_page(struct sgx_encl *encl,
+			       struct sgx_encl_page *encl_page,
+			       void *data,
+			       struct sgx_secinfo *secinfo,
+			       unsigned int mrmask)
+{
+	u64 page_type = secinfo->flags & SGX_SECINFO_PAGE_TYPE_MASK;
+	struct sgx_add_page_req *req = NULL;
+	pgoff_t backing_index;
+	struct page *backing;
+	void *backing_ptr;
+	int empty;
+
+	req = kzalloc(sizeof(*req), GFP_KERNEL);
+	if (!req)
+		return -ENOMEM;
+
+	backing_index = SGX_ENCL_PAGE_BACKING_INDEX(encl_page, encl);
+	backing = sgx_get_backing(encl->backing, backing_index);
+	if (IS_ERR(backing)) {
+		kfree(req);
+		return PTR_ERR(backing);
+	}
+	backing_ptr = kmap(backing);
+	memcpy(backing_ptr, data, PAGE_SIZE);
+	kunmap(backing);
+	if (page_type == SGX_SECINFO_TCS)
+		encl_page->desc |= SGX_ENCL_PAGE_TCS;
+	memcpy(&req->secinfo, secinfo, sizeof(*secinfo));
+	req->encl = encl;
+	req->encl_page = encl_page;
+	req->mrmask = mrmask;
+	empty = list_empty(&encl->add_page_reqs);
+	kref_get(&encl->refcount);
+	list_add_tail(&req->list, &encl->add_page_reqs);
+	if (empty)
+		queue_work(sgx_add_page_wq, &encl->add_page_work);
+	sgx_put_backing(backing, true /* write */);
+	return 0;
+}
+
+/**
+ * sgx_encl_alloc_page - allocate a new enclave page
+ * @encl:	an enclave
+ * @addr:	page address in the ELRANGE
+ *
+ * Return:
+ *   an &sgx_encl_page instance on success,
+ *   -errno otherwise
+ */
+struct sgx_encl_page *sgx_encl_alloc_page(struct sgx_encl *encl,
+					  unsigned long addr)
+{
+	struct sgx_encl_page *encl_page;
+	int ret;
+
+	if (radix_tree_lookup(&encl->page_tree, PFN_DOWN(addr)))
+		return ERR_PTR(-EEXIST);
+	encl_page = kzalloc(sizeof(*encl_page), GFP_KERNEL);
+	if (!encl_page)
+		return ERR_PTR(-ENOMEM);
+	encl_page->desc = addr;
+	encl_page->impl.ops = &sgx_encl_page_ops;
+	encl_page->encl = encl;
+	ret = radix_tree_insert(&encl->page_tree, PFN_DOWN(encl_page->desc),
+				encl_page);
+	if (ret) {
+		kfree(encl_page);
+		return ERR_PTR(ret);
+	}
+	return encl_page;
+}
+
+/**
+ * sgx_encl_free_page - free an enclave page
+ * @encl_page:	an enclave page
+ */
+void sgx_encl_free_page(struct sgx_encl_page *encl_page)
+{
+	radix_tree_delete(&encl_page->encl->page_tree,
+			  PFN_DOWN(encl_page->desc));
+	if (encl_page->desc & SGX_ENCL_PAGE_LOADED) {
+		WARN_ON(encl_page->desc & SGX_ENCL_PAGE_RECLAIMED);
+		sgx_free_page(encl_page->epc_page);
+	}
+	kfree(encl_page);
+}
+
+/**
+ * sgx_encl_add_page - add a page to the enclave
+ *
+ * @encl:	an enclave
+ * @addr:	page address in the ELRANGE
+ * @data:	page data
+ * @secinfo:	page permissions
+ * @mrmask:	bitmask to select the 256 byte chunks to be measured
+ *
+ * Creates a new enclave page and enqueues an EADD operation that will be
+ * processed by a worker thread later on.
+ *
+ * Return:
+ *   0 on success,
+ *   -errno otherwise
+ */
+int sgx_encl_add_page(struct sgx_encl *encl, unsigned long addr, void *data,
+		      struct sgx_secinfo *secinfo, unsigned int mrmask)
+{
+	u64 page_type = secinfo->flags & SGX_SECINFO_PAGE_TYPE_MASK;
+	struct sgx_encl_page *encl_page;
+	int ret;
+
+	if (sgx_validate_secinfo(secinfo))
+		return -EINVAL;
+	if (page_type == SGX_SECINFO_TCS) {
+		ret = sgx_validate_tcs(encl, data);
+		if (ret)
+			return ret;
+	}
+	ret = sgx_encl_grow(encl);
+	if (ret)
+		return ret;
+	mutex_lock(&encl->lock);
+	if (encl->flags & (SGX_ENCL_INITIALIZED | SGX_ENCL_DEAD)) {
+		mutex_unlock(&encl->lock);
+		return -EINVAL;
+	}
+	encl_page = sgx_encl_alloc_page(encl, addr);
+	if (IS_ERR(encl_page)) {
+		mutex_unlock(&encl->lock);
+		return PTR_ERR(encl_page);
+	}
+	ret = __sgx_encl_add_page(encl, encl_page, data, secinfo, mrmask);
+	if (ret)
+		sgx_encl_free_page(encl_page);
+	mutex_unlock(&encl->lock);
+	return ret;
+}
+
+static int __sgx_get_key_hash(struct crypto_shash *tfm, const void *modulus,
+			      void *hash)
+{
+	SHASH_DESC_ON_STACK(shash, tfm);
+
+	shash->tfm = tfm;
+	shash->flags = CRYPTO_TFM_REQ_MAY_SLEEP;
+
+	return crypto_shash_digest(shash, modulus, SGX_MODULUS_SIZE, hash);
+}
+
+static int sgx_get_key_hash(const void *modulus, void *hash)
+{
+	struct crypto_shash *tfm;
+	int ret;
+
+	tfm = crypto_alloc_shash("sha256", 0, CRYPTO_ALG_ASYNC);
+	if (IS_ERR(tfm))
+		return PTR_ERR(tfm);
+
+	ret = __sgx_get_key_hash(tfm, modulus, hash);
+
+	crypto_free_shash(tfm);
+	return ret;
+}
+
+/**
+ * sgx_encl_init - perform EINIT for the given enclave
+ *
+ * @encl:	an enclave
+ * @sigstruct:	SIGSTRUCT for the enclave
+ * @token:	EINITTOKEN for the enclave
+ *
+ * Retries a few times in order to perform EINIT operation on an enclave
+ * because there could be potentially an interrupt storm.
+ *
+ * Return:
+ *   0 on success,
+ *   SGX error code on EINIT failure,
+ *   -errno otherwise
+ */
+int sgx_encl_init(struct sgx_encl *encl, struct sgx_sigstruct *sigstruct,
+		  struct sgx_einittoken *token)
+{
+	u64 mrsigner[4];
+	int ret;
+	int i;
+	int j;
+
+	ret = sgx_get_key_hash(sigstruct->modulus, mrsigner);
+	if (ret)
+		return ret;
+
+	flush_work(&encl->add_page_work);
+
+	mutex_lock(&encl->lock);
+
+	if (encl->flags & SGX_ENCL_INITIALIZED) {
+		mutex_unlock(&encl->lock);
+		return 0;
+	}
+	if (encl->flags & SGX_ENCL_DEAD) {
+		mutex_unlock(&encl->lock);
+		return -EFAULT;
+	}
+
+	for (i = 0; i < SGX_EINIT_SLEEP_COUNT; i++) {
+		for (j = 0; j < SGX_EINIT_SPIN_COUNT; j++) {
+			ret = sgx_einit(sigstruct, token, encl->secs.epc_page,
+					mrsigner);
+			if (ret == SGX_UNMASKED_EVENT)
+				continue;
+			else
+				break;
+		}
+
+		if (ret != SGX_UNMASKED_EVENT)
+			break;
+
+		msleep_interruptible(SGX_EINIT_SLEEP_TIME);
+		if (signal_pending(current)) {
+			mutex_unlock(&encl->lock);
+			return -ERESTARTSYS;
+		}
+	}
+
+	if (ret > 0)
+		sgx_dbg(encl, "EINIT returned %d\n", ret);
+	else if (!ret)
+		encl->flags |= SGX_ENCL_INITIALIZED;
+	mutex_unlock(&encl->lock);
+
+	return ret;
+}
+
+/**
+ * sgx_encl_block - block an enclave page
+ * @encl_page:	an enclave page
+ *
+ * Changes the state of the associated EPC page to blocked.
+ */
+void sgx_encl_block(struct sgx_encl_page *encl_page)
+{
+	unsigned long addr = SGX_ENCL_PAGE_ADDR(encl_page);
+	struct sgx_encl *encl = encl_page->encl;
+	struct vm_area_struct *vma;
+	int ret;
+
+	if (encl->flags & SGX_ENCL_DEAD)
+		return;
+
+	ret = sgx_encl_find(encl->mm, addr, &vma);
+	if (ret || encl != vma->vm_private_data)
+		return;
+
+	zap_vma_ptes(vma, addr, PAGE_SIZE);
+	ret = __eblock(sgx_epc_addr(encl_page->epc_page));
+	SGX_INVD(ret, encl, "EBLOCK returned %d (0x%x)", ret, ret);
+}
+
+/**
+ * sgx_encl_track - start tracking pages in the blocked state
+ * @encl:	an enclave
+ *
+ * Start blocking accesses for pages in the blocked state for threads that enter
+ * inside the enclave by executing the ETRACK leaf instruction. This starts a
+ * shootdown sequence for threads that entered before ETRACK.
+ *
+ * The caller must take care (with an IPI when necessary) to make sure that the
+ * previous shootdown sequence was completed before calling this function.  If
+ * this is not the case, the callee prints a critical error to the klog and
+ * kills the enclave.
+ */
+void sgx_encl_track(struct sgx_encl *encl)
+{
+	int ret = __etrack(sgx_epc_addr(encl->secs.epc_page));
+
+	SGX_INVD(ret, encl, "ETRACK returned %d\n", ret);
+}
+
+/**
+ * sgx_encl_load_page - load an enclave page
+ * @encl_page:	a &sgx_encl_page
+ * @epc_page:	a &sgx_epc_page
+ *
+ * Loads an enclave page from the regular memory to the EPC. The pages, which
+ * are not children of a SECS (eg SECS itself and VA pages) should set their
+ * address to zero.
+ */
+int sgx_encl_load_page(struct sgx_encl_page *encl_page,
+		       struct sgx_epc_page *epc_page)
+{
+	unsigned long addr = SGX_ENCL_PAGE_ADDR(encl_page);
+	struct sgx_encl *encl = encl_page->encl;
+	struct sgx_pageinfo pginfo;
+	unsigned long pcmd_offset;
+	unsigned long va_offset;
+	pgoff_t backing_index;
+	struct page *backing;
+	struct page *pcmd;
+	void *va_ptr;
+	int ret;
+
+	backing_index = SGX_ENCL_PAGE_BACKING_INDEX(encl_page, encl);
+	pcmd_offset = SGX_ENCL_PAGE_PCMD_OFFSET(encl_page, encl);
+	va_offset = SGX_ENCL_PAGE_VA_OFFSET(encl_page);
+
+	backing = sgx_get_backing(encl->backing, backing_index);
+	if (IS_ERR(backing))
+		return PTR_ERR(backing);
+
+	pcmd = sgx_get_backing(encl->pcmd, backing_index >> 5);
+	if (IS_ERR(pcmd)) {
+		sgx_put_backing(backing, false);
+		return PTR_ERR(pcmd);
+	}
+
+
+	va_ptr = sgx_epc_addr(encl_page->va_page->epc_page) + va_offset;
+
+	pginfo.addr = addr;
+	pginfo.contents = (unsigned long)kmap_atomic(backing);
+	pginfo.metadata = (unsigned long)kmap_atomic(pcmd) + pcmd_offset;
+	pginfo.secs = addr ? (unsigned long)sgx_epc_addr(encl->secs.epc_page) :
+		      0;
+
+	ret = __eldu(&pginfo, sgx_epc_addr(epc_page), va_ptr);
+	if (ret) {
+		sgx_err(encl, "ELDU returned %d\n", ret);
+		ret = encls_to_err(ret);
+	}
+
+	kunmap_atomic((void *)(unsigned long)(pginfo.metadata - pcmd_offset));
+	kunmap_atomic((void *)(unsigned long)pginfo.contents);
+
+	sgx_put_backing(pcmd, false);
+	sgx_put_backing(backing, false);
+	return ret;
+}
+
+/**
+ * sgx_encl_release - destroy an enclave instance
+ *
+ * @kref:	address of a kref inside &sgx_encl
+ *
+ * Used together with kref_put(). Frees all the resources associated with the
+ * enclave and the instance itself.
+ */
+void sgx_encl_release(struct kref *ref)
+{
+	struct sgx_encl *encl = container_of(ref, struct sgx_encl, refcount);
+	struct sgx_encl_page *entry;
+	struct radix_tree_iter iter;
+	struct sgx_va_page *va_page;
+	void **slot;
+
+	if (encl->mmu_notifier.ops) {
+		mmu_notifier_unregister_no_release(&encl->mmu_notifier,
+						   encl->mm);
+		encl->mmu_notifier.ops = NULL;
+	}
+
+	if (encl->pm_notifier.notifier_call) {
+		unregister_pm_notifier(&encl->pm_notifier);
+		encl->pm_notifier.notifier_call = NULL;
+	}
+
+	radix_tree_for_each_slot(slot, &encl->page_tree, &iter, 0) {
+		entry = *slot;
+		sgx_encl_free_page(entry);
+	}
+
+	if (encl->tgid) {
+		put_pid(encl->tgid);
+		encl->tgid = NULL;
+	}
+
+	while (!list_empty(&encl->va_pages)) {
+		va_page = list_first_entry(&encl->va_pages, struct sgx_va_page,
+					   list);
+		list_del(&va_page->list);
+		sgx_free_page(va_page->epc_page);
+		kfree(va_page);
+	}
+
+	if (encl->secs.desc & SGX_ENCL_PAGE_LOADED)
+		sgx_free_page(encl->secs.epc_page);
+
+	if (encl->backing) {
+		fput(encl->backing);
+		encl->backing = NULL;
+	}
+
+	if (encl->pcmd) {
+		fput(encl->pcmd);
+		encl->pcmd = NULL;
+	}
+
+	kfree(encl);
+}
diff --git a/drivers/platform/x86/intel_sgx/sgx_encl_page.c b/drivers/platform/x86/intel_sgx/sgx_encl_page.c
new file mode 100644
index 000000000000..fe52fb90d42b
--- /dev/null
+++ b/drivers/platform/x86/intel_sgx/sgx_encl_page.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-18 Intel Corporation.
+
+#include <linux/device.h>
+#include <linux/freezer.h>
+#include <linux/highmem.h>
+#include <linux/kthread.h>
+#include <linux/ratelimit.h>
+#include <linux/sched/signal.h>
+#include <linux/slab.h>
+#include "sgx.h"
+
+static inline struct sgx_encl_page *to_encl_page(struct sgx_epc_page *epc_page)
+{
+	return container_of(epc_page->impl, struct sgx_encl_page, impl);
+}
+
+static bool sgx_encl_page_get(struct sgx_epc_page *epc_page)
+{
+	struct sgx_encl_page *encl_page = to_encl_page(epc_page);
+	struct sgx_encl *encl = encl_page->encl;
+
+	return kref_get_unless_zero(&encl->refcount) != 0;
+}
+
+static void sgx_encl_page_put(struct sgx_epc_page *epc_page)
+{
+	struct sgx_encl_page *encl_page = to_encl_page(epc_page);
+	struct sgx_encl *encl = encl_page->encl;
+
+	kref_put(&encl->refcount, sgx_encl_release);
+}
+
+static bool sgx_encl_page_reclaim(struct sgx_epc_page *epc_page)
+{
+	struct sgx_encl_page *encl_page = to_encl_page(epc_page);
+	struct sgx_encl *encl = encl_page->encl;
+	bool ret;
+
+	down_read(&encl->mm->mmap_sem);
+	mutex_lock(&encl->lock);
+	/*
+	 * There's a small window between the EPC manager pulling the
+	 * page off the active list and calling reclaim(), during which
+	 * we can free the page, e.g. via sgx_invalidate().  Check the
+	 * LOADED flag to ensure the page is still resident in the EPC.
+	 */
+	if (!(encl_page->desc & SGX_ENCL_PAGE_LOADED))
+		ret = false;
+	else if (encl->flags & SGX_ENCL_DEAD)
+		ret = true;
+	else if (encl_page->desc & SGX_ENCL_PAGE_RESERVED)
+		ret = false;
+	else
+		ret = !sgx_test_and_clear_young(encl_page);
+	if (ret)
+		encl_page->desc |= SGX_ENCL_PAGE_RECLAIMED;
+	mutex_unlock(&encl->lock);
+	up_read(&encl->mm->mmap_sem);
+
+	return ret;
+}
+
+static void sgx_encl_page_block(struct sgx_epc_page *epc_page)
+{
+	struct sgx_encl_page *encl_page = to_encl_page(epc_page);
+	struct sgx_encl *encl = encl_page->encl;
+
+	down_read(&encl->mm->mmap_sem);
+	mutex_lock(&encl->lock);
+	sgx_encl_block(encl_page);
+	mutex_unlock(&encl->lock);
+	up_read(&encl->mm->mmap_sem);
+}
+
+static int sgx_ewb(struct sgx_encl *encl, struct sgx_epc_page *epc_page,
+		   struct sgx_va_page *va_page, unsigned int va_offset)
+{
+	struct sgx_encl_page *encl_page = to_encl_page(epc_page);
+	unsigned long pcmd_offset = SGX_ENCL_PAGE_PCMD_OFFSET(encl_page, encl);
+	struct sgx_pageinfo pginfo;
+	pgoff_t backing_index;
+	struct page *backing;
+	struct page *pcmd;
+	void *va;
+	int ret;
+
+	backing_index = SGX_ENCL_PAGE_BACKING_INDEX(encl_page, encl);
+
+	backing = sgx_get_backing(encl->backing, backing_index);
+	if (IS_ERR(backing)) {
+		ret = PTR_ERR(backing);
+		return ret;
+	}
+
+	pcmd = sgx_get_backing(encl->pcmd, backing_index >> 5);
+	if (IS_ERR(pcmd)) {
+		ret = PTR_ERR(pcmd);
+		sgx_put_backing(backing, true);
+		return ret;
+	}
+
+	va = sgx_epc_addr(va_page->epc_page) + va_offset;
+
+	pginfo.addr = 0;
+	pginfo.contents = (unsigned long)kmap_atomic(backing);
+	pginfo.metadata = (unsigned long)kmap_atomic(pcmd) + pcmd_offset;
+	pginfo.secs = 0;
+	ret = __ewb(&pginfo, sgx_epc_addr(epc_page), va);
+	kunmap_atomic((void *)(unsigned long)(pginfo.metadata - pcmd_offset));
+	kunmap_atomic((void *)(unsigned long)pginfo.contents);
+
+	sgx_put_backing(pcmd, true);
+	sgx_put_backing(backing, true);
+
+	return ret;
+}
+
+/**
+ * sgx_write_page - write a page to the regular memory
+ *
+ * Writes an EPC page to the shmem file associated with the enclave. Flushes
+ * CPUs and retries if there are hardware threads that can potentially have TLB
+ * entries to the page (indicated by SGX_NOT_TRACKED). Clears the reserved flag
+ * after the page is swapped.
+ *
+ * @epc_page:	an EPC page
+ */
+static void sgx_write_page(struct sgx_epc_page *epc_page, bool do_free)
+{
+	struct sgx_encl_page *encl_page = to_encl_page(epc_page);
+	struct sgx_encl *encl = encl_page->encl;
+	struct sgx_va_page *va_page;
+	unsigned int va_offset;
+	int ret;
+
+	encl_page->desc &= ~(SGX_ENCL_PAGE_LOADED | SGX_ENCL_PAGE_RECLAIMED);
+
+	if (!(encl->flags & SGX_ENCL_DEAD)) {
+		va_page = list_first_entry(&encl->va_pages, struct sgx_va_page,
+					   list);
+		va_offset = sgx_alloc_va_slot(va_page);
+		if (sgx_va_page_full(va_page))
+			list_move_tail(&va_page->list, &encl->va_pages);
+
+		ret = sgx_ewb(encl, epc_page, va_page, va_offset);
+		if (ret == SGX_NOT_TRACKED) {
+			sgx_encl_track(encl);
+			ret = sgx_ewb(encl, epc_page, va_page, va_offset);
+			if (ret == SGX_NOT_TRACKED) {
+				/* slow path, IPI needed */
+				sgx_flush_cpus(encl);
+				ret = sgx_ewb(encl, epc_page, va_page,
+					      va_offset);
+			}
+		}
+		SGX_INVD(ret, encl, "EWB returned %d\n", ret);
+
+		SGX_INVD(encl_page->desc & SGX_ENCL_PAGE_VA_OFFSET_MASK, encl,
+			"Flags set in VA offset area: %lx", encl_page->desc);
+		encl_page->desc |= va_offset;
+		encl_page->va_page = va_page;
+	} else if (!do_free) {
+		ret = __eremove(sgx_epc_addr(epc_page));
+		WARN(ret, "EREMOVE returned %d\n", ret);
+	}
+
+	if (do_free)
+		sgx_free_page(epc_page);
+}
+
+static void sgx_encl_page_write(struct sgx_epc_page *epc_page)
+{
+	struct sgx_encl_page *encl_page = to_encl_page(epc_page);
+	struct sgx_encl *encl = encl_page->encl;
+
+	down_read(&encl->mm->mmap_sem);
+	mutex_lock(&encl->lock);
+	sgx_write_page(epc_page, false);
+	encl->secs_child_cnt--;
+	if (!encl->secs_child_cnt && (encl->flags & SGX_ENCL_INITIALIZED))
+		sgx_write_page(encl->secs.epc_page, true);
+	mutex_unlock(&encl->lock);
+	up_read(&encl->mm->mmap_sem);
+}
+
+const struct sgx_epc_page_ops sgx_encl_page_ops = {
+	.get = sgx_encl_page_get,
+	.put = sgx_encl_page_put,
+	.reclaim = sgx_encl_page_reclaim,
+	.block = sgx_encl_page_block,
+	.write = sgx_encl_page_write,
+};
+
+/**
+ * sgx_set_epc_page - associate an EPC page with an enclave page
+ * @encl_page:	an enclave page
+ * @epc_page:	the EPC page to attach to @encl_page
+ */
+void sgx_set_epc_page(struct sgx_encl_page *encl_page,
+		      struct sgx_epc_page *epc_page)
+{
+	encl_page->desc |= SGX_ENCL_PAGE_LOADED;
+	encl_page->epc_page = epc_page;
+}
+
+/**
+ * sgx_set_page_reclaimable - mark an EPC page reclaimable
+ * @encl_page:	an enclave page with a loaded EPC page
+ */
+void sgx_set_page_reclaimable(struct sgx_encl_page *encl_page)
+{
+	sgx_test_and_clear_young(encl_page);
+
+	sgx_page_reclaimable(encl_page->epc_page);
+}
+
+/**
+ * sgx_alloc_page - allocate a VA page
+ * @flags:	allocation flags
+ *
+ * Allocates an &sgx_epc_page instance and converts it to a VA page.
+ *
+ * Return:
+ *   a &struct sgx_va_page instance,
+ *   -errno otherwise
+ */
+struct sgx_epc_page *sgx_alloc_va_page(unsigned int flags)
+{
+	struct sgx_epc_page *epc_page;
+	int ret;
+
+	epc_page = sgx_alloc_page(NULL, flags);
+	if (IS_ERR(epc_page))
+		return (void *)epc_page;
+
+	ret = __epa(sgx_epc_addr(epc_page));
+	if (ret) {
+		pr_crit("EPA failed\n");
+		sgx_free_page(epc_page);
+		return ERR_PTR(ret);
+	}
+
+	return epc_page;
+}
+
+/**
+ * sgx_alloc_va_slot - allocate a VA slot
+ * @va_page:	a &struct sgx_va_page instance
+ *
+ * Allocates a slot from a &struct sgx_va_page instance.
+ *
+ * Return: offset of the slot inside the VA page
+ */
+unsigned int sgx_alloc_va_slot(struct sgx_va_page *va_page)
+{
+	int slot = find_first_zero_bit(va_page->slots, SGX_VA_SLOT_COUNT);
+
+	if (slot < SGX_VA_SLOT_COUNT)
+		set_bit(slot, va_page->slots);
+
+	return slot << 3;
+}
+
+/**
+ * sgx_free_va_slot - free a VA slot
+ * @va_page:	a &struct sgx_va_page instance
+ * @offset:	offset of the slot inside the VA page
+ *
+ * Frees a slot from a &struct sgx_va_page instance.
+ */
+void sgx_free_va_slot(struct sgx_va_page *va_page, unsigned int offset)
+{
+	clear_bit(offset >> 3, va_page->slots);
+}
+
+/**
+ * sgx_va_page_full - is the VA page full?
+ * @va_page:	a &struct sgx_va_page instance
+ *
+ * Return: true if all slots have been taken
+ */
+bool sgx_va_page_full(struct sgx_va_page *va_page)
+{
+	int slot = find_first_zero_bit(va_page->slots, SGX_VA_SLOT_COUNT);
+
+	return slot == SGX_VA_SLOT_COUNT;
+}
diff --git a/drivers/platform/x86/intel_sgx/sgx_fault.c b/drivers/platform/x86/intel_sgx/sgx_fault.c
new file mode 100644
index 000000000000..dc50b6e391f4
--- /dev/null
+++ b/drivers/platform/x86/intel_sgx/sgx_fault.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-18 Intel Corporation.
+
+#include <linux/highmem.h>
+#include <linux/sched/mm.h>
+#include "sgx.h"
+
+static int sgx_test_and_clear_young_cb(pte_t *ptep, pgtable_t token,
+				       unsigned long addr, void *data)
+{
+	pte_t pte;
+	int ret;
+
+	ret = pte_young(*ptep);
+	if (ret) {
+		pte = pte_mkold(*ptep);
+		set_pte_at((struct mm_struct *)data, addr, ptep, pte);
+	}
+
+	return ret;
+}
+
+/**
+ * sgx_test_and_clear_young() - Test and reset the accessed bit
+ * @page:	enclave page to be tested for recent access
+ *
+ * Checks the Access (A) bit from the PTE corresponding to the
+ * enclave page and clears it.  Returns 1 if the page has been
+ * recently accessed and 0 if not.
+ */
+int sgx_test_and_clear_young(struct sgx_encl_page *page)
+{
+	unsigned long addr = SGX_ENCL_PAGE_ADDR(page);
+	struct sgx_encl *encl = page->encl;
+	struct vm_area_struct *vma;
+	int ret;
+
+	ret = sgx_encl_find(encl->mm, addr, &vma);
+	if (ret)
+		return 0;
+
+	if (encl != vma->vm_private_data)
+		return 0;
+
+	return apply_to_page_range(vma->vm_mm, addr, PAGE_SIZE,
+				   sgx_test_and_clear_young_cb, vma->vm_mm);
+}
+
+static void sgx_ipi_cb(void *info)
+{
+}
+
+void sgx_flush_cpus(struct sgx_encl *encl)
+{
+	on_each_cpu_mask(mm_cpumask(encl->mm), sgx_ipi_cb, NULL, 1);
+}
+
+static struct sgx_epc_page *__sgx_load_faulted_page(
+	struct sgx_encl_page *encl_page)
+{
+	unsigned long va_offset = SGX_ENCL_PAGE_VA_OFFSET(encl_page);
+	struct sgx_encl *encl = encl_page->encl;
+	struct sgx_epc_page *epc_page;
+	int ret;
+
+	epc_page = sgx_alloc_page(&encl_page->impl, SGX_ALLOC_ATOMIC);
+	if (IS_ERR(epc_page))
+		return epc_page;
+	ret = sgx_encl_load_page(encl_page, epc_page);
+	if (ret) {
+		sgx_free_page(epc_page);
+		return ERR_PTR(ret);
+	}
+	sgx_free_va_slot(encl_page->va_page, va_offset);
+	list_move(&encl_page->va_page->list, &encl->va_pages);
+	encl_page->desc &= ~SGX_ENCL_PAGE_VA_OFFSET_MASK;
+	sgx_set_epc_page(encl_page, epc_page);
+	return epc_page;
+}
+
+static struct sgx_encl_page *__sgx_fault_page(struct vm_area_struct *vma,
+					      unsigned long addr,
+					      bool do_reserve)
+{
+	struct sgx_encl *encl = vma->vm_private_data;
+	struct sgx_epc_page *epc_page;
+	struct sgx_encl_page *entry;
+	int rc = 0;
+
+	if ((encl->flags & SGX_ENCL_DEAD) ||
+	    !(encl->flags & SGX_ENCL_INITIALIZED))
+		return ERR_PTR(-EFAULT);
+
+	entry = radix_tree_lookup(&encl->page_tree, addr >> PAGE_SHIFT);
+	if (!entry)
+		return ERR_PTR(-EFAULT);
+
+	/* Page is already resident in the EPC. */
+	if (entry->desc & SGX_ENCL_PAGE_LOADED) {
+		if (entry->desc & SGX_ENCL_PAGE_RESERVED) {
+			sgx_dbg(encl, "EPC page 0x%p is already reserved\n",
+				(void *)SGX_ENCL_PAGE_ADDR(entry));
+			return ERR_PTR(-EBUSY);
+		}
+		if (entry->desc & SGX_ENCL_PAGE_RECLAIMED) {
+			sgx_dbg(encl, "EPC page 0x%p is being reclaimed\n",
+				(void *)SGX_ENCL_PAGE_ADDR(entry));
+			return ERR_PTR(-EBUSY);
+		}
+		if (do_reserve)
+			entry->desc |= SGX_ENCL_PAGE_RESERVED;
+		return entry;
+	}
+
+	if (!(encl->secs.desc & SGX_ENCL_PAGE_LOADED)) {
+		epc_page = __sgx_load_faulted_page(&encl->secs);
+		if (IS_ERR(epc_page))
+			return (void *)epc_page;
+	}
+	epc_page = __sgx_load_faulted_page(entry);
+	if (IS_ERR(epc_page))
+		return (void *)epc_page;
+
+	encl->secs_child_cnt++;
+	sgx_set_page_reclaimable(entry);
+	if (do_reserve)
+		entry->desc |= SGX_ENCL_PAGE_RESERVED;
+
+	rc = vm_insert_pfn(vma, addr, PFN_DOWN(entry->epc_page->desc));
+	SGX_INVD(rc, encl, "%s: vm_insert_pfn() returned %d\n", __func__, rc);
+	if (rc)
+		return ERR_PTR(rc);
+
+	return entry;
+}
+
+struct sgx_encl_page *sgx_fault_page(struct vm_area_struct *vma,
+				     unsigned long addr, bool do_reserve)
+{
+	struct sgx_encl *encl = vma->vm_private_data;
+	struct sgx_encl_page *entry;
+
+	/* If process was forked, VMA is still there but vm_private_data is set
+	 * to NULL.
+	 */
+	if (!encl)
+		return ERR_PTR(-EFAULT);
+	do {
+		mutex_lock(&encl->lock);
+		entry = __sgx_fault_page(vma, addr, do_reserve);
+		mutex_unlock(&encl->lock);
+		if (!do_reserve)
+			break;
+	} while (PTR_ERR(entry) == -EBUSY);
+
+	return entry;
+}
diff --git a/drivers/platform/x86/intel_sgx/sgx_ioctl.c b/drivers/platform/x86/intel_sgx/sgx_ioctl.c
new file mode 100644
index 000000000000..4edf1cc956b1
--- /dev/null
+++ b/drivers/platform/x86/intel_sgx/sgx_ioctl.c
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-18 Intel Corporation.
+
+#include <asm/mman.h>
+#include <linux/delay.h>
+#include <linux/file.h>
+#include <linux/hashtable.h>
+#include <linux/highmem.h>
+#include <linux/ratelimit.h>
+#include <linux/sched/signal.h>
+#include <linux/slab.h>
+#include "sgx.h"
+
+static int sgx_encl_get(unsigned long addr, struct sgx_encl **encl)
+{
+	struct mm_struct *mm = current->mm;
+	struct vm_area_struct *vma;
+	int ret;
+
+	if (addr & (PAGE_SIZE - 1))
+		return -EINVAL;
+
+	down_read(&mm->mmap_sem);
+
+	ret = sgx_encl_find(mm, addr, &vma);
+	if (!ret) {
+		*encl = vma->vm_private_data;
+
+		if ((*encl)->flags & SGX_ENCL_SUSPEND)
+			ret = SGX_POWER_LOST_ENCLAVE;
+		else
+			kref_get(&(*encl)->refcount);
+	}
+
+	up_read(&mm->mmap_sem);
+	return ret;
+}
+
+/**
+ * sgx_ioc_enclave_create - handler for %SGX_IOC_ENCLAVE_CREATE
+ * @filep:	open file to /dev/sgx
+ * @cmd:	the command value
+ * @arg:	pointer to an &sgx_enclave_create instance
+ *
+ * Validates SECS attributes, allocates an EPC page for the SECS and performs
+ * ECREATE.
+ *
+ * Return:
+ *   0 on success,
+ *   -errno otherwise
+ */
+static long sgx_ioc_enclave_create(struct file *filep, unsigned int cmd,
+				   unsigned long arg)
+{
+	struct sgx_enclave_create *createp = (struct sgx_enclave_create *)arg;
+	struct page *secs_page;
+	struct sgx_secs *secs;
+	struct sgx_encl *encl;
+	int ret;
+
+	secs_page = alloc_page(GFP_HIGHUSER);
+	if (!secs_page)
+		return -ENOMEM;
+
+	secs = kmap(secs_page);
+	ret = copy_from_user(secs, (void __user *)createp->src, sizeof(*secs));
+	if (ret)
+		goto out;
+
+	encl = sgx_encl_alloc(secs);
+	if (IS_ERR(encl)) {
+		ret = PTR_ERR(encl);
+		goto out;
+	}
+
+	ret = sgx_encl_create(encl, secs);
+	if (ret)
+		kref_put(&encl->refcount, sgx_encl_release);
+
+out:
+	kunmap(secs_page);
+	__free_page(secs_page);
+	return ret;
+}
+
+/**
+ * sgx_ioc_enclave_add_page - handler for %SGX_IOC_ENCLAVE_ADD_PAGE
+ *
+ * @filep:	open file to /dev/sgx
+ * @cmd:	the command value
+ * @arg:	pointer to an &sgx_enclave_add_page instance
+ *
+ * Creates a new enclave page and enqueues an EADD operation that will be
+ * processed by a worker thread later on.
+ *
+ * Return:
+ *   0 on success,
+ *   -errno otherwise
+ */
+static long sgx_ioc_enclave_add_page(struct file *filep, unsigned int cmd,
+				     unsigned long arg)
+{
+	struct sgx_enclave_add_page *addp = (void *)arg;
+	struct sgx_secinfo secinfo;
+	struct sgx_encl *encl;
+	struct page *data_page;
+	void *data;
+	int ret;
+
+	ret = sgx_encl_get(addp->addr, &encl);
+	if (ret)
+		return ret;
+
+	if (copy_from_user(&secinfo, (void __user *)addp->secinfo,
+			   sizeof(secinfo))) {
+		kref_put(&encl->refcount, sgx_encl_release);
+		return -EFAULT;
+	}
+
+	data_page = alloc_page(GFP_HIGHUSER);
+	if (!data_page) {
+		kref_put(&encl->refcount, sgx_encl_release);
+		return -ENOMEM;
+	}
+
+	data = kmap(data_page);
+
+	ret = copy_from_user((void *)data, (void __user *)addp->src, PAGE_SIZE);
+	if (ret)
+		goto out;
+
+	ret = sgx_encl_add_page(encl, addp->addr, data, &secinfo, addp->mrmask);
+	if (ret)
+		goto out;
+
+out:
+	kref_put(&encl->refcount, sgx_encl_release);
+	kunmap(data_page);
+	__free_page(data_page);
+	return ret;
+}
+
+/**
+ * sgx_ioc_enclave_init - handler for %SGX_IOC_ENCLAVE_INIT
+ *
+ * @filep:	open file to /dev/sgx
+ * @cmd:	the command value
+ * @arg:	pointer to an &sgx_enclave_init instance
+ *
+ * Flushes the remaining enqueued EADD operations and performs EINIT. Does not
+ * allow the EINITTOKENKEY attribute for an enclave.
+ *
+ * Return:
+ *   0 on success,
+ *   SGX error code on EINIT failure,
+ *   -errno otherwise
+ */
+static long sgx_ioc_enclave_init(struct file *filep, unsigned int cmd,
+				 unsigned long arg)
+{
+	struct sgx_enclave_init *initp = (struct sgx_enclave_init *)arg;
+	struct sgx_sigstruct *sigstruct;
+	struct sgx_einittoken *einittoken;
+	struct sgx_encl *encl;
+	struct page *initp_page;
+	int ret;
+
+	initp_page = alloc_page(GFP_HIGHUSER);
+	if (!initp_page)
+		return -ENOMEM;
+
+	sigstruct = kmap(initp_page);
+	einittoken = (struct sgx_einittoken *)
+		((unsigned long)sigstruct + PAGE_SIZE / 2);
+	memset(einittoken, 0, sizeof(*einittoken));
+
+	ret = copy_from_user(sigstruct, (void __user *)initp->sigstruct,
+			     sizeof(*sigstruct));
+	if (ret)
+		goto out;
+	if (sigstruct->attributes & SGX_ATTR_EINITTOKENKEY) {
+		ret = EINVAL;
+		goto out;
+	}
+
+	ret = sgx_encl_get(initp->addr, &encl);
+	if (ret)
+		goto out;
+
+	ret = sgx_encl_init(encl, sigstruct, einittoken);
+
+	kref_put(&encl->refcount, sgx_encl_release);
+
+out:
+	kunmap(initp_page);
+	__free_page(initp_page);
+	return ret;
+}
+
+typedef long (*sgx_ioc_t)(struct file *filep, unsigned int cmd,
+			  unsigned long arg);
+
+long sgx_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
+{
+	char data[256];
+	sgx_ioc_t handler = NULL;
+	long ret;
+
+	switch (cmd) {
+	case SGX_IOC_ENCLAVE_CREATE:
+		handler = sgx_ioc_enclave_create;
+		break;
+	case SGX_IOC_ENCLAVE_ADD_PAGE:
+		handler = sgx_ioc_enclave_add_page;
+		break;
+	case SGX_IOC_ENCLAVE_INIT:
+		handler = sgx_ioc_enclave_init;
+		break;
+	default:
+		return -ENOIOCTLCMD;
+	}
+
+	if (copy_from_user(data, (void __user *)arg, _IOC_SIZE(cmd)))
+		return -EFAULT;
+
+	ret = handler(filep, cmd, (unsigned long)((void *)data));
+	if (!ret && (cmd & IOC_OUT)) {
+		if (copy_to_user((void __user *)arg, data, _IOC_SIZE(cmd)))
+			return -EFAULT;
+	}
+	if (IS_ENCLS_FAULT(ret))
+		return -EFAULT;
+	return ret;
+}
diff --git a/drivers/platform/x86/intel_sgx/sgx_main.c b/drivers/platform/x86/intel_sgx/sgx_main.c
new file mode 100644
index 000000000000..69655f82a327
--- /dev/null
+++ b/drivers/platform/x86/intel_sgx/sgx_main.c
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-18 Intel Corporation.
+
+#include <linux/acpi.h>
+#include <linux/cdev.h>
+#include <linux/platform_device.h>
+#include <linux/suspend.h>
+#include "sgx.h"
+
+MODULE_DESCRIPTION("Intel SGX Driver");
+MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
+MODULE_LICENSE("Dual BSD/GPL");
+
+struct workqueue_struct *sgx_add_page_wq;
+u64 sgx_encl_size_max_32;
+u64 sgx_encl_size_max_64;
+u64 sgx_xfrm_mask = 0x3;
+u32 sgx_misc_reserved;
+u32 sgx_xsave_size_tbl[64];
+
+#ifdef CONFIG_COMPAT
+long sgx_compat_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
+{
+	return sgx_ioctl(filep, cmd, arg);
+}
+#endif
+
+static int sgx_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	vma->vm_ops = &sgx_vm_ops;
+	vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_IO |
+			 VM_DONTCOPY;
+
+	return 0;
+}
+
+static unsigned long sgx_get_unmapped_area(struct file *file,
+					   unsigned long addr,
+					   unsigned long len,
+					   unsigned long pgoff,
+					   unsigned long flags)
+{
+	if (len < 2 * PAGE_SIZE || (len & (len - 1)))
+		return -EINVAL;
+
+	if (len > sgx_encl_size_max_64)
+		return -EINVAL;
+
+	if (len > sgx_encl_size_max_32 && test_thread_flag(TIF_ADDR32))
+		return -EINVAL;
+
+	addr = current->mm->get_unmapped_area(file, addr, 2 * len, pgoff,
+					      flags);
+	if (IS_ERR_VALUE(addr))
+		return addr;
+
+	addr = (addr + (len - 1)) & ~(len - 1);
+
+	return addr;
+}
+
+static const struct file_operations sgx_fops = {
+	.owner			= THIS_MODULE,
+	.unlocked_ioctl		= sgx_ioctl,
+#ifdef CONFIG_COMPAT
+	.compat_ioctl		= sgx_compat_ioctl,
+#endif
+	.mmap			= sgx_mmap,
+	.get_unmapped_area	= sgx_get_unmapped_area,
+};
+
+static struct bus_type sgx_bus_type = {
+	.name	= "sgx",
+};
+
+struct sgx_context {
+	struct device dev;
+	struct cdev cdev;
+};
+
+static dev_t sgx_devt;
+
+static void sgx_dev_release(struct device *dev)
+{
+	struct sgx_context *ctx = container_of(dev, struct sgx_context, dev);
+
+	kfree(ctx);
+}
+
+static struct sgx_context *sgx_ctx_alloc(struct device *parent)
+{
+	struct sgx_context *ctx;
+
+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return ERR_PTR(-ENOMEM);
+
+	device_initialize(&ctx->dev);
+
+	ctx->dev.bus = &sgx_bus_type;
+	ctx->dev.parent = parent;
+	ctx->dev.devt = MKDEV(MAJOR(sgx_devt), 0);
+	ctx->dev.release = sgx_dev_release;
+
+	dev_set_name(&ctx->dev, "sgx");
+
+	cdev_init(&ctx->cdev, &sgx_fops);
+	ctx->cdev.owner = THIS_MODULE;
+
+	dev_set_drvdata(parent, ctx);
+
+	return ctx;
+}
+
+static struct sgx_context *sgxm_ctx_alloc(struct device *parent)
+{
+	struct sgx_context *ctx;
+	int rc;
+
+	ctx = sgx_ctx_alloc(parent);
+	if (IS_ERR(ctx))
+		return ctx;
+
+	rc = devm_add_action_or_reset(parent, (void (*)(void *))put_device,
+				      &ctx->dev);
+	if (rc) {
+		kfree(ctx);
+		return ERR_PTR(rc);
+	}
+
+	return ctx;
+}
+
+static int sgx_dev_init(struct device *parent)
+{
+	struct sgx_context *sgx_dev;
+	unsigned int eax;
+	unsigned int ebx;
+	unsigned int ecx;
+	unsigned int edx;
+	int ret;
+	int i;
+
+	sgx_dev = sgxm_ctx_alloc(parent);
+
+	cpuid_count(SGX_CPUID, 0, &eax, &ebx, &ecx, &edx);
+	/* Only allow misc bits supported by the driver. */
+	sgx_misc_reserved = ~ebx | SGX_MISC_RESERVED_MASK;
+	sgx_encl_size_max_64 = 1ULL << ((edx >> 8) & 0xFF);
+	sgx_encl_size_max_32 = 1ULL << (edx & 0xFF);
+
+	if (boot_cpu_has(X86_FEATURE_OSXSAVE)) {
+		cpuid_count(SGX_CPUID, 1, &eax, &ebx, &ecx, &edx);
+		sgx_xfrm_mask = (((u64)edx) << 32) + (u64)ecx;
+
+		for (i = 2; i < 64; i++) {
+			cpuid_count(0x0D, i, &eax, &ebx, &ecx, &edx);
+			if ((1 << i) & sgx_xfrm_mask)
+				sgx_xsave_size_tbl[i] = eax + ebx;
+		}
+	}
+
+	sgx_add_page_wq = alloc_workqueue("intel_sgx-add-page-wq",
+					  WQ_UNBOUND | WQ_FREEZABLE, 1);
+	if (!sgx_add_page_wq)
+		return -ENOMEM;
+
+	ret = cdev_device_add(&sgx_dev->cdev, &sgx_dev->dev);
+	if (ret)
+		goto out_workqueue;
+
+	return 0;
+out_workqueue:
+	destroy_workqueue(sgx_add_page_wq);
+	return ret;
+}
+
+static int sgx_drv_probe(struct platform_device *pdev)
+{
+	if (!sgx_enabled || !sgx_lc_enabled)
+		return -ENODEV;
+
+	return sgx_dev_init(&pdev->dev);
+}
+
+static int sgx_drv_remove(struct platform_device *pdev)
+{
+	struct sgx_context *ctx = dev_get_drvdata(&pdev->dev);
+
+	cdev_device_del(&ctx->cdev, &ctx->dev);
+	destroy_workqueue(sgx_add_page_wq);
+
+	return 0;
+}
+
+#ifdef CONFIG_ACPI
+static struct acpi_device_id sgx_device_ids[] = {
+	{"INT0E0C", 0},
+	{"", 0},
+};
+MODULE_DEVICE_TABLE(acpi, sgx_device_ids);
+#endif
+
+static struct platform_driver sgx_drv = {
+	.probe = sgx_drv_probe,
+	.remove = sgx_drv_remove,
+	.driver = {
+		.name			= "intel_sgx",
+		.acpi_match_table	= ACPI_PTR(sgx_device_ids),
+	},
+};
+
+static int __init sgx_drv_subsys_init(void)
+{
+	int ret;
+
+	ret = bus_register(&sgx_bus_type);
+	if (ret)
+		return ret;
+
+	ret = alloc_chrdev_region(&sgx_devt, 0, 1, "sgx");
+	if (ret < 0) {
+		bus_unregister(&sgx_bus_type);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void sgx_drv_subsys_exit(void)
+{
+	bus_unregister(&sgx_bus_type);
+	unregister_chrdev_region(sgx_devt, 1);
+}
+
+static int __init sgx_drv_init(void)
+{
+	int ret;
+
+	ret = sgx_drv_subsys_init();
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&sgx_drv);
+	if (ret)
+		sgx_drv_subsys_exit();
+
+	return ret;
+}
+module_init(sgx_drv_init);
+
+static void __exit sgx_drv_exit(void)
+{
+	platform_driver_unregister(&sgx_drv);
+	sgx_drv_subsys_exit();
+}
+module_exit(sgx_drv_exit);
diff --git a/drivers/platform/x86/intel_sgx/sgx_vma.c b/drivers/platform/x86/intel_sgx/sgx_vma.c
new file mode 100644
index 000000000000..cc0993b4fd40
--- /dev/null
+++ b/drivers/platform/x86/intel_sgx/sgx_vma.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+// Copyright(c) 2016-18 Intel Corporation.
+
+#include <asm/mman.h>
+#include <linux/delay.h>
+#include <linux/file.h>
+#include <linux/hashtable.h>
+#include <linux/highmem.h>
+#include <linux/mm.h>
+#include <linux/ratelimit.h>
+#include <linux/slab.h>
+#include "sgx.h"
+
+static void sgx_vma_open(struct vm_area_struct *vma)
+{
+	struct sgx_encl *encl = vma->vm_private_data;
+
+	if (!encl)
+		return;
+
+	/* kref cannot underflow because ECREATE ioctl checks that there is only
+	 * one single VMA for the enclave before proceeding.
+	 */
+	kref_get(&encl->refcount);
+}
+
+static void sgx_vma_close(struct vm_area_struct *vma)
+{
+	struct sgx_encl *encl = vma->vm_private_data;
+
+	if (!encl)
+		return;
+
+	mutex_lock(&encl->lock);
+	sgx_invalidate(encl, true);
+	mutex_unlock(&encl->lock);
+	kref_put(&encl->refcount, sgx_encl_release);
+}
+
+static int sgx_vma_fault(struct vm_fault *vmf)
+{
+	unsigned long addr = (unsigned long)vmf->address;
+	struct vm_area_struct *vma = vmf->vma;
+	struct sgx_encl_page *entry;
+
+	entry = sgx_fault_page(vma, addr, 0);
+
+	if (!IS_ERR(entry) || PTR_ERR(entry) == -EBUSY)
+		return VM_FAULT_NOPAGE;
+	else
+		return VM_FAULT_SIGBUS;
+}
+
+const struct vm_operations_struct sgx_vm_ops = {
+	.close = sgx_vma_close,
+	.open = sgx_vma_open,
+	.fault = sgx_vma_fault,
+};
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 12/13] platform/x86: ptrace() support for the SGX driver
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (10 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 11/13] platform/x86: Intel SGX driver Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-27 18:53 ` [PATCH v13 13/13] x86/sgx: Driver documentation Jarkko Sakkinen
  12 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Darren Hart, Andy Shevchenko,
	Serge Ayoun, Shay Katz-zamir, Suresh Siddha, open list

Add VMA callbacks for ptrace() that can be used with debug enclaves.
With debug enclaves data can be read and write the memory word at a time
by using ENCLS(EDBGRD) and ENCLS(EDBGWR) leaf instructions.

Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 drivers/platform/x86/intel_sgx/sgx_vma.c | 109 +++++++++++++++++++++++
 1 file changed, 109 insertions(+)

diff --git a/drivers/platform/x86/intel_sgx/sgx_vma.c b/drivers/platform/x86/intel_sgx/sgx_vma.c
index cc0993b4fd40..df604e4d0d0a 100644
--- a/drivers/platform/x86/intel_sgx/sgx_vma.c
+++ b/drivers/platform/x86/intel_sgx/sgx_vma.c
@@ -51,8 +51,117 @@ static int sgx_vma_fault(struct vm_fault *vmf)
 		return VM_FAULT_SIGBUS;
 }
 
+static int sgx_edbgrd(struct sgx_encl *encl, struct sgx_encl_page *page,
+		      unsigned long addr, void *data)
+{
+	unsigned long offset;
+	int ret;
+
+	offset = addr & ~PAGE_MASK;
+
+	if ((page->desc & SGX_ENCL_PAGE_TCS) &&
+	    offset > offsetof(struct sgx_tcs, gs_limit))
+		return -ECANCELED;
+
+	ret = __edbgrd(sgx_epc_addr(page->epc_page) + offset, data);
+	if (ret) {
+		sgx_dbg(encl, "EDBGRD returned %d\n", ret);
+		return encls_to_err(ret);
+	}
+
+	return 0;
+}
+
+static int sgx_edbgwr(struct sgx_encl *encl, struct sgx_encl_page *page,
+		      unsigned long addr, void *data)
+{
+	unsigned long offset;
+	int ret;
+
+	offset = addr & ~PAGE_MASK;
+
+	/* Writing anything else than flags will cause #GP */
+	if ((page->desc & SGX_ENCL_PAGE_TCS) &&
+	    offset != offsetof(struct sgx_tcs, flags))
+		return -ECANCELED;
+
+	ret = __edbgwr(sgx_epc_addr(page->epc_page) + offset, data);
+	if (ret) {
+		sgx_dbg(encl, "EDBGWR returned %d\n", ret);
+		return encls_to_err(ret);
+	}
+
+	return 0;
+}
+
+static int sgx_vma_access(struct vm_area_struct *vma, unsigned long addr,
+			  void *buf, int len, int write)
+{
+	struct sgx_encl *encl = vma->vm_private_data;
+	struct sgx_encl_page *entry = NULL;
+	unsigned long align;
+	char data[sizeof(unsigned long)];
+	int offset;
+	int cnt;
+	int ret = 0;
+	int i;
+
+	/* If process was forked, VMA is still there but vm_private_data is set
+	 * to NULL.
+	 */
+	if (!encl)
+		return -EFAULT;
+
+	if (!(encl->flags & SGX_ENCL_DEBUG) ||
+	    !(encl->flags & SGX_ENCL_INITIALIZED) ||
+	    (encl->flags & SGX_ENCL_DEAD))
+		return -EFAULT;
+
+	for (i = 0; i < len; i += cnt) {
+		if (!entry || !((addr + i) & (PAGE_SIZE - 1))) {
+			if (entry)
+				entry->desc &= ~SGX_ENCL_PAGE_RESERVED;
+
+			entry = sgx_fault_page(vma, (addr + i) & PAGE_MASK,
+					       true);
+			if (IS_ERR(entry)) {
+				ret = PTR_ERR(entry);
+				entry = NULL;
+				break;
+			}
+		}
+
+		/* Locking is not needed because only immutable fields of the
+		 * page are accessed and page itself is reserved so that it
+		 * cannot be swapped out in the middle.
+		 */
+
+		align = ALIGN_DOWN(addr + i, sizeof(unsigned long));
+		offset = (addr + i) & (sizeof(unsigned long) - 1);
+		cnt = sizeof(unsigned long) - offset;
+		cnt = min(cnt, len - i);
+
+		ret = sgx_edbgrd(encl, entry, align, data);
+		if (ret)
+			break;
+		if (write) {
+			memcpy(data + offset, buf + i, cnt);
+			ret = sgx_edbgwr(encl, entry, align, data);
+			if (ret)
+				break;
+		} else
+			memcpy(buf + i, data + offset, cnt);
+	}
+
+	if (entry)
+		entry->desc &= ~SGX_ENCL_PAGE_RESERVED;
+
+	return ret < 0 ? ret : i;
+}
+
 const struct vm_operations_struct sgx_vm_ops = {
 	.close = sgx_vma_close,
 	.open = sgx_vma_open,
 	.fault = sgx_vma_fault,
+	.access = sgx_vma_access,
 };
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* [PATCH v13 13/13] x86/sgx: Driver documentation
  2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
                   ` (11 preceding siblings ...)
  2018-08-27 18:53 ` [PATCH v13 12/13] platform/x86: ptrace() support for the " Jarkko Sakkinen
@ 2018-08-27 18:53 ` Jarkko Sakkinen
  2018-08-27 19:40   ` Randy Dunlap
  2018-08-28  8:03   ` Jarkko Sakkinen
  12 siblings, 2 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-27 18:53 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jarkko Sakkinen, Jonathan Corbet, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, open list:DOCUMENTATION, open list

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 9145 bytes --]

Documentation of the features of the Software Guard eXtensions used
by the Linux kernel and basic design choices for the core and driver
and functionality.

Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
 Documentation/index.rst         |   1 +
 Documentation/x86/intel_sgx.rst | 185 ++++++++++++++++++++++++++++++++
 2 files changed, 186 insertions(+)
 create mode 100644 Documentation/x86/intel_sgx.rst

diff --git a/Documentation/index.rst b/Documentation/index.rst
index 5db7e87c7cb1..1cdc139adb40 100644
--- a/Documentation/index.rst
+++ b/Documentation/index.rst
@@ -104,6 +104,7 @@ implementation.
    :maxdepth: 2
 
    sh/index
+   x86/index
 
 Filesystem Documentation
 ------------------------
diff --git a/Documentation/x86/intel_sgx.rst b/Documentation/x86/intel_sgx.rst
new file mode 100644
index 000000000000..f6b7979c41f2
--- /dev/null
+++ b/Documentation/x86/intel_sgx.rst
@@ -0,0 +1,185 @@
+===================
+Intel(R) SGX driver
+===================
+
+Introduction
+============
+
+Intel(R) SGX is a set of CPU instructions that can be used by applications to
+set aside private regions of code and data. The code outside the enclave is
+disallowed to access the memory inside the enclave by the CPU access control.
+In a way you can think that SGX provides inverted sandbox. It protects the
+application from a malicious host.
+
+You can tell if your CPU supports SGX by looking into ``/proc/cpuinfo``:
+
+	``cat /proc/cpuinfo  | grep sgx``
+
+Overview of SGX
+===============
+
+SGX has a set of data structures to maintain information about the enclaves and
+their security properties. BIOS reserves a fixed size region of physical memory
+for these structures by setting Processor Reserved Memory Range Registers
+(PRMRR).
+
+This memory range is protected from outside access by the CPU and all the data
+coming in and out of the CPU package is encrypted by a key that is generated for
+each boot cycle.
+
+Enclaves execute in ring-3 in a special enclave submode using pages from the
+reserved memory range. A fixed logical address range for the enclave is reserved
+by ENCLS(ECREATE), a leaf instruction used to create enclaves. It is referred in
+the documentation commonly as the ELRANGE.
+
+Every memory access to the ELRANGE is asserted by the CPU. If the CPU is not
+executing in the enclave mode inside the enclave, #GP is raised. On the other
+hand enclave code can make memory accesses both inside and outside of the
+ELRANGE.
+
+Enclave can only execute code inside the ELRANGE. Instructions that may cause
+VMEXIT, IO instructions and instructions that require a privilege change are
+prohibited inside the enclave. Interrupts and exceptions always cause enclave
+to exit and jump to an address outside the enclave given when the enclave is
+entered by using the leaf instruction ENCLS(EENTER).
+
+Data types
+----------
+
+The protected memory range contains the following data:
+
+* **Enclave Page Cache (EPC):** protected pages
+* **Enclave Page Cache Map (EPCM):** a database that describes the state of the
+  pages and link them to an enclave.
+
+EPC has a number of different types of pages:
+
+* **SGX Enclave Control Structure (SECS)**: describes the global
+  properties of an enclave.
+* **Regular (REG):** code and data pages in the ELRANGE.
+* **Thread Control Structure (TCS):** pages that define entry points inside an
+  enclave. The enclave can only be entered through these entry points and each
+  can host a single hardware thread at a time.
+* **Version Array (VA)**: 64-bit version numbers for pages that have been
+  swapped outside the enclave. Each page contains 512 version numbers.
+
+Launch control
+--------------
+
+To launch an enclave, two structures must be provided for ENCLS(EINIT):
+
+1. **SIGSTRUCT:** signed measurement of the enclave binary.
+2. **EINITTOKEN:** a cryptographic token CMAC-signed with a AES256-key called
+   *launch key*, which is re-generated for each boot cycle.
+
+The CPU holds a SHA256 hash of a 3072-bit RSA public key inside
+IA32_SGXLEPUBKEYHASHn MSRs. Enclaves with a SIGSTRUCT that is signed with this
+key do not require a valid EINITTOKEN and can be authorized with special
+privileges. One of those privileges is ability to acquire the launch key with
+ENCLS(EGETKEY).
+
+**IA32_FEATURE_CONTROL[17]** is used by the BIOS configure whether
+IA32_SGXLEPUBKEYHASH MSRs are read-only or read-write before locking the
+feature control register and handing over control to the operating system.
+
+Enclave construction
+--------------------
+
+The construction is started by filling out the SECS that contains enclave
+address range, privileged attributes and measurement of TCS and REG pages (pages
+that will be mapped to the address range) among the other things. This structure
+is passed out to the ENCLS(ECREATE) together with a physical address of a page
+in EPC that will hold the SECS.
+
+The pages are added with ENCLS(EADD) and measured with ENCLS(EEXTEND) i.e.
+SHA256 hash MRENCLAVE residing in the SECS is extended with the page data.
+
+After all of the pages have been added, the enclave is initialized with
+ENCLS(EINIT). ENCLS(INIT) checks that the SIGSTRUCT is signed with the contained
+public key. If the given EINITTOKEN has the valid bit set, the CPU checks that
+the token is valid (CMAC'd with the launch key). If the token is not valid,
+the CPU will check whether the enclave is signed with a key matching to the
+IA32_SGXLEPUBKEYHASHn MSRs.
+
+Swapping pages
+--------------
+
+Enclave pages can be swapped out with ENCLS(EWB) to the unprotected memory. In
+addition to the EPC page, ENCLS(EWB) takes in a VA page and address for PCMD
+structure (Page Crypto MetaData) as input. The VA page will seal a version
+number for the page. PCMD is 128 byte structure that contains tracking
+information for the page, most importantly its MAC. With these structures the
+enclave is sealed and rollback protected while it resides in the unprotected
+memory.
+
+Before the page can be swapped out it must not have any active TLB references.
+ENCLS(EBLOCK) instruction moves a page to the *blocked* state, which means
+that no new TLB entries can be created to it by the hardware threads.
+
+After this a shootdown sequence is started with ENCLS(ETRACK), which sets an
+increased counter value to the entering hardware threads. ENCLS(EWB) will
+return SGX_NOT_TRACKED error while there are still threads with the earlier
+couner value because that means that there might be hardware thread inside
+the enclave with TLB entries to pages that are to be swapped.
+
+Kernel internals
+================
+
+Requirements
+------------
+
+Because SGX has an ever evolving and expanding feature set, it's possible for
+a BIOS or VMM to configure a system in such a way that not all CPUs are equal,
+e.g. where Launch Control is only enabled on a subset of CPUs.  Linux does
+*not* support such a heterogeneous system configuration, nor does it even
+attempt to play nice in the face of a misconfigured system.  With the exception
+of Launch Control's hash MSRs, which can vary per CPU, Linux assumes that all
+CPUs have a configuration that is identical to the boot CPU.
+
+
+Roles and responsibilities
+--------------------------
+
+SGX introduces system resources, e.g. EPC memory, that must be accessible to
+multiple entities, e.g. the native kernel driver (to expose SGX to userspace)
+and KVM (to expose SGX to VMs), ideally without introducing any dependencies
+between each SGX entity.  To that end, the kernel owns and manages the shared
+system resources, i.e. the EPC and Launch Control MSRs, and defines functions
+that provide appropriate access to the shared resources.  SGX support for
+user space and VMs is left to the SGX platform driver and KVM respectively.
+
+Launching enclaves
+------------------
+
+The current kernel implementation supports only unlocked MSRs i.e.
+FEATURE_CONTROL_SGX_LE_WR must be set. The launch is performed by setting the
+MSRs to the hash of the public key modulus of the enclave signer, which is one
+f the fields in the SIGSTRUCT.
+
+EPC management
+--------------
+
+Due to the unique requirements for swapping EPC pages, and because EPC pages
+(currently) do not have associated page structures, management of the EPC is
+not handled by the standard Linux swapper.  SGX directly handles swapping
+of EPC pages, including a kthread to initiate reclaim and a rudimentary LRU
+mechanism. The consumers of EPC pages, e.g. the SGX driver, are required to
+implement function callbacks that can be invoked by the kernel to age,
+swap, and/or forcefully reclaim a target EPC page.  In effect, the kernel
+controls what happens and when, while the consumers (driver, KVM, etc..) do
+the actual work.
+
+SGX uapi
+========
+
+.. kernel-doc:: drivers/platform/x86/intel_sgx/sgx_ioctl.c
+   :functions: sgx_ioc_enclave_create
+               sgx_ioc_enclave_add_page
+               sgx_ioc_enclave_init
+
+.. kernel-doc:: arch/x86/include/uapi/asm/sgx.h
+
+References
+==========
+
+* System Programming Manual: 39.1.4 Intel® SGX Launch Control Configuration
-- 
2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX
  2018-08-27 18:53 ` [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX Jarkko Sakkinen
@ 2018-08-27 19:39   ` Dave Hansen
  2018-08-28  7:23     ` Jarkko Sakkinen
  2018-08-28 10:21   ` Borislav Petkov
  1 sibling, 1 reply; 103+ messages in thread
From: Dave Hansen @ 2018-08-27 19:39 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: sean.j.christopherson, nhorman, npmccallum, linux-sgx,
	Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Paolo Bonzini,
	Radim Krčmář,
	Peter Zijlstra, Borislav Petkov, Greg Kroah-Hartman,
	David Woodhouse, Alexei Starovoitov, Andi Kleen,
	Konrad Rzeszutek Wilk, Ricardo Neri, Kirill A. Shutemov,
	Andy Lutomirski, open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	open list:KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)

On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> +	/* Intel SGX features: level 0x00000012 */
> +	if (c->cpuid_level >= 0x00000012) {
> +		cpuid(0x00000012, &eax, &ebx, &ecx, &edx);
> +
> +		c->x86_capability[CPUID_12_EAX] = eax;
> +	}

I've given this specific bit of feedback at least once in the past.
These patches are not ordered properly.  You introduce this in the next
patch:

+#define SGX_CPUID 0x12

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 13/13] x86/sgx: Driver documentation
  2018-08-27 18:53 ` [PATCH v13 13/13] x86/sgx: Driver documentation Jarkko Sakkinen
@ 2018-08-27 19:40   ` Randy Dunlap
  2018-08-28  7:58     ` Jarkko Sakkinen
  2018-08-28  8:03   ` Jarkko Sakkinen
  1 sibling, 1 reply; 103+ messages in thread
From: Randy Dunlap @ 2018-08-27 19:40 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jonathan Corbet, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, open list:DOCUMENTATION, open list

On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> Documentation of the features of the Software Guard eXtensions used
> by the Linux kernel and basic design choices for the core and driver
> and functionality.
> 
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>

Hi,

Comments inline...

> ---
>  Documentation/index.rst         |   1 +
>  Documentation/x86/intel_sgx.rst | 185 ++++++++++++++++++++++++++++++++
>  2 files changed, 186 insertions(+)
>  create mode 100644 Documentation/x86/intel_sgx.rst
> 
> diff --git a/Documentation/index.rst b/Documentation/index.rst
> index 5db7e87c7cb1..1cdc139adb40 100644
> --- a/Documentation/index.rst
> +++ b/Documentation/index.rst
> @@ -104,6 +104,7 @@ implementation.
>     :maxdepth: 2
>  
>     sh/index
> +   x86/index
>  
>  Filesystem Documentation
>  ------------------------
> diff --git a/Documentation/x86/intel_sgx.rst b/Documentation/x86/intel_sgx.rst
> new file mode 100644
> index 000000000000..f6b7979c41f2
> --- /dev/null
> +++ b/Documentation/x86/intel_sgx.rst
> @@ -0,0 +1,185 @@
> +===================
> +Intel(R) SGX driver
> +===================
> +
> +Introduction
> +============
> +
> +Intel(R) SGX is a set of CPU instructions that can be used by applications to
> +set aside private regions of code and data. The code outside the enclave is

   set aside private regions of code and data (which are called enclaves). The ...

> +disallowed to access the memory inside the enclave by the CPU access control.
> +In a way you can think that SGX provides inverted sandbox. It protects the

                                   provides an inverted sandbox.

> +application from a malicious host.
> +
> +You can tell if your CPU supports SGX by looking into ``/proc/cpuinfo``:
> +
> +	``cat /proc/cpuinfo  | grep sgx``

or	``grep sgx /proc/cpuinfo``
?

> +
> +Overview of SGX
> +===============
> +
> +SGX has a set of data structures to maintain information about the enclaves and
> +their security properties. BIOS reserves a fixed size region of physical memory
> +for these structures by setting Processor Reserved Memory Range Registers
> +(PRMRR).
> +
> +This memory range is protected from outside access by the CPU and all the data
> +coming in and out of the CPU package is encrypted by a key that is generated for
> +each boot cycle.
> +
> +Enclaves execute in ring-3 in a special enclave submode using pages from the
> +reserved memory range. A fixed logical address range for the enclave is reserved
> +by ENCLS(ECREATE), a leaf instruction used to create enclaves. It is referred in

                                                                  It is referred to in

> +the documentation commonly as the ELRANGE.
> +
> +Every memory access to the ELRANGE is asserted by the CPU. If the CPU is not
> +executing in the enclave mode inside the enclave, #GP is raised. On the other
> +hand enclave code can make memory accesses both inside and outside of the
> +ELRANGE.
> +
> +Enclave can only execute code inside the ELRANGE. Instructions that may cause

   An enclave can
or
   Enclaves can

> +VMEXIT, IO instructions and instructions that require a privilege change are
> +prohibited inside the enclave. Interrupts and exceptions always cause enclave

                                                                   cause the enclave

> +to exit and jump to an address outside the enclave given when the enclave is
> +entered by using the leaf instruction ENCLS(EENTER).
> +
> +Data types
> +----------
> +
> +The protected memory range contains the following data:
> +
> +* **Enclave Page Cache (EPC):** protected pages
> +* **Enclave Page Cache Map (EPCM):** a database that describes the state of the
> +  pages and link them to an enclave.
> +
> +EPC has a number of different types of pages:
> +
> +* **SGX Enclave Control Structure (SECS)**: describes the global
> +  properties of an enclave.
> +* **Regular (REG):** code and data pages in the ELRANGE.
> +* **Thread Control Structure (TCS):** pages that define entry points inside an
> +  enclave. The enclave can only be entered through these entry points and each
> +  can host a single hardware thread at a time.
> +* **Version Array (VA)**: 64-bit version numbers for pages that have been
> +  swapped outside the enclave. Each page contains 512 version numbers.
> +
> +Launch control
> +--------------
> +
> +To launch an enclave, two structures must be provided for ENCLS(EINIT):
> +
> +1. **SIGSTRUCT:** signed measurement of the enclave binary.

what does "signed measurement" mean?

> +2. **EINITTOKEN:** a cryptographic token CMAC-signed with a AES256-key called
> +   *launch key*, which is re-generated for each boot cycle.
> +
> +The CPU holds a SHA256 hash of a 3072-bit RSA public key inside
> +IA32_SGXLEPUBKEYHASHn MSRs. Enclaves with a SIGSTRUCT that is signed with this
> +key do not require a valid EINITTOKEN and can be authorized with special
> +privileges. One of those privileges is ability to acquire the launch key with
> +ENCLS(EGETKEY).
> +
> +**IA32_FEATURE_CONTROL[17]** is used by the BIOS configure whether

                                        by the BIOS to configure whether

> +IA32_SGXLEPUBKEYHASH MSRs are read-only or read-write before locking the
> +feature control register and handing over control to the operating system.
> +
> +Enclave construction
> +--------------------
> +
> +The construction is started by filling out the SECS that contains enclave
> +address range, privileged attributes and measurement of TCS and REG pages (pages

what is this "measurement"?  how is it done?

> +that will be mapped to the address range) among the other things. This structure
> +is passed out to the ENCLS(ECREATE) together with a physical address of a page
> +in EPC that will hold the SECS.
> +
> +The pages are added with ENCLS(EADD) and measured with ENCLS(EEXTEND) i.e.
> +SHA256 hash MRENCLAVE residing in the SECS is extended with the page data.
> +
> +After all of the pages have been added, the enclave is initialized with
> +ENCLS(EINIT). ENCLS(INIT) checks that the SIGSTRUCT is signed with the contained
> +public key. If the given EINITTOKEN has the valid bit set, the CPU checks that
> +the token is valid (CMAC'd with the launch key). If the token is not valid,
> +the CPU will check whether the enclave is signed with a key matching to the
> +IA32_SGXLEPUBKEYHASHn MSRs.
> +
> +Swapping pages
> +--------------
> +
> +Enclave pages can be swapped out with ENCLS(EWB) to the unprotected memory. In
> +addition to the EPC page, ENCLS(EWB) takes in a VA page and address for PCMD
> +structure (Page Crypto MetaData) as input. The VA page will seal a version
> +number for the page. PCMD is 128 byte structure that contains tracking
> +information for the page, most importantly its MAC. With these structures the
> +enclave is sealed and rollback protected while it resides in the unprotected
> +memory.
> +
> +Before the page can be swapped out it must not have any active TLB references.
> +ENCLS(EBLOCK) instruction moves a page to the *blocked* state, which means
> +that no new TLB entries can be created to it by the hardware threads.
> +
> +After this a shootdown sequence is started with ENCLS(ETRACK), which sets an
> +increased counter value to the entering hardware threads. ENCLS(EWB) will
> +return SGX_NOT_TRACKED error while there are still threads with the earlier
> +couner value because that means that there might be hardware thread inside

   counter

> +the enclave with TLB entries to pages that are to be swapped.
> +
> +Kernel internals
> +================
> +
> +Requirements
> +------------
> +
> +Because SGX has an ever evolving and expanding feature set, it's possible for
> +a BIOS or VMM to configure a system in such a way that not all CPUs are equal,
> +e.g. where Launch Control is only enabled on a subset of CPUs.  Linux does
> +*not* support such a heterogeneous system configuration, nor does it even
> +attempt to play nice in the face of a misconfigured system.  With the exception
> +of Launch Control's hash MSRs, which can vary per CPU, Linux assumes that all
> +CPUs have a configuration that is identical to the boot CPU.
> +
> +
> +Roles and responsibilities
> +--------------------------
> +
> +SGX introduces system resources, e.g. EPC memory, that must be accessible to
> +multiple entities, e.g. the native kernel driver (to expose SGX to userspace)
> +and KVM (to expose SGX to VMs), ideally without introducing any dependencies
> +between each SGX entity.  To that end, the kernel owns and manages the shared
> +system resources, i.e. the EPC and Launch Control MSRs, and defines functions
> +that provide appropriate access to the shared resources.  SGX support for
> +user space and VMs is left to the SGX platform driver and KVM respectively.

   userspace
(as on the second line of that same paragraph)

> +
> +Launching enclaves
> +------------------
> +
> +The current kernel implementation supports only unlocked MSRs i.e.
> +FEATURE_CONTROL_SGX_LE_WR must be set. The launch is performed by setting the
> +MSRs to the hash of the public key modulus of the enclave signer, which is one
> +f the fields in the SIGSTRUCT.
> +
> +EPC management
> +--------------
> +
> +Due to the unique requirements for swapping EPC pages, and because EPC pages
> +(currently) do not have associated page structures, management of the EPC is
> +not handled by the standard Linux swapper.  SGX directly handles swapping
> +of EPC pages, including a kthread to initiate reclaim and a rudimentary LRU
> +mechanism. The consumers of EPC pages, e.g. the SGX driver, are required to
> +implement function callbacks that can be invoked by the kernel to age,
> +swap, and/or forcefully reclaim a target EPC page.  In effect, the kernel
> +controls what happens and when, while the consumers (driver, KVM, etc..) do
> +the actual work.
> +
> +SGX uapi
> +========
> +
> +.. kernel-doc:: drivers/platform/x86/intel_sgx/sgx_ioctl.c
> +   :functions: sgx_ioc_enclave_create
> +               sgx_ioc_enclave_add_page
> +               sgx_ioc_enclave_init
> +
> +.. kernel-doc:: arch/x86/include/uapi/asm/sgx.h
> +
> +References
> +==========
> +
> +* System Programming Manual: 39.1.4 Intel® SGX Launch Control Configuration
> 

HTH.
-- 
~Randy

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 04/13] x86/sgx: Architectural structures
  2018-08-27 18:53 ` [PATCH v13 04/13] x86/sgx: Architectural structures Jarkko Sakkinen
@ 2018-08-27 19:41   ` Dave Hansen
  2018-08-28  8:08     ` Jarkko Sakkinen
  2018-09-03 13:16   ` Andy Shevchenko
  1 sibling, 1 reply; 103+ messages in thread
From: Dave Hansen @ 2018-08-27 19:41 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: sean.j.christopherson, nhorman, npmccallum, linux-sgx,
	Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

> +/**
> + * enum sgx_encls_leaves - return codes for ENCLS, ENCLU and ENCLV
> + * %SGX_SUCCESS:		No error.
> + * %SGX_INVALID_SIG_STRUCT:	SIGSTRUCT contains an invalid value.
> + * %SGX_INVALID_ATTRIBUTE:	Enclave is not attempting to access a resource
> + *				for which it is not authorized.
> + * %SGX_BLKSTATE:		EPC page is already blocked.
> + * %SGX_INVALID_MEASUREMENT:	SIGSTRUCT or EINITTOKEN contains an incorrect
> + *				measurement.
...
> +enum sgx_return_codes {
> +	SGX_SUCCESS			= 0,
> +	SGX_INVALID_SIG_STRUCT		= 1,
> +	SGX_INVALID_ATTRIBUTE		= 2,
> +	SGX_BLKSTATE			= 3,
> +	SGX_INVALID_MEASUREMENT		= 4,
...

I don't think I've ever seen this particular method of commenting
before.  It's rather verbose and duplicates the names twice, which seems
a bit silly.

Can you talk a bit about why you chose to do it this way?  I'd
personally much rather see at least some brief comments inline with the
definitions.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 05/13] x86/msr: Add SGX definitions to msr-index.h
  2018-08-27 18:53 ` [PATCH v13 05/13] x86/msr: Add SGX definitions to msr-index.h Jarkko Sakkinen
@ 2018-08-27 19:42   ` Dave Hansen
  2018-08-28  8:11     ` Jarkko Sakkinen
  0 siblings, 1 reply; 103+ messages in thread
From: Dave Hansen @ 2018-08-27 19:42 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: sean.j.christopherson, nhorman, npmccallum, linux-sgx,
	Haim Cohen, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Borislav Petkov, Konrad Rzeszutek Wilk, Tom Lendacky,
	Paolo Bonzini, David Woodhouse, Greg Kroah-Hartman,
	Janakarajan Natarajan, Matt Turner, Andy Lutomirski,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> @@ -866,10 +867,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
>  		}
>  	}
>  
> -	/* Intel SGX features: level 0x00000012 */
> -	if (c->cpuid_level >= 0x00000012) {
> -		cpuid(0x00000012, &eax, &ebx, &ecx, &edx);
> -
> +	/* Intel SGX features */
> +	if (c->cpuid_level >= SGX_CPUID) {
> +		cpuid(SGX_CPUID,  &eax, &ebx, &ecx, &edx);
>  		c->x86_capability[CPUID_12_EAX] = eax;
>  	}

This hunk has no apparent connection to the changelog.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 06/13] x86/sgx: Detect Intel SGX
  2018-08-27 18:53 ` [PATCH v13 06/13] x86/sgx: Detect Intel SGX Jarkko Sakkinen
@ 2018-08-27 19:53   ` Dave Hansen
  2018-08-28  8:28     ` Jarkko Sakkinen
  2018-09-03 14:26   ` Andy Shevchenko
  1 sibling, 1 reply; 103+ messages in thread
From: Dave Hansen @ 2018-08-27 19:53 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: sean.j.christopherson, nhorman, npmccallum, linux-sgx,
	Suresh Siddha, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Serge Ayoun, Rafael J. Wysocki, Borislav Petkov, Reinette Chatre,
	Andi Kleen, Greg Kroah-Hartman, Kirill A. Shutemov,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

> +config INTEL_SGX_CORE
> +	prompt "Intel SGX core functionality"
> +	def_bool n
> +	depends on X86_64 && CPU_SUP_INTEL
> +	help
> +	Intel Software Guard eXtensions (SGX) is a set of CPU instructions
> +	that allows ring 3 applications to create enclaves, private regions
> +	of memory that are protected, by hardware, from unauthorized access
> +	and/or modification.

This is a bit comma-crazy.  Also, considering some of our recent CVE
fun, I'd probably not claim hardware protection. :)

Maybe:

	Intel Software Guard eXtensions (SGX) CPU feature that allows
	ring 3 applications to create enclaves: private regions
	of memory that are architecturally protected from unauthorized
	access and/or modification.

> +	This option enables kernel recognition of SGX, high-level management
> +	of the Enclave Page Cache (EPC), tracking and writing of SGX Launch
> +	Enclave Hash MSRs, and allows for virtualization of SGX via KVM. By
> +	iteslf, this option does not provide SGX support to userspace.

itself


> diff --git a/arch/x86/include/asm/sgx_pr.h b/arch/x86/include/asm/sgx_pr.h
> new file mode 100644
> index 000000000000..c68578127620
> --- /dev/null
> +++ b/arch/x86/include/asm/sgx_pr.h
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
> +// Copyright(c) 2016-17 Intel Corporation.
> +
> +#ifndef _ASM_X86_SGX_PR_H
> +#define _ASM_X86_SGX_PR_H
> +
> +#include <linux/printk.h>
> +#include <linux/ratelimit.h>
> +
> +#undef pr_fmt
> +#define pr_fmt(fmt) "sgx: " fmt
> +
> +#endif /* _ASM_X86_SGX_PR_H */

I don't think this belongs in a generic header.  Generally, we do the
pr_fmt stuff in .c files, not in headers.  If someone includes this
header directly or indirectly, they'll get a big surprise.

If you *must* have this in a .h file, put it in
arch/x86/kernel/cpu/intel_sgx.h or something and #include "intel_sgx.h"
in all the .c files where you want this.


> +static __init int sgx_init(void)
> +{
> +	unsigned long fc;
> +
> +	if (!boot_cpu_has(X86_FEATURE_SGX))
> +		return false;
> +
> +	if (!boot_cpu_has(X86_FEATURE_SGX1))
> +		return false;
> +
> +	rdmsrl(MSR_IA32_FEATURE_CONTROL, fc);
> +	if (!(fc & FEATURE_CONTROL_LOCKED)) {
> +		pr_info("IA32_FEATURE_CONTROL MSR is not locked\n");
> +		return false;
> +	}

This is a rather crummy error message.  Doesn't this keep sgx from
initializing?  Would something like this be more informative?

	pr_info("failed init: IA32_FEATURE_CONTROL MSR not locked\n");

> +	if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) {
> +		pr_info("disabled by the firmware\n");
> +		return false;
> +	}
> +
> +	if (!(fc & FEATURE_CONTROL_SGX_LE_WR))
> +		pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not writable\n");

How about something that might help an end user?  Perhaps:

	pr_warn("launch configuration not available\n");

> +	sgx_enabled = true;
> +	sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR);
> +	return 0;
> +}
> +
> +arch_initcall(sgx_init);
> 



^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-08-27 18:53 ` [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages Jarkko Sakkinen
@ 2018-08-27 21:07   ` Dave Hansen
  2018-08-28 10:30     ` Jarkko Sakkinen
  2018-09-03 14:41   ` Andy Shevchenko
  1 sibling, 1 reply; 103+ messages in thread
From: Dave Hansen @ 2018-08-27 21:07 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: sean.j.christopherson, nhorman, npmccallum, linux-sgx,
	Serge Ayoun, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Suresh Siddha, open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> Add data structures to track Enclave Page Cache (EPC) pages.  EPC is
> divided into multiple banks (1-N) of which addresses and sizes can be
> enumerated with CPUID by the OS.
> 
> On NUMA systems a node can have at most bank. A bank can be at most part of
> two nodes. SGX supports both nodes with a single memory controller and also
> sub-cluster nodes with severals memory controllers on a single die.
> 
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> Co-developed-by: Serge Ayoun <serge.ayoun@intel.com>
> Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Signed-off-by: Serge Ayoun <serge.ayoun@intel.com>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> ---
>  arch/x86/include/asm/sgx.h      |  60 ++++++++++++++++++
>  arch/x86/kernel/cpu/intel_sgx.c | 106 +++++++++++++++++++++++++++++++-
>  2 files changed, 164 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
> index 2130e639ab49..17b7b3aa66bf 100644
> --- a/arch/x86/include/asm/sgx.h
> +++ b/arch/x86/include/asm/sgx.h
> @@ -4,9 +4,69 @@
>  #ifndef _ASM_X86_SGX_H
>  #define _ASM_X86_SGX_H
>  
> +#include <linux/bitops.h>
> +#include <linux/err.h>
> +#include <linux/rwsem.h>
>  #include <linux/types.h>
> +#include <asm/sgx_arch.h>
> +#include <asm/asm.h>
> +
> +#define SGX_MAX_EPC_BANKS 8

This is _still_ missing a meaningful description of what a bank is and
whether it is a hardware or software structure.

It would also help us to determine whether your bit packing below is
really required.

> +struct sgx_epc_page {
> +	unsigned long desc;
> +	struct list_head list;
> +};
> +
> +struct sgx_epc_bank {
> +	unsigned long pa;
> +	void *va;
> +	unsigned long size;

Please add units.  size could be bytes or pages, or who knows what.  I
can't tell you how many bugs I've tripped over in the past from simple
unit conversions

> +	struct sgx_epc_page *pages_data;
> +	struct sgx_epc_page **pages;
> +	unsigned long free_cnt;
> +	spinlock_t lock;
> +};
>  
>  extern bool sgx_enabled;
>  extern bool sgx_lc_enabled;
> +extern struct sgx_epc_bank sgx_epc_banks[SGX_MAX_EPC_BANKS];
> +
> +/*
> + * enum sgx_epc_page_desc - defines bits and masks for an EPC page's desc

Why are you bothering packing these bits?  This seems a rather
convoluted way to store two integers.

> +static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned long index,
> +				    struct sgx_epc_bank *bank)
> +{
> +	unsigned long nr_pages = size >> PAGE_SHIFT;
> +	struct sgx_epc_page *pages_data;
> +	unsigned long i;
> +	void *va;
> +
> +	va = ioremap_cache(addr, size);
> +	if (!va)
> +		return -ENOMEM;
> +
> +	pages_data = kcalloc(nr_pages, sizeof(struct sgx_epc_page), GFP_KERNEL);
> +	if (!pages_data)
> +		goto out_iomap;

This looks like you're roughly limited by the page allocator to a bank
size of ~1.4GB which seems kinda small.  Is this really OK?

> +	bank->pages = kcalloc(nr_pages, sizeof(struct sgx_epc_page *),
> +			      GFP_KERNEL);
> +	if (!bank->pages)
> +		goto out_pdata;
> +
> +	for (i = 0; i < nr_pages; i++) {
> +		bank->pages[i] = &pages_data[i];
> +		bank->pages[i]->desc = (addr + (i << PAGE_SHIFT)) | index;
> +	}
> +
> +	bank->pa = addr;
> +	bank->size = size;
> +	bank->va = va;
> +	bank->free_cnt = nr_pages;
> +	bank->pages_data = pages_data;
> +	spin_lock_init(&bank->lock);
> +	return 0;
> +out_pdata:
> +	kfree(pages_data);
> +out_iomap:
> +	iounmap(va);
> +	return -ENOMEM;
> +}
> +
> +static __init void sgx_page_cache_teardown(void)
> +{
> +	struct sgx_epc_bank *bank;
> +	int i;
> +
> +	for (i = 0; i < sgx_nr_epc_banks; i++) {
> +		bank = &sgx_epc_banks[i];
> +		iounmap((void *)bank->va);
> +		kfree(bank->pages);
> +		kfree(bank->pages_data);
> +	}
> +}
> +
> +static inline u64 sgx_combine_bank_regs(u64 low, u64 high)
> +{
> +	return (low & 0xFFFFF000) + ((high & 0xFFFFF) << 32);
> +}

-ENOCOMMENT for a rather weird looking calculation

> +static __init int sgx_page_cache_init(void)
> +{
> +	u32 eax, ebx, ecx, edx;
> +	u64 pa, size;
> +	int ret;
> +	int i;
> +
> +	for (i = 0; i < SGX_MAX_EPC_BANKS; i++) {
> +		cpuid_count(SGX_CPUID, 2 + i, &eax, &ebx, &ecx, &edx);
> +		if (!(eax & 0xF))
> +			break;

So, we have random data coming out of a random CPUID leaf being called
'eax' and then being tested against a random hard-coded mask.  This
seems rather unfortunate for someone trying to understand the code.  Can
we do better?

> +		pa = sgx_combine_bank_regs(eax, ebx);
> +		size = sgx_combine_bank_regs(ecx, edx);
> +		pr_info("EPC bank 0x%llx-0x%llx\n", pa, pa + size - 1);
> +		ret = sgx_init_epc_bank(pa, size, i, &sgx_epc_banks[i]);
> +		if (ret) {
> +			sgx_page_cache_teardown();
> +			return ret;
> +		}

So if one bank fails, we tear down all banks, yet leave sgx_nr_epc_banks
incremented?  That sounds troublesome.

> +		sgx_nr_epc_banks++;
> +	}
> +
> +	if (!sgx_nr_epc_banks) {
> +		pr_err("There are zero EPC banks.\n");
> +		return -ENODEV;
> +	}
> +
> +	return 0;
> +}

Does this support hot-addition of a bank?  If not, why not?

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-27 18:53 ` [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager Jarkko Sakkinen
@ 2018-08-27 21:14   ` Dave Hansen
  2018-08-28  8:36     ` Jarkko Sakkinen
  2018-08-27 21:15   ` Dave Hansen
                     ` (2 subsequent siblings)
  3 siblings, 1 reply; 103+ messages in thread
From: Dave Hansen @ 2018-08-27 21:14 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: sean.j.christopherson, nhorman, npmccallum, linux-sgx,
	Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Suresh Siddha,
	Serge Ayoun, open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> +enum sgx_alloc_flags {
> +	SGX_ALLOC_ATOMIC	= BIT(0),
> +};

Doing this with enums is unprecedented IMNHO.  Why are you doing it this
way for simple, one-off constants?

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-27 18:53 ` [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager Jarkko Sakkinen
  2018-08-27 21:14   ` Dave Hansen
@ 2018-08-27 21:15   ` Dave Hansen
  2018-08-28  8:35     ` Jarkko Sakkinen
  2018-09-03 19:02   ` Andy Shevchenko
  2018-09-11 15:04   ` Sean Christopherson
  3 siblings, 1 reply; 103+ messages in thread
From: Dave Hansen @ 2018-08-27 21:15 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: sean.j.christopherson, nhorman, npmccallum, linux-sgx,
	Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Suresh Siddha,
	Serge Ayoun, open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> +struct sgx_epc_page_ops {
> +	bool (*get)(struct sgx_epc_page *epc_page);
> +	void (*put)(struct sgx_epc_page *epc_page);
> +	bool (*reclaim)(struct sgx_epc_page *epc_page);
> +	void (*block)(struct sgx_epc_page *epc_page);
> +	void (*write)(struct sgx_epc_page *epc_page);
> +};

Why do we need a fancy, slow (retpoline'd) set of function pointers when
we only have one user of these (the SGX driver)?

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-27 18:53 ` [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves Jarkko Sakkinen
@ 2018-08-27 21:41   ` Huang, Kai
  2018-08-28  7:01     ` Jarkko Sakkinen
  2018-09-03 13:53   ` Jann Horn
  2018-09-04 16:05   ` Andy Shevchenko
  2 siblings, 1 reply; 103+ messages in thread
From: Huang, Kai @ 2018-08-27 21:41 UTC (permalink / raw)
  To: jarkko.sakkinen, platform-driver-x86, x86
  Cc: nhorman, linux-kernel, Christopherson, Sean J, tglx,
	suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo, linux-sgx,
	Hansen, Dave

On Mon, 2018-08-27 at 21:53 +0300, Jarkko Sakkinen wrote:
> From: Sean Christopherson <sean.j.christopherson@intel.com>
> 
> Add a function to perform ENCLS(EINIT), which initializes an enclave,
> which can be used by a driver for running enclaves and VMMs.
> 
> Writing the LE hash MSRs is extraordinarily expensive, e.g. 3-4x
> slower
> than normal MSRs, so we use a per-cpu cache to track the last known
> value
> of the MSRs to avoid unnecessarily writing the MSRs with the current
> value.
> 
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> ---
>  arch/x86/include/asm/sgx.h      |  2 +
>  arch/x86/kernel/cpu/intel_sgx.c | 86
> +++++++++++++++++++++++++++++++--
>  2 files changed, 85 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
> index baf30d49b71f..c15c156436be 100644
> --- a/arch/x86/include/asm/sgx.h
> +++ b/arch/x86/include/asm/sgx.h
> @@ -108,6 +108,8 @@ void sgx_free_page(struct sgx_epc_page *page);
>  void sgx_page_reclaimable(struct sgx_epc_page *page);
>  struct page *sgx_get_backing(struct file *file, pgoff_t index);
>  void sgx_put_backing(struct page *backing_page, bool write);
> +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken
> *token,
> +	      struct sgx_epc_page *secs_page, u64 lepubkeyhash[4]);
>  
>  #define ENCLS_FAULT_FLAG 0x40000000UL
>  #define ENCLS_FAULT_FLAG_ASM "$0x40000000"
> diff --git a/arch/x86/kernel/cpu/intel_sgx.c
> b/arch/x86/kernel/cpu/intel_sgx.c
> index 1046478a3ab9..fe25e6805680 100644
> --- a/arch/x86/kernel/cpu/intel_sgx.c
> +++ b/arch/x86/kernel/cpu/intel_sgx.c
> @@ -9,6 +9,7 @@
>  #include <linux/sched/signal.h>
>  #include <linux/shmem_fs.h>
>  #include <linux/slab.h>
> +#include <linux/suspend.h>
>  #include <asm/sgx.h>
>  #include <asm/sgx_pr.h>
>  
> @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);
>  static DEFINE_SPINLOCK(sgx_active_page_list_lock);
>  static struct task_struct *ksgxswapd_tsk;
>  static DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> +static struct notifier_block sgx_pm_notifier;
> +static u64 sgx_pm_cnt;
> +
> +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx MSRs
> for each
> + * CPU. The entries are initialized when they are first used by
> sgx_einit().
> + */
> +struct sgx_lepubkeyhash {
> +	u64 msrs[4];
> +	u64 pm_cnt;

May I ask why do we need pm_cnt here? In fact why do we need suspend
staff (namely, sgx_pm_cnt above, and related code in this patch) here
in this patch? From the patch commit message I don't see why we need PM
staff here. Please give comment why you need PM staff, or you may
consider to split the PM staff to another patch.

> +};
> +
> +static DEFINE_PER_CPU(struct sgx_lepubkeyhash *,
> sgx_lepubkeyhash_cache);
>  
>  /**
>   * sgx_reclaim_pages - reclaim EPC pages from the consumers
> @@ -328,6 +341,54 @@ void sgx_put_backing(struct page *backing_page,
> bool write)
>  }
>  EXPORT_SYMBOL_GPL(sgx_put_backing);
>  
> +/**
> + * sgx_einit - initialize an enclave
> + * @sigstruct:		a pointer to the SIGSTRUCT
> + * @token:		a pointer to the EINITTOKEN
> + * @secs_page:		a pointer to the SECS EPC page
> + * @lepubkeyhash:	the desired value for IA32_SGXLEPUBKEYHASHx
> MSRs
> + *
> + * Try to perform EINIT operation. If the MSRs are writable, they
> are updated
> + * according to @lepubkeyhash.
> + *
> + * Return:
> + *   0 on success,
> + *   -errno on failure
> + *   SGX error code if EINIT fails
> + */
> +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken
> *token,
> +	      struct sgx_epc_page *secs_page, u64 lepubkeyhash[4])
> +{
> +	struct sgx_lepubkeyhash __percpu *cache;
> +	bool cache_valid;
> +	int i, ret;
> +
> +	if (!sgx_lc_enabled)
> +		return __einit(sigstruct, token,
> sgx_epc_addr(secs_page));
> +
> +	cache = per_cpu(sgx_lepubkeyhash_cache, smp_processor_id());
> +	if (!cache) {
> +		cache = kzalloc(sizeof(struct sgx_lepubkeyhash),
> GFP_KERNEL);
> +		if (!cache)
> +			return -ENOMEM;
> +	}

It seems per-cpu variable is a pointer to struct sgx_lepubkeyhash, and
the actual structure is allocated at the first time the function is
called. May I ask when will it be freed? It seems the free is not in
this patch. Or I am misunderstanding something?

> +
> +	cache_valid = cache->pm_cnt == sgx_pm_cnt;
> +	cache->pm_cnt = sgx_pm_cnt;
> +	preempt_disable();
> +	for (i = 0; i < 4; i++) {
> +		if (cache_valid && lepubkeyhash[i] == cache-
> >msrs[i])
> +			continue;
> +
> +		wrmsrl(MSR_IA32_SGXLEPUBKEYHASH0 + i,
> lepubkeyhash[i]);
> +		cache->msrs[i] = lepubkeyhash[i];
> +	}
> +	ret = __einit(sigstruct, token, sgx_epc_addr(secs_page));
> +	preempt_enable();
> +	return ret;
> +}
> +EXPORT_SYMBOL(sgx_einit);
> +
>  static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned
> long index,
>  				    struct sgx_epc_bank *bank)
>  {
> @@ -426,6 +487,15 @@ static __init int sgx_page_cache_init(void)
>  	return 0;
>  }
>  
> +static int sgx_pm_notifier_cb(struct notifier_block *nb, unsigned
> long action,
> +			      void *data)
> +{
> +	if (action == PM_SUSPEND_PREPARE || action ==
> PM_HIBERNATION_PREPARE)
> +		sgx_pm_cnt++;
> +
> +	return NOTIFY_DONE;
> +}
> +
>  static __init int sgx_init(void)
>  {
>  	struct task_struct *tsk;
> @@ -452,20 +522,30 @@ static __init int sgx_init(void)
>  	if (!(fc & FEATURE_CONTROL_SGX_LE_WR))
>  		pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not
> writable\n");
>  
> -	ret = sgx_page_cache_init();
> +	sgx_pm_notifier.notifier_call = sgx_pm_notifier_cb;
> +	ret = register_pm_notifier(&sgx_pm_notifier);
>  	if (ret)
>  		return ret;
>  
> +	ret = sgx_page_cache_init();
> +	if (ret)
> +		goto out_pm;
> +
>  	tsk = kthread_run(ksgxswapd, NULL, "ksgxswapd");
>  	if (IS_ERR(tsk)) {
> -		sgx_page_cache_teardown();
> -		return PTR_ERR(tsk);
> +		ret = PTR_ERR(tsk);
> +		goto out_pcache;
>  	}
>  	ksgxswapd_tsk = tsk;
>  
>  	sgx_enabled = true;
>  	sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR);
>  	return 0;
> +out_pcache:
> +	sgx_page_cache_teardown();

I don't think this particular 2 lines of code of 'out_pcache' case
should be in this patch?

Thanks,
-Kai

> +out_pm:
> +	unregister_pm_notifier(&sgx_pm_notifier);
> +	return ret;
>  }
>  
>  arch_initcall(sgx_init);

^ permalink raw reply	[flat|nested] 103+ messages in thread

* RE: [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features
  2018-08-27 18:53 ` [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features Jarkko Sakkinen
@ 2018-08-28  0:07   ` Huang, Kai
  2018-08-28  7:17     ` Jarkko Sakkinen
  2018-08-31 16:18   ` Dr. Greg
  1 sibling, 1 reply; 103+ messages in thread
From: Huang, Kai @ 2018-08-28  0:07 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: Hansen, Dave, Christopherson, Sean J, nhorman, npmccallum,
	linux-sgx, Kai Huang, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Borislav Petkov, Konrad Rzeszutek Wilk,
	David Woodhouse, open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

> +#define X86_FEATURE_SGX_LC		(16*32+30) /* supports SGX launch
> configuration */

Sorry if it was me who wrote the comment "SGX launch configuration". I think we should just use "SGX launch control". :)

Thanks,
-Kai
> 
>  /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
>  #define X86_FEATURE_OVERFLOW_RECOV	(17*32+ 0) /* MCA overflow
> recovery support */
> --
> 2.17.1


^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-27 21:41   ` Huang, Kai
@ 2018-08-28  7:01     ` Jarkko Sakkinen
  2018-08-29  7:33       ` Huang, Kai
  0 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  7:01 UTC (permalink / raw)
  To: Huang, Kai
  Cc: platform-driver-x86, x86, nhorman, linux-kernel, Christopherson,
	Sean J, tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum,
	mingo, linux-sgx, Hansen, Dave

On Mon, Aug 27, 2018 at 09:41:22PM +0000, Huang, Kai wrote:
> On Mon, 2018-08-27 at 21:53 +0300, Jarkko Sakkinen wrote:
> > From: Sean Christopherson <sean.j.christopherson@intel.com>
> > 
> > Add a function to perform ENCLS(EINIT), which initializes an enclave,
> > which can be used by a driver for running enclaves and VMMs.
> > 
> > Writing the LE hash MSRs is extraordinarily expensive, e.g. 3-4x
> > slower
> > than normal MSRs, so we use a per-cpu cache to track the last known
> > value
> > of the MSRs to avoid unnecessarily writing the MSRs with the current
> > value.
> > 
> > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> > Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> > Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> > ---
> >  arch/x86/include/asm/sgx.h      |  2 +
> >  arch/x86/kernel/cpu/intel_sgx.c | 86
> > +++++++++++++++++++++++++++++++--
> >  2 files changed, 85 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
> > index baf30d49b71f..c15c156436be 100644
> > --- a/arch/x86/include/asm/sgx.h
> > +++ b/arch/x86/include/asm/sgx.h
> > @@ -108,6 +108,8 @@ void sgx_free_page(struct sgx_epc_page *page);
> >  void sgx_page_reclaimable(struct sgx_epc_page *page);
> >  struct page *sgx_get_backing(struct file *file, pgoff_t index);
> >  void sgx_put_backing(struct page *backing_page, bool write);
> > +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken
> > *token,
> > +	      struct sgx_epc_page *secs_page, u64 lepubkeyhash[4]);
> >  
> >  #define ENCLS_FAULT_FLAG 0x40000000UL
> >  #define ENCLS_FAULT_FLAG_ASM "$0x40000000"
> > diff --git a/arch/x86/kernel/cpu/intel_sgx.c
> > b/arch/x86/kernel/cpu/intel_sgx.c
> > index 1046478a3ab9..fe25e6805680 100644
> > --- a/arch/x86/kernel/cpu/intel_sgx.c
> > +++ b/arch/x86/kernel/cpu/intel_sgx.c
> > @@ -9,6 +9,7 @@
> >  #include <linux/sched/signal.h>
> >  #include <linux/shmem_fs.h>
> >  #include <linux/slab.h>
> > +#include <linux/suspend.h>
> >  #include <asm/sgx.h>
> >  #include <asm/sgx_pr.h>
> >  
> > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);
> >  static DEFINE_SPINLOCK(sgx_active_page_list_lock);
> >  static struct task_struct *ksgxswapd_tsk;
> >  static DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > +static struct notifier_block sgx_pm_notifier;
> > +static u64 sgx_pm_cnt;
> > +
> > +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx MSRs
> > for each
> > + * CPU. The entries are initialized when they are first used by
> > sgx_einit().
> > + */
> > +struct sgx_lepubkeyhash {
> > +	u64 msrs[4];
> > +	u64 pm_cnt;
> 
> May I ask why do we need pm_cnt here? In fact why do we need suspend
> staff (namely, sgx_pm_cnt above, and related code in this patch) here
> in this patch? From the patch commit message I don't see why we need PM
> staff here. Please give comment why you need PM staff, or you may
> consider to split the PM staff to another patch.

Refining the commit message probably makes more sense because without PM
code sgx_einit() would be broken. The MSRs have been reset after waking
up.

Some kind of counter is required to keep track of the power cycle. When
going to sleep the sgx_pm_cnt is increased. sgx_einit() compares the
current value of the global count to the value in the cache entry to see
whether we are in a new power cycle.

This brings up one question though: how do we deal with VM host going
to sleep? VM guest would not be aware of this.

I think the best measure would be to add a new parameter to sgx_einit()
that enforces update of the MSRs. The driver can then set this parameter
in the case when sgx_einit() returns SGX_INVALID_LICENSE. This is
coherent because the driver requires writable MSRs. It would not be
coherent to do it directly in the core because KVM does not require
writable MSRs.

> 
> > +};
> > +
> > +static DEFINE_PER_CPU(struct sgx_lepubkeyhash *,
> > sgx_lepubkeyhash_cache);
> >  
> >  /**
> >   * sgx_reclaim_pages - reclaim EPC pages from the consumers
> > @@ -328,6 +341,54 @@ void sgx_put_backing(struct page *backing_page,
> > bool write)
> >  }
> >  EXPORT_SYMBOL_GPL(sgx_put_backing);
> >  
> > +/**
> > + * sgx_einit - initialize an enclave
> > + * @sigstruct:		a pointer to the SIGSTRUCT
> > + * @token:		a pointer to the EINITTOKEN
> > + * @secs_page:		a pointer to the SECS EPC page
> > + * @lepubkeyhash:	the desired value for IA32_SGXLEPUBKEYHASHx
> > MSRs
> > + *
> > + * Try to perform EINIT operation. If the MSRs are writable, they
> > are updated
> > + * according to @lepubkeyhash.
> > + *
> > + * Return:
> > + *   0 on success,
> > + *   -errno on failure
> > + *   SGX error code if EINIT fails
> > + */
> > +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken
> > *token,
> > +	      struct sgx_epc_page *secs_page, u64 lepubkeyhash[4])
> > +{
> > +	struct sgx_lepubkeyhash __percpu *cache;
> > +	bool cache_valid;
> > +	int i, ret;
> > +
> > +	if (!sgx_lc_enabled)
> > +		return __einit(sigstruct, token,
> > sgx_epc_addr(secs_page));
> > +
> > +	cache = per_cpu(sgx_lepubkeyhash_cache, smp_processor_id());
> > +	if (!cache) {
> > +		cache = kzalloc(sizeof(struct sgx_lepubkeyhash),
> > GFP_KERNEL);
> > +		if (!cache)
> > +			return -ENOMEM;
> > +	}
> 
> It seems per-cpu variable is a pointer to struct sgx_lepubkeyhash, and
> the actual structure is allocated at the first time the function is
> called. May I ask when will it be freed? It seems the free is not in
> this patch. Or I am misunderstanding something?

Well, it is part of the core. When the power goes of from the DRAM
banks, everything is wiped out :-)


> 
> > +
> > +	cache_valid = cache->pm_cnt == sgx_pm_cnt;
> > +	cache->pm_cnt = sgx_pm_cnt;
> > +	preempt_disable();
> > +	for (i = 0; i < 4; i++) {
> > +		if (cache_valid && lepubkeyhash[i] == cache-
> > >msrs[i])
> > +			continue;
> > +
> > +		wrmsrl(MSR_IA32_SGXLEPUBKEYHASH0 + i,
> > lepubkeyhash[i]);
> > +		cache->msrs[i] = lepubkeyhash[i];
> > +	}
> > +	ret = __einit(sigstruct, token, sgx_epc_addr(secs_page));
> > +	preempt_enable();
> > +	return ret;
> > +}
> > +EXPORT_SYMBOL(sgx_einit);
> > +
> >  static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned
> > long index,
> >  				    struct sgx_epc_bank *bank)
> >  {
> > @@ -426,6 +487,15 @@ static __init int sgx_page_cache_init(void)
> >  	return 0;
> >  }
> >  
> > +static int sgx_pm_notifier_cb(struct notifier_block *nb, unsigned
> > long action,
> > +			      void *data)
> > +{
> > +	if (action == PM_SUSPEND_PREPARE || action ==
> > PM_HIBERNATION_PREPARE)
> > +		sgx_pm_cnt++;
> > +
> > +	return NOTIFY_DONE;
> > +}
> > +
> >  static __init int sgx_init(void)
> >  {
> >  	struct task_struct *tsk;
> > @@ -452,20 +522,30 @@ static __init int sgx_init(void)
> >  	if (!(fc & FEATURE_CONTROL_SGX_LE_WR))
> >  		pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not
> > writable\n");
> >  
> > -	ret = sgx_page_cache_init();
> > +	sgx_pm_notifier.notifier_call = sgx_pm_notifier_cb;
> > +	ret = register_pm_notifier(&sgx_pm_notifier);
> >  	if (ret)
> >  		return ret;
> >  
> > +	ret = sgx_page_cache_init();
> > +	if (ret)
> > +		goto out_pm;
> > +
> >  	tsk = kthread_run(ksgxswapd, NULL, "ksgxswapd");
> >  	if (IS_ERR(tsk)) {
> > -		sgx_page_cache_teardown();
> > -		return PTR_ERR(tsk);
> > +		ret = PTR_ERR(tsk);
> > +		goto out_pcache;
> >  	}
> >  	ksgxswapd_tsk = tsk;
> >  
> >  	sgx_enabled = true;
> >  	sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR);
> >  	return 0;
> > +out_pcache:
> > +	sgx_page_cache_teardown();
> 
> I don't think this particular 2 lines of code of 'out_pcache' case
> should be in this patch?

Yea, you are right. It cold be implemented already in the earlier patch
(note taken).

> Thanks,
> -Kai

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features
  2018-08-28  0:07   ` Huang, Kai
@ 2018-08-28  7:17     ` Jarkko Sakkinen
  2018-08-29  7:36       ` Huang, Kai
  0 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  7:17 UTC (permalink / raw)
  To: Huang, Kai
  Cc: x86, platform-driver-x86, Hansen, Dave, Christopherson, Sean J,
	nhorman, npmccallum, linux-sgx, Kai Huang, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Borislav Petkov,
	Konrad Rzeszutek Wilk, David Woodhouse,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Tue, Aug 28, 2018 at 12:07:41AM +0000, Huang, Kai wrote:
> > +#define X86_FEATURE_SGX_LC		(16*32+30) /* supports SGX launch
> > configuration */
> 
> Sorry if it was me who wrote the comment "SGX launch configuration". I
> think we should just use "SGX launch control". :)

Not sure if we should change though. The former is more self-explaining,
the latter is "more official".

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX
  2018-08-27 19:39   ` Dave Hansen
@ 2018-08-28  7:23     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  7:23 UTC (permalink / raw)
  To: Dave Hansen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Paolo Bonzini, Radim Krčmář,
	Peter Zijlstra, Borislav Petkov, Greg Kroah-Hartman,
	David Woodhouse, Alexei Starovoitov, Andi Kleen,
	Konrad Rzeszutek Wilk, Ricardo Neri, Kirill A. Shutemov,
	Andy Lutomirski, open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	open list:KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)

On Mon, Aug 27, 2018 at 12:39:36PM -0700, Dave Hansen wrote:
> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> > +	/* Intel SGX features: level 0x00000012 */
> > +	if (c->cpuid_level >= 0x00000012) {
> > +		cpuid(0x00000012, &eax, &ebx, &ecx, &edx);
> > +
> > +		c->x86_capability[CPUID_12_EAX] = eax;
> > +	}
> 
> I've given this specific bit of feedback at least once in the past.
> These patches are not ordered properly.  You introduce this in the next
> patch:
> 
> +#define SGX_CPUID 0x12

Yeah, my mistake probably when squashing fixups.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 13/13] x86/sgx: Driver documentation
  2018-08-27 19:40   ` Randy Dunlap
@ 2018-08-28  7:58     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  7:58 UTC (permalink / raw)
  To: Randy Dunlap
  Cc: x86, platform-driver-x86, dave.hansen, sean.j.christopherson,
	nhorman, npmccallum, linux-sgx, Jonathan Corbet, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, open list:DOCUMENTATION, open list

On Mon, Aug 27, 2018 at 12:40:50PM -0700, Randy Dunlap wrote:
> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> > Documentation of the features of the Software Guard eXtensions used
> > by the Linux kernel and basic design choices for the core and driver
> > and functionality.
> > 
> > Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> 
> Hi,
> 
> Comments inline...
> 
> > ---
> >  Documentation/index.rst         |   1 +
> >  Documentation/x86/intel_sgx.rst | 185 ++++++++++++++++++++++++++++++++
> >  2 files changed, 186 insertions(+)
> >  create mode 100644 Documentation/x86/intel_sgx.rst
> > 
> > diff --git a/Documentation/index.rst b/Documentation/index.rst
> > index 5db7e87c7cb1..1cdc139adb40 100644
> > --- a/Documentation/index.rst
> > +++ b/Documentation/index.rst
> > @@ -104,6 +104,7 @@ implementation.
> >     :maxdepth: 2
> >  
> >     sh/index
> > +   x86/index
> >  
> >  Filesystem Documentation
> >  ------------------------
> > diff --git a/Documentation/x86/intel_sgx.rst b/Documentation/x86/intel_sgx.rst
> > new file mode 100644
> > index 000000000000..f6b7979c41f2
> > --- /dev/null
> > +++ b/Documentation/x86/intel_sgx.rst
> > @@ -0,0 +1,185 @@
> > +===================
> > +Intel(R) SGX driver
> > +===================
> > +
> > +Introduction
> > +============
> > +
> > +Intel(R) SGX is a set of CPU instructions that can be used by applications to
> > +set aside private regions of code and data. The code outside the enclave is
> 
>    set aside private regions of code and data (which are called enclaves). The ...
> 
> > +disallowed to access the memory inside the enclave by the CPU access control.
> > +In a way you can think that SGX provides inverted sandbox. It protects the
> 
>                                    provides an inverted sandbox.
> 
> > +application from a malicious host.
> > +
> > +You can tell if your CPU supports SGX by looking into ``/proc/cpuinfo``:
> > +
> > +	``cat /proc/cpuinfo  | grep sgx``
> 
> or	``grep sgx /proc/cpuinfo``
> ?
> 
> > +
> > +Overview of SGX
> > +===============
> > +
> > +SGX has a set of data structures to maintain information about the enclaves and
> > +their security properties. BIOS reserves a fixed size region of physical memory
> > +for these structures by setting Processor Reserved Memory Range Registers
> > +(PRMRR).
> > +
> > +This memory range is protected from outside access by the CPU and all the data
> > +coming in and out of the CPU package is encrypted by a key that is generated for
> > +each boot cycle.
> > +
> > +Enclaves execute in ring-3 in a special enclave submode using pages from the
> > +reserved memory range. A fixed logical address range for the enclave is reserved
> > +by ENCLS(ECREATE), a leaf instruction used to create enclaves. It is referred in
> 
>                                                                   It is referred to in
> 
> > +the documentation commonly as the ELRANGE.
> > +
> > +Every memory access to the ELRANGE is asserted by the CPU. If the CPU is not
> > +executing in the enclave mode inside the enclave, #GP is raised. On the other
> > +hand enclave code can make memory accesses both inside and outside of the
> > +ELRANGE.
> > +
> > +Enclave can only execute code inside the ELRANGE. Instructions that may cause
> 
>    An enclave can
> or
>    Enclaves can
> 
> > +VMEXIT, IO instructions and instructions that require a privilege change are
> > +prohibited inside the enclave. Interrupts and exceptions always cause enclave
> 
>                                                                    cause the enclave
> 
> > +to exit and jump to an address outside the enclave given when the enclave is
> > +entered by using the leaf instruction ENCLS(EENTER).
> > +
> > +Data types
> > +----------
> > +
> > +The protected memory range contains the following data:
> > +
> > +* **Enclave Page Cache (EPC):** protected pages
> > +* **Enclave Page Cache Map (EPCM):** a database that describes the state of the
> > +  pages and link them to an enclave.
> > +
> > +EPC has a number of different types of pages:
> > +
> > +* **SGX Enclave Control Structure (SECS)**: describes the global
> > +  properties of an enclave.
> > +* **Regular (REG):** code and data pages in the ELRANGE.
> > +* **Thread Control Structure (TCS):** pages that define entry points inside an
> > +  enclave. The enclave can only be entered through these entry points and each
> > +  can host a single hardware thread at a time.
> > +* **Version Array (VA)**: 64-bit version numbers for pages that have been
> > +  swapped outside the enclave. Each page contains 512 version numbers.
> > +
> > +Launch control
> > +--------------
> > +
> > +To launch an enclave, two structures must be provided for ENCLS(EINIT):
> > +
> > +1. **SIGSTRUCT:** signed measurement of the enclave binary.
> 
> what does "signed measurement" mean?

Right, I admit that this looks complete nonsense.

It is SHA256 hash of the construction of the enclave signed with the
private RSA key of the enclave signer (the public key is part of the
SIGSTRUCT).

A measurement is constructed by hashing tags for ECREATE, EADD and
EEXTEND together with those parameters that either define ordinal and
cardinal properties of the enclave associated with the operation and for
each EADD the associated data page is also hashed.

> > +2. **EINITTOKEN:** a cryptographic token CMAC-signed with a AES256-key called
> > +   *launch key*, which is re-generated for each boot cycle.
> > +
> > +The CPU holds a SHA256 hash of a 3072-bit RSA public key inside
> > +IA32_SGXLEPUBKEYHASHn MSRs. Enclaves with a SIGSTRUCT that is signed with this
> > +key do not require a valid EINITTOKEN and can be authorized with special
> > +privileges. One of those privileges is ability to acquire the launch key with
> > +ENCLS(EGETKEY).
> > +
> > +**IA32_FEATURE_CONTROL[17]** is used by the BIOS configure whether
> 
>                                         by the BIOS to configure whether
> 
> > +IA32_SGXLEPUBKEYHASH MSRs are read-only or read-write before locking the
> > +feature control register and handing over control to the operating system.
> > +
> > +Enclave construction
> > +--------------------
> > +
> > +The construction is started by filling out the SECS that contains enclave
> > +address range, privileged attributes and measurement of TCS and REG pages (pages
> 
> what is this "measurement"?  how is it done?

I will update this according the above explanation probably adding
section just for explaining what measurement means as it is a concept
that is cuts through the whole stack.

The CPU calculates it to variable inside the SECS page of the enclave
while you construct the enclave and a signing tool calculates equivalent
value and signs it with the private key (i.e. the signed measurement).

> > +that will be mapped to the address range) among the other things. This structure
> > +is passed out to the ENCLS(ECREATE) together with a physical address of a page
> > +in EPC that will hold the SECS.
> > +
> > +The pages are added with ENCLS(EADD) and measured with ENCLS(EEXTEND) i.e.
> > +SHA256 hash MRENCLAVE residing in the SECS is extended with the page data.
> > +
> > +After all of the pages have been added, the enclave is initialized with
> > +ENCLS(EINIT). ENCLS(INIT) checks that the SIGSTRUCT is signed with the contained
> > +public key. If the given EINITTOKEN has the valid bit set, the CPU checks that
> > +the token is valid (CMAC'd with the launch key). If the token is not valid,
> > +the CPU will check whether the enclave is signed with a key matching to the
> > +IA32_SGXLEPUBKEYHASHn MSRs.
> > +
> > +Swapping pages
> > +--------------
> > +
> > +Enclave pages can be swapped out with ENCLS(EWB) to the unprotected memory. In
> > +addition to the EPC page, ENCLS(EWB) takes in a VA page and address for PCMD
> > +structure (Page Crypto MetaData) as input. The VA page will seal a version
> > +number for the page. PCMD is 128 byte structure that contains tracking
> > +information for the page, most importantly its MAC. With these structures the
> > +enclave is sealed and rollback protected while it resides in the unprotected
> > +memory.
> > +
> > +Before the page can be swapped out it must not have any active TLB references.
> > +ENCLS(EBLOCK) instruction moves a page to the *blocked* state, which means
> > +that no new TLB entries can be created to it by the hardware threads.
> > +
> > +After this a shootdown sequence is started with ENCLS(ETRACK), which sets an
> > +increased counter value to the entering hardware threads. ENCLS(EWB) will
> > +return SGX_NOT_TRACKED error while there are still threads with the earlier
> > +couner value because that means that there might be hardware thread inside
> 
>    counter
> 
> > +the enclave with TLB entries to pages that are to be swapped.
> > +
> > +Kernel internals
> > +================
> > +
> > +Requirements
> > +------------
> > +
> > +Because SGX has an ever evolving and expanding feature set, it's possible for
> > +a BIOS or VMM to configure a system in such a way that not all CPUs are equal,
> > +e.g. where Launch Control is only enabled on a subset of CPUs.  Linux does
> > +*not* support such a heterogeneous system configuration, nor does it even
> > +attempt to play nice in the face of a misconfigured system.  With the exception
> > +of Launch Control's hash MSRs, which can vary per CPU, Linux assumes that all
> > +CPUs have a configuration that is identical to the boot CPU.
> > +
> > +
> > +Roles and responsibilities
> > +--------------------------
> > +
> > +SGX introduces system resources, e.g. EPC memory, that must be accessible to
> > +multiple entities, e.g. the native kernel driver (to expose SGX to userspace)
> > +and KVM (to expose SGX to VMs), ideally without introducing any dependencies
> > +between each SGX entity.  To that end, the kernel owns and manages the shared
> > +system resources, i.e. the EPC and Launch Control MSRs, and defines functions
> > +that provide appropriate access to the shared resources.  SGX support for
> > +user space and VMs is left to the SGX platform driver and KVM respectively.
> 
>    userspace
> (as on the second line of that same paragraph)
> 
> > +
> > +Launching enclaves
> > +------------------
> > +
> > +The current kernel implementation supports only unlocked MSRs i.e.
> > +FEATURE_CONTROL_SGX_LE_WR must be set. The launch is performed by setting the
> > +MSRs to the hash of the public key modulus of the enclave signer, which is one
> > +f the fields in the SIGSTRUCT.
> > +
> > +EPC management
> > +--------------
> > +
> > +Due to the unique requirements for swapping EPC pages, and because EPC pages
> > +(currently) do not have associated page structures, management of the EPC is
> > +not handled by the standard Linux swapper.  SGX directly handles swapping
> > +of EPC pages, including a kthread to initiate reclaim and a rudimentary LRU
> > +mechanism. The consumers of EPC pages, e.g. the SGX driver, are required to
> > +implement function callbacks that can be invoked by the kernel to age,
> > +swap, and/or forcefully reclaim a target EPC page.  In effect, the kernel
> > +controls what happens and when, while the consumers (driver, KVM, etc..) do
> > +the actual work.
> > +
> > +SGX uapi
> > +========
> > +
> > +.. kernel-doc:: drivers/platform/x86/intel_sgx/sgx_ioctl.c
> > +   :functions: sgx_ioc_enclave_create
> > +               sgx_ioc_enclave_add_page
> > +               sgx_ioc_enclave_init
> > +
> > +.. kernel-doc:: arch/x86/include/uapi/asm/sgx.h
> > +
> > +References
> > +==========
> > +
> > +* System Programming Manual: 39.1.4 Intel® SGX Launch Control Configuration
> > 
> 
> HTH.
> -- 

Thank this was really useful feedback.

I've been drowned in SGX long enough to become blind sometimes to what
is not obvious :-)

> ~Randy

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 13/13] x86/sgx: Driver documentation
  2018-08-27 18:53 ` [PATCH v13 13/13] x86/sgx: Driver documentation Jarkko Sakkinen
  2018-08-27 19:40   ` Randy Dunlap
@ 2018-08-28  8:03   ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  8:03 UTC (permalink / raw)
  To: x86, platform-driver-x86
  Cc: dave.hansen, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Jonathan Corbet, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, open list:DOCUMENTATION, open list

On Mon, Aug 27, 2018 at 09:53:34PM +0300, Jarkko Sakkinen wrote:
> Documentation of the features of the Software Guard eXtensions used
> by the Linux kernel and basic design choices for the core and driver
> and functionality.
> 
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>

The short summary should be changed as "SGX documentation".

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 04/13] x86/sgx: Architectural structures
  2018-08-27 19:41   ` Dave Hansen
@ 2018-08-28  8:08     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  8:08 UTC (permalink / raw)
  To: Dave Hansen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Mon, Aug 27, 2018 at 12:41:29PM -0700, Dave Hansen wrote:
> > +/**
> > + * enum sgx_encls_leaves - return codes for ENCLS, ENCLU and ENCLV
> > + * %SGX_SUCCESS:		No error.
> > + * %SGX_INVALID_SIG_STRUCT:	SIGSTRUCT contains an invalid value.
> > + * %SGX_INVALID_ATTRIBUTE:	Enclave is not attempting to access a resource
> > + *				for which it is not authorized.
> > + * %SGX_BLKSTATE:		EPC page is already blocked.
> > + * %SGX_INVALID_MEASUREMENT:	SIGSTRUCT or EINITTOKEN contains an incorrect
> > + *				measurement.
> ...
> > +enum sgx_return_codes {
> > +	SGX_SUCCESS			= 0,
> > +	SGX_INVALID_SIG_STRUCT		= 1,
> > +	SGX_INVALID_ATTRIBUTE		= 2,
> > +	SGX_BLKSTATE			= 3,
> > +	SGX_INVALID_MEASUREMENT		= 4,
> ...
> 
> I don't think I've ever seen this particular method of commenting
> before.  It's rather verbose and duplicates the names twice, which seems
> a bit silly.
> 
> Can you talk a bit about why you chose to do it this way?  I'd
> personally much rather see at least some brief comments inline with the
> definitions.

The reason that I chose this was

  https://www.kernel.org/doc/Documentation/kernel-doc-nano-HOWTO.txt

It is recommended in the "kernel-doc for structs, unions, enums, and
typedefs" section.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 05/13] x86/msr: Add SGX definitions to msr-index.h
  2018-08-27 19:42   ` Dave Hansen
@ 2018-08-28  8:11     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  8:11 UTC (permalink / raw)
  To: Dave Hansen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Haim Cohen, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Borislav Petkov, Konrad Rzeszutek Wilk,
	Tom Lendacky, Paolo Bonzini, David Woodhouse, Greg Kroah-Hartman,
	Janakarajan Natarajan, Matt Turner, Andy Lutomirski,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Mon, Aug 27, 2018 at 12:42:32PM -0700, Dave Hansen wrote:
> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> > @@ -866,10 +867,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
> >  		}
> >  	}
> >  
> > -	/* Intel SGX features: level 0x00000012 */
> > -	if (c->cpuid_level >= 0x00000012) {
> > -		cpuid(0x00000012, &eax, &ebx, &ecx, &edx);
> > -
> > +	/* Intel SGX features */
> > +	if (c->cpuid_level >= SGX_CPUID) {
> > +		cpuid(SGX_CPUID,  &eax, &ebx, &ecx, &edx);
> >  		c->x86_capability[CPUID_12_EAX] = eax;
> >  	}
> 
> This hunk has no apparent connection to the changelog.

Thanks for catching this, the same squashing mistake :-)

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 06/13] x86/sgx: Detect Intel SGX
  2018-08-27 19:53   ` Dave Hansen
@ 2018-08-28  8:28     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  8:28 UTC (permalink / raw)
  To: Dave Hansen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Suresh Siddha, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Serge Ayoun, Rafael J. Wysocki,
	Borislav Petkov, Reinette Chatre, Andi Kleen, Greg Kroah-Hartman,
	Kirill A. Shutemov,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Mon, Aug 27, 2018 at 12:53:59PM -0700, Dave Hansen wrote:
> > +config INTEL_SGX_CORE
> > +	prompt "Intel SGX core functionality"
> > +	def_bool n
> > +	depends on X86_64 && CPU_SUP_INTEL
> > +	help
> > +	Intel Software Guard eXtensions (SGX) is a set of CPU instructions
> > +	that allows ring 3 applications to create enclaves, private regions
> > +	of memory that are protected, by hardware, from unauthorized access
> > +	and/or modification.
> 
> This is a bit comma-crazy.  Also, considering some of our recent CVE
> fun, I'd probably not claim hardware protection. :)

Agreed :)

> Maybe:
> 
> 	Intel Software Guard eXtensions (SGX) CPU feature that allows
> 	ring 3 applications to create enclaves: private regions
> 	of memory that are architecturally protected from unauthorized
> 	access and/or modification.

Yeah, looks way more better structured.

> > +	This option enables kernel recognition of SGX, high-level management
> > +	of the Enclave Page Cache (EPC), tracking and writing of SGX Launch
> > +	Enclave Hash MSRs, and allows for virtualization of SGX via KVM. By
> > +	iteslf, this option does not provide SGX support to userspace.
> 
> itself
> 
> 
> > diff --git a/arch/x86/include/asm/sgx_pr.h b/arch/x86/include/asm/sgx_pr.h
> > new file mode 100644
> > index 000000000000..c68578127620
> > --- /dev/null
> > +++ b/arch/x86/include/asm/sgx_pr.h
> > @@ -0,0 +1,13 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
> > +// Copyright(c) 2016-17 Intel Corporation.
> > +
> > +#ifndef _ASM_X86_SGX_PR_H
> > +#define _ASM_X86_SGX_PR_H
> > +
> > +#include <linux/printk.h>
> > +#include <linux/ratelimit.h>
> > +
> > +#undef pr_fmt
> > +#define pr_fmt(fmt) "sgx: " fmt
> > +
> > +#endif /* _ASM_X86_SGX_PR_H */
> 
> I don't think this belongs in a generic header.  Generally, we do the
> pr_fmt stuff in .c files, not in headers.  If someone includes this
> header directly or indirectly, they'll get a big surprise.
> 
> If you *must* have this in a .h file, put it in
> arch/x86/kernel/cpu/intel_sgx.h or something and #include "intel_sgx.h"
> in all the .c files where you want this.

I think for intel_sgx.c (the core part) we could just manually add the
"sgx:" prefix because there are only few log messages. I would move the
definition to drivers/platform/x86/intel_sgx/sgx.h because the prefix
makes sense for all .c files there AFAIK.

> > +static __init int sgx_init(void)
> > +{
> > +	unsigned long fc;
> > +
> > +	if (!boot_cpu_has(X86_FEATURE_SGX))
> > +		return false;
> > +
> > +	if (!boot_cpu_has(X86_FEATURE_SGX1))
> > +		return false;
> > +
> > +	rdmsrl(MSR_IA32_FEATURE_CONTROL, fc);
> > +	if (!(fc & FEATURE_CONTROL_LOCKED)) {
> > +		pr_info("IA32_FEATURE_CONTROL MSR is not locked\n");
> > +		return false;
> > +	}
> 
> This is a rather crummy error message.  Doesn't this keep sgx from
> initializing?  Would something like this be more informative?
> 
> 	pr_info("failed init: IA32_FEATURE_CONTROL MSR not locked\n");

What about:

pr_err(FW_BUG "IA32_FEATURE_CONTROL MSR not locked\n");

> > +	if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) {
> > +		pr_info("disabled by the firmware\n");
> > +		return false;
> > +	}
> > +
> > +	if (!(fc & FEATURE_CONTROL_SGX_LE_WR))
> > +		pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not writable\n");
> 
> How about something that might help an end user?  Perhaps:
> 
> 	pr_warn("launch configuration not available\n");

I think this message is a false flag here in the first place as KVM does
not require writable MSRs. It really should be moved to the driver.

> > +	sgx_enabled = true;
> > +	sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR);
> > +	return 0;
> > +}
> > +
> > +arch_initcall(sgx_init);
> > 
> 
> 

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-27 21:15   ` Dave Hansen
@ 2018-08-28  8:35     ` Jarkko Sakkinen
  2018-08-28 14:07       ` Dave Hansen
  0 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  8:35 UTC (permalink / raw)
  To: Dave Hansen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Mon, Aug 27, 2018 at 02:15:34PM -0700, Dave Hansen wrote:
> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> > +struct sgx_epc_page_ops {
> > +	bool (*get)(struct sgx_epc_page *epc_page);
> > +	void (*put)(struct sgx_epc_page *epc_page);
> > +	bool (*reclaim)(struct sgx_epc_page *epc_page);
> > +	void (*block)(struct sgx_epc_page *epc_page);
> > +	void (*write)(struct sgx_epc_page *epc_page);
> > +};
> 
> Why do we need a fancy, slow (retpoline'd) set of function pointers when
> we only have one user of these (the SGX driver)?

KVM has its own implementation for these operations.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-27 21:14   ` Dave Hansen
@ 2018-08-28  8:36     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28  8:36 UTC (permalink / raw)
  To: Dave Hansen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Mon, Aug 27, 2018 at 02:14:24PM -0700, Dave Hansen wrote:
> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> > +enum sgx_alloc_flags {
> > +	SGX_ALLOC_ATOMIC	= BIT(0),
> > +};
> 
> Doing this with enums is unprecedented IMNHO.  Why are you doing it this
> way for simple, one-off constants?

I'll change it to bool, thanks.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX
  2018-08-27 18:53 ` [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX Jarkko Sakkinen
  2018-08-27 19:39   ` Dave Hansen
@ 2018-08-28 10:21   ` Borislav Petkov
  2018-08-28 10:38     ` Jarkko Sakkinen
  1 sibling, 1 reply; 103+ messages in thread
From: Borislav Petkov @ 2018-08-28 10:21 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: x86, platform-driver-x86, dave.hansen, sean.j.christopherson,
	nhorman, npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Paolo Bonzini, Radim Krčmář,
	Peter Zijlstra, Greg Kroah-Hartman, David Woodhouse,
	Alexei Starovoitov, Andi Kleen, Konrad Rzeszutek Wilk,
	Ricardo Neri, Kirill A. Shutemov, Andy Lutomirski,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	open list:KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)

On Mon, Aug 27, 2018 at 09:53:24PM +0300, Jarkko Sakkinen wrote:
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 7bb647f57d42..4af60a0fdb20 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -13,7 +13,7 @@
>  /*
>   * Defines x86 CPU feature bits
>   */
> -#define NCAPINTS			19	   /* N 32-bit words worth of info */
> +#define NCAPINTS			20	   /* N 32-bit words worth of info */
>  #define NBUGINTS			1	   /* N 32-bit bug flags */
>  
>  /*
> @@ -349,6 +349,12 @@
>  #define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
>  #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */
>  
> +/* Intel SGX CPU features, CPUID level 0x000000012:0 (EAX), word 19 */
> +#define X86_FEATURE_SGX1		(19*32+ 0) /* SGX1 leaf functions */
> +#define X86_FEATURE_SGX2		(19*32+ 1) /* SGX2 leaf functions */
> +#define X86_FEATURE_SGX_ENCLV		(19*32+ 5) /* SGX ENCLV instruction, leafs E[INC|DEC]VIRTCHILD, ESETCONTEXT */
> +#define X86_FEATURE_SGX_ENCLS_C		(19*32+ 6) /* SGX ENCLS leafs ERDINFO, ETRACK, ELDBC and ELDUC */

No need to add a whole new ->x86_capability member for 4 bits - just add
those bits to leaf 8 where the artificial virtualization flags are -
there's some room there.

Thx.

-- 
Regards/Gruss,
    Boris.

SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
-- 

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-08-27 21:07   ` Dave Hansen
@ 2018-08-28 10:30     ` Jarkko Sakkinen
  2018-08-28 16:53       ` Dave Hansen
  0 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28 10:30 UTC (permalink / raw)
  To: Dave Hansen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Serge Ayoun, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Mon, Aug 27, 2018 at 02:07:53PM -0700, Dave Hansen wrote:
> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> > Add data structures to track Enclave Page Cache (EPC) pages.  EPC is
> > divided into multiple banks (1-N) of which addresses and sizes can be
> > enumerated with CPUID by the OS.
> > 
> > On NUMA systems a node can have at most bank. A bank can be at most part of
> > two nodes. SGX supports both nodes with a single memory controller and also
> > sub-cluster nodes with severals memory controllers on a single die.
> > 
> > Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> > Co-developed-by: Serge Ayoun <serge.ayoun@intel.com>
> > Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
> > Signed-off-by: Serge Ayoun <serge.ayoun@intel.com>
> > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> > ---
> >  arch/x86/include/asm/sgx.h      |  60 ++++++++++++++++++
> >  arch/x86/kernel/cpu/intel_sgx.c | 106 +++++++++++++++++++++++++++++++-
> >  2 files changed, 164 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
> > index 2130e639ab49..17b7b3aa66bf 100644
> > --- a/arch/x86/include/asm/sgx.h
> > +++ b/arch/x86/include/asm/sgx.h
> > @@ -4,9 +4,69 @@
> >  #ifndef _ASM_X86_SGX_H
> >  #define _ASM_X86_SGX_H
> >  
> > +#include <linux/bitops.h>
> > +#include <linux/err.h>
> > +#include <linux/rwsem.h>
> >  #include <linux/types.h>
> > +#include <asm/sgx_arch.h>
> > +#include <asm/asm.h>
> > +
> > +#define SGX_MAX_EPC_BANKS 8
> 
> This is _still_ missing a meaningful description of what a bank is and
> whether it is a hardware or software structure.
> 
> It would also help us to determine whether your bit packing below is
> really required.

I think a better name would be EPC section as this is what the SDM uses
in the Table 3-8 when describing subleaves of EAX=0x12 (SGX specific
leaf) starting from ECX=0x02. It is a software structure that contains
the information given by these subleaves.

These sections constitute the physical pages that are part of the EPC.

> > +struct sgx_epc_page {
> > +	unsigned long desc;
> > +	struct list_head list;
> > +};
> > +
> > +struct sgx_epc_bank {
> > +	unsigned long pa;
> > +	void *va;
> > +	unsigned long size;
> 
> Please add units.  size could be bytes or pages, or who knows what.  I
> can't tell you how many bugs I've tripped over in the past from simple
> unit conversions

Will do.

> > +	struct sgx_epc_page *pages_data;
> > +	struct sgx_epc_page **pages;
> > +	unsigned long free_cnt;
> > +	spinlock_t lock;
> > +};
> >  
> >  extern bool sgx_enabled;
> >  extern bool sgx_lc_enabled;
> > +extern struct sgx_epc_bank sgx_epc_banks[SGX_MAX_EPC_BANKS];
> > +
> > +/*
> > + * enum sgx_epc_page_desc - defines bits and masks for an EPC page's desc
> 
> Why are you bothering packing these bits?  This seems a rather
> convoluted way to store two integers.

To keep struct sgx_epc_page 64 bytes.

> > +static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned long index,
> > +				    struct sgx_epc_bank *bank)
> > +{
> > +	unsigned long nr_pages = size >> PAGE_SHIFT;
> > +	struct sgx_epc_page *pages_data;
> > +	unsigned long i;
> > +	void *va;
> > +
> > +	va = ioremap_cache(addr, size);
> > +	if (!va)
> > +		return -ENOMEM;
> > +
> > +	pages_data = kcalloc(nr_pages, sizeof(struct sgx_epc_page), GFP_KERNEL);
> > +	if (!pages_data)
> > +		goto out_iomap;
> 
> This looks like you're roughly limited by the page allocator to a bank
> size of ~1.4GB which seems kinda small.  Is this really OK?

Where does this limitation come from?

> 
> > +	bank->pages = kcalloc(nr_pages, sizeof(struct sgx_epc_page *),
> > +			      GFP_KERNEL);
> > +	if (!bank->pages)
> > +		goto out_pdata;
> > +
> > +	for (i = 0; i < nr_pages; i++) {
> > +		bank->pages[i] = &pages_data[i];
> > +		bank->pages[i]->desc = (addr + (i << PAGE_SHIFT)) | index;
> > +	}
> > +
> > +	bank->pa = addr;
> > +	bank->size = size;
> > +	bank->va = va;
> > +	bank->free_cnt = nr_pages;
> > +	bank->pages_data = pages_data;
> > +	spin_lock_init(&bank->lock);
> > +	return 0;
> > +out_pdata:
> > +	kfree(pages_data);
> > +out_iomap:
> > +	iounmap(va);
> > +	return -ENOMEM;
> > +}
> > +
> > +static __init void sgx_page_cache_teardown(void)
> > +{
> > +	struct sgx_epc_bank *bank;
> > +	int i;
> > +
> > +	for (i = 0; i < sgx_nr_epc_banks; i++) {
> > +		bank = &sgx_epc_banks[i];
> > +		iounmap((void *)bank->va);
> > +		kfree(bank->pages);
> > +		kfree(bank->pages_data);
> > +	}
> > +}
> > +
> > +static inline u64 sgx_combine_bank_regs(u64 low, u64 high)
> > +{
> > +	return (low & 0xFFFFF000) + ((high & 0xFFFFF) << 32);
> > +}
> 
> -ENOCOMMENT for a rather weird looking calculation

Yea, totally agreed... I'll think about how to make this cleaner. Maybe
it would be anyway better idea to open code this to the call sites and
explain the calculation in a comment.

> > +static __init int sgx_page_cache_init(void)
> > +{
> > +	u32 eax, ebx, ecx, edx;
> > +	u64 pa, size;
> > +	int ret;
> > +	int i;
> > +
> > +	for (i = 0; i < SGX_MAX_EPC_BANKS; i++) {
> > +		cpuid_count(SGX_CPUID, 2 + i, &eax, &ebx, &ecx, &edx);
> > +		if (!(eax & 0xF))
> > +			break;
> 
> So, we have random data coming out of a random CPUID leaf being called
> 'eax' and then being tested against a random hard-coded mask.  This
> seems rather unfortunate for someone trying to understand the code.  Can
> we do better?

Should probably do something along the lines:

#define SGX_CPUID_SECTION(i) (2 + (i))

enum sgx_section {
	SGX_CPUID_SECTION_INVALID	= 0x00,
	SGX_CPUID_SECTION_VALID		= 0x1B,
	SGX_CPUID_SECTION_MASK		= 0xFF,
};


for (i = 0; i < SGX_MAX_EPC_BANKS; i++) {
	cpuid_count(SGX_CPUID, SGX_CPUID_SECTION(i), &eax, &ebx, &ecx, &edx);

	section = eax & SGX_SECTION_MASK;
	if (section != SGX_CPUID_SECTION_VALID) {
		if (section != SGX_CPUID_SECTION_INVALID) {
			/* Maybe a warning here for any other value as
			 * they are reserved according to the SDM?
			 */
		}

		continue;
	}

	/* ... */
}

> > +		pa = sgx_combine_bank_regs(eax, ebx);
> > +		size = sgx_combine_bank_regs(ecx, edx);
> > +		pr_info("EPC bank 0x%llx-0x%llx\n", pa, pa + size - 1);
> > +		ret = sgx_init_epc_bank(pa, size, i, &sgx_epc_banks[i]);
> > +		if (ret) {
> > +			sgx_page_cache_teardown();
> > +			return ret;
> > +		}
> 
> So if one bank fails, we tear down all banks, yet leave sgx_nr_epc_banks
> incremented?  That sounds troublesome.

It is. Thanks for spotting that out.

> > +		sgx_nr_epc_banks++;
> > +	}
> > +
> > +	if (!sgx_nr_epc_banks) {
> > +		pr_err("There are zero EPC banks.\n");
> > +		return -ENODEV;
> > +	}
> > +
> > +	return 0;
> > +}
> 
> Does this support hot-addition of a bank?  If not, why not?

This is the DSDT for this data from my GLK NUC:

    Scope (_SB)
    {
        Device (EPC)
        {
            Name (_HID, EisaId ("INT0E0C"))  // _HID: Hardware ID
            Name (_STR, Unicode ("Enclave Page Cache 1.0"))  // _STR: Description String
            Name (_MLS, Package (0x01)  // _MLS: Multiple Language String
            {
                Package (0x02)
                {
                    "en", 
                    Unicode ("Enclave Page Cache 1.0")
                }
            })
            Name (RBUF, ResourceTemplate ()
            {
                QWordMemory (ResourceConsumer, PosDecode, MinNotFixed, MaxNotFixed, NonCacheable, ReadWrite,
                    0x0000000000000000, // Granularity
                    0x0000000000000000, // Range Minimum
                    0x0000000000000000, // Range Maximum
                    0x0000000000000000, // Translation Offset
                    0x0000000000000001, // Length
                    ,, _Y18, AddressRangeMemory, TypeStatic)
            })
            Method (_CRS, 0, NotSerialized)  // _CRS: Current Resource Settings
            {
                CreateQWordField (RBUF, \_SB.EPC._Y18._MIN, EMIN)  // _MIN: Minimum Base Address
                CreateQWordField (RBUF, \_SB.EPC._Y18._MAX, EMAX)  // _MAX: Maximum Base Address
                CreateQWordField (RBUF, \_SB.EPC._Y18._LEN, ELEN)  // _LEN: Length
                EMIN = EMNA /* External reference */
                ELEN = ELNG /* External reference */
                EMAX = ((EMNA + ELNG) - One)
                Return (RBUF) /* \_SB_.EPC_.RBUF */
            }

            Method (_STA, 0, NotSerialized)  // _STA: Status
            {
                If ((EPCS != Zero))
                {
                    Return (0x0F)
                }

                Return (Zero)
            }
        }
    }

I'm not aware that we would have an ACPI specification for SGX so this
is all I have at the moment (does not show any ACPI event for
hotplugging).

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX
  2018-08-28 10:21   ` Borislav Petkov
@ 2018-08-28 10:38     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-28 10:38 UTC (permalink / raw)
  To: Borislav Petkov, '
  Cc: x86, platform-driver-x86, dave.hansen, sean.j.christopherson,
	nhorman, npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Paolo Bonzini, Radim Krčmář,
	Peter Zijlstra, Greg Kroah-Hartman, David Woodhouse,
	Alexei Starovoitov, Andi Kleen, Konrad Rzeszutek Wilk,
	Ricardo Neri, Kirill A. Shutemov, Andy Lutomirski,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	open list:KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)

On Tue, Aug 28, 2018 at 12:21:40PM +0200, Borislav Petkov wrote:
> On Mon, Aug 27, 2018 at 09:53:24PM +0300, Jarkko Sakkinen wrote:
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index 7bb647f57d42..4af60a0fdb20 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -13,7 +13,7 @@
> >  /*
> >   * Defines x86 CPU feature bits
> >   */
> > -#define NCAPINTS			19	   /* N 32-bit words worth of info */
> > +#define NCAPINTS			20	   /* N 32-bit words worth of info */
> >  #define NBUGINTS			1	   /* N 32-bit bug flags */
> >  
> >  /*
> > @@ -349,6 +349,12 @@
> >  #define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
> >  #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */
> >  
> > +/* Intel SGX CPU features, CPUID level 0x000000012:0 (EAX), word 19 */
> > +#define X86_FEATURE_SGX1		(19*32+ 0) /* SGX1 leaf functions */
> > +#define X86_FEATURE_SGX2		(19*32+ 1) /* SGX2 leaf functions */
> > +#define X86_FEATURE_SGX_ENCLV		(19*32+ 5) /* SGX ENCLV instruction, leafs E[INC|DEC]VIRTCHILD, ESETCONTEXT */
> > +#define X86_FEATURE_SGX_ENCLS_C		(19*32+ 6) /* SGX ENCLS leafs ERDINFO, ETRACK, ELDBC and ELDUC */
> 
> No need to add a whole new ->x86_capability member for 4 bits - just add
> those bits to leaf 8 where the artificial virtualization flags are -
> there's some room there.
> 
> Thx.

Roger.

> 
> -- 
> Regards/Gruss,
>     Boris.
> 
> SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
> -- 

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-28  8:35     ` Jarkko Sakkinen
@ 2018-08-28 14:07       ` Dave Hansen
  2018-08-28 21:22         ` Sean Christopherson
  0 siblings, 1 reply; 103+ messages in thread
From: Dave Hansen @ 2018-08-28 14:07 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On 08/28/2018 01:35 AM, Jarkko Sakkinen wrote:
> On Mon, Aug 27, 2018 at 02:15:34PM -0700, Dave Hansen wrote:
>> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
>>> +struct sgx_epc_page_ops {
>>> +	bool (*get)(struct sgx_epc_page *epc_page);
>>> +	void (*put)(struct sgx_epc_page *epc_page);
>>> +	bool (*reclaim)(struct sgx_epc_page *epc_page);
>>> +	void (*block)(struct sgx_epc_page *epc_page);
>>> +	void (*write)(struct sgx_epc_page *epc_page);
>>> +};
>> Why do we need a fancy, slow (retpoline'd) set of function pointers when
>> we only have one user of these (the SGX driver)?
> KVM has its own implementation for these operations.

That belongs in the changelog.

Also, where is the implementation?  How can we assess this code that was
built to create an abstraction without both of the users?

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-08-28 10:30     ` Jarkko Sakkinen
@ 2018-08-28 16:53       ` Dave Hansen
  2018-08-28 21:34         ` Sean Christopherson
  2018-08-31 11:10         ` Jarkko Sakkinen
  0 siblings, 2 replies; 103+ messages in thread
From: Dave Hansen @ 2018-08-28 16:53 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Serge Ayoun, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

>>>  extern bool sgx_enabled;
>>>  extern bool sgx_lc_enabled;
>>> +extern struct sgx_epc_bank sgx_epc_banks[SGX_MAX_EPC_BANKS];
>>> +
>>> +/*
>>> + * enum sgx_epc_page_desc - defines bits and masks for an EPC page's desc
>>
>> Why are you bothering packing these bits?  This seems a rather
>> convoluted way to store two integers.
> 
> To keep struct sgx_epc_page 64 bytes.

It's a list_head and a ulong now.  That doesn't add up to 64.

If you properly describe the bounds and limits of banks we can possibly
help you find a nice solution.  As it stands, they are totally opaque
and we have no idea what is going on.

>>> +static __init int sgx_init_epc_bank(u64 addr, u64 size, unsigned long index,
>>> +				    struct sgx_epc_bank *bank)
>>> +{
>>> +	unsigned long nr_pages = size >> PAGE_SHIFT;
>>> +	struct sgx_epc_page *pages_data;
>>> +	unsigned long i;
>>> +	void *va;
>>> +
>>> +	va = ioremap_cache(addr, size);
>>> +	if (!va)
>>> +		return -ENOMEM;
>>> +
>>> +	pages_data = kcalloc(nr_pages, sizeof(struct sgx_epc_page), GFP_KERNEL);
>>> +	if (!pages_data)
>>> +		goto out_iomap;
>>
>> This looks like you're roughly limited by the page allocator to a bank
>> size of ~1.4GB which seems kinda small.  Is this really OK?
> 
> Where does this limitation come from?

The page allocator can only do 4MB at a time.  Using your 64 byte
numbers: 4MB/64 = 64k sgx_epc_pages.  64k*PAGE_SIZE = 256MB.  So you can
only handle 256MB banks with this code.

BTW, if you only have 64k worth of pages, you can use a u16 for the index.

>>> +	u32 eax, ebx, ecx, edx;
>>> +	u64 pa, size;
>>> +	int ret;
>>> +	int i;
>>> +
>>> +	for (i = 0; i < SGX_MAX_EPC_BANKS; i++) {
>>> +		cpuid_count(SGX_CPUID, 2 + i, &eax, &ebx, &ecx, &edx);
>>> +		if (!(eax & 0xF))
>>> +			break;
>>
>> So, we have random data coming out of a random CPUID leaf being called
>> 'eax' and then being tested against a random hard-coded mask.  This
>> seems rather unfortunate for someone trying to understand the code.  Can
>> we do better?
> 
> Should probably do something along the lines:
> 
> #define SGX_CPUID_SECTION(i) (2 + (i))
> 
> enum sgx_section {
> 	SGX_CPUID_SECTION_INVALID	= 0x00,
> 	SGX_CPUID_SECTION_VALID		= 0x1B,
> 	SGX_CPUID_SECTION_MASK		= 0xFF,
> };

Plus comments, that would be nice.

>>> +		sgx_nr_epc_banks++;
>>> +	}
>>> +
>>> +	if (!sgx_nr_epc_banks) {
>>> +		pr_err("There are zero EPC banks.\n");
>>> +		return -ENODEV;
>>> +	}
>>> +
>>> +	return 0;
>>> +}
>>
>> Does this support hot-addition of a bank?  If not, why not?
...
> I'm not aware that we would have an ACPI specification for SGX so this
> is all I have at the moment (does not show any ACPI event for
> hotplugging).

So you're saying the one platform you looked at don't support hotplug.
I was looking for a more broad statement about SGX.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-28 14:07       ` Dave Hansen
@ 2018-08-28 21:22         ` Sean Christopherson
  2018-08-28 21:26           ` Dave Hansen
  2018-08-31 11:22           ` Jarkko Sakkinen
  0 siblings, 2 replies; 103+ messages in thread
From: Sean Christopherson @ 2018-08-28 21:22 UTC (permalink / raw)
  To: Dave Hansen
  Cc: Jarkko Sakkinen, x86, platform-driver-x86, nhorman, npmccallum,
	linux-sgx, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Tue, Aug 28, 2018 at 07:07:33AM -0700, Dave Hansen wrote:
> On 08/28/2018 01:35 AM, Jarkko Sakkinen wrote:
> > On Mon, Aug 27, 2018 at 02:15:34PM -0700, Dave Hansen wrote:
> >> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> >>> +struct sgx_epc_page_ops {
> >>> +	bool (*get)(struct sgx_epc_page *epc_page);
> >>> +	void (*put)(struct sgx_epc_page *epc_page);
> >>> +	bool (*reclaim)(struct sgx_epc_page *epc_page);
> >>> +	void (*block)(struct sgx_epc_page *epc_page);
> >>> +	void (*write)(struct sgx_epc_page *epc_page);
> >>> +};
> >> Why do we need a fancy, slow (retpoline'd) set of function pointers when
> >> we only have one user of these (the SGX driver)?
> > KVM has its own implementation for these operations.
> 
> That belongs in the changelog.
> 
> Also, where is the implementation?  How can we assess this code that was
> built to create an abstraction without both of the users?

I can provide an early preview of the KVM reclaim code, but honestly
I think that would do more harm than good.  The VMX architecture for
EPC reclaim is complex, even for SGX standards.  Opening that can of
worms would likely derail this discussion.  That being said, this
abstraction isn't exactly what KVM will need, but it's pretty close
and gives us something to build on.

Regardless, this layer of indirection is justifiable even with a
single implementation.  Reclaiming an EPC page is not a simple matter
of copying the data somewhere else and marking the page not present.
Actual eviction requires a reference to the Secure Enclave Control
Structure (SECS) of the enclave that owns the page.  Software needs
to ensure it doesn't violate the hardware-enforced access rules, e.g.
most reclaim activites need to be done under a per-enclave lock.
Not all pages have the same reclaim rules, e.g. an SECS can only
be reclaimed after all its child pages have reclaimed, a VA page
doesn't need to be blocked, etc...  And the list goes on...

All of the tracking metadata and logic about what can be evicted when
resides in the driver component[1], e.g. the core SGX code doesn't
even have a software representation of an enclave.  Alternatively the
driver could provide a single "do_reclaim" function if we wanted to
avoid a fancy abstraction layer, and in fact that's how I initially
implemented the abstraction, but that approach has it's own warts and
in a lot of ways makes the end result more complex.

Ultimately, moving pages in/out of the EPC is so abysmally slow that
the raw performance of software is almost completely irrelevant.  The
algorithms certainly matter, but optimizing away things like function
pointers definitely takes a back seat to just about everything else.

[1] Early versions of SGX support tried to put all EPC management in
    the driver, but that approach caused major problems for KVM (even
    without reclaim support) and received a less than enthusiastic
    response from the community.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-28 21:22         ` Sean Christopherson
@ 2018-08-28 21:26           ` Dave Hansen
  2018-08-28 21:52             ` Sean Christopherson
  2018-08-31 11:22           ` Jarkko Sakkinen
  1 sibling, 1 reply; 103+ messages in thread
From: Dave Hansen @ 2018-08-28 21:26 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Jarkko Sakkinen, x86, platform-driver-x86, nhorman, npmccallum,
	linux-sgx, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On 08/28/2018 02:22 PM, Sean Christopherson wrote:
> On Tue, Aug 28, 2018 at 07:07:33AM -0700, Dave Hansen wrote:
>> On 08/28/2018 01:35 AM, Jarkko Sakkinen wrote:
>>> On Mon, Aug 27, 2018 at 02:15:34PM -0700, Dave Hansen wrote:
>>>> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
>>>>> +struct sgx_epc_page_ops {
>>>>> +	bool (*get)(struct sgx_epc_page *epc_page);
>>>>> +	void (*put)(struct sgx_epc_page *epc_page);
>>>>> +	bool (*reclaim)(struct sgx_epc_page *epc_page);
>>>>> +	void (*block)(struct sgx_epc_page *epc_page);
>>>>> +	void (*write)(struct sgx_epc_page *epc_page);
>>>>> +};
>>>> Why do we need a fancy, slow (retpoline'd) set of function pointers when
>>>> we only have one user of these (the SGX driver)?
>>> KVM has its own implementation for these operations.
>>
>> That belongs in the changelog.
>>
>> Also, where is the implementation?  How can we assess this code that was
>> built to create an abstraction without both of the users?
> 
> I can provide an early preview of the KVM reclaim code, but honestly
> I think that would do more harm than good.  The VMX architecture for
> EPC reclaim is complex, even for SGX standards.  Opening that can of
> worms would likely derail this discussion.  That being said, this
> abstraction isn't exactly what KVM will need, but it's pretty close
> and gives us something to build on.

Please remove the abstraction code.  We don't introduce infrastructure
which no one will use.



^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-08-28 16:53       ` Dave Hansen
@ 2018-08-28 21:34         ` Sean Christopherson
  2018-08-31 11:13           ` Jarkko Sakkinen
  2018-08-31 11:10         ` Jarkko Sakkinen
  1 sibling, 1 reply; 103+ messages in thread
From: Sean Christopherson @ 2018-08-28 21:34 UTC (permalink / raw)
  To: Dave Hansen
  Cc: Jarkko Sakkinen, x86, platform-driver-x86, nhorman, npmccallum,
	linux-sgx, Serge Ayoun, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Tue, Aug 28, 2018 at 09:53:11AM -0700, Dave Hansen wrote:
> >>> +		sgx_nr_epc_banks++;
> >>> +	}
> >>> +
> >>> +	if (!sgx_nr_epc_banks) {
> >>> +		pr_err("There are zero EPC banks.\n");
> >>> +		return -ENODEV;
> >>> +	}
> >>> +
> >>> +	return 0;
> >>> +}
> >>
> >> Does this support hot-addition of a bank?  If not, why not?
> ...
> > I'm not aware that we would have an ACPI specification for SGX so this
> > is all I have at the moment (does not show any ACPI event for
> > hotplugging).
> 
> So you're saying the one platform you looked at don't support hotplug.
> I was looking for a more broad statement about SGX.

Hardware doesn't support hotplug of EPC as the EPC size and location
is locked during activation of SGX.  And IIRC, activation of SGX must
be synchronized across all CPUs in a multi-socket platform, e.g. you
can't late-enable SGX on a socket and due hotplugging that way.

In a virtualized environment there are no such restrictions.  I am not
aware of any explicit requirements or use cases for supporting hotplug
of EPC, but that's probably only because virtualization of SGX is
fairly nascent.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-28 21:26           ` Dave Hansen
@ 2018-08-28 21:52             ` Sean Christopherson
  0 siblings, 0 replies; 103+ messages in thread
From: Sean Christopherson @ 2018-08-28 21:52 UTC (permalink / raw)
  To: Dave Hansen
  Cc: Jarkko Sakkinen, x86, platform-driver-x86, nhorman, npmccallum,
	linux-sgx, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Tue, Aug 28, 2018 at 02:26:36PM -0700, Dave Hansen wrote:
> On 08/28/2018 02:22 PM, Sean Christopherson wrote:
> > On Tue, Aug 28, 2018 at 07:07:33AM -0700, Dave Hansen wrote:
> >> On 08/28/2018 01:35 AM, Jarkko Sakkinen wrote:
> >>> On Mon, Aug 27, 2018 at 02:15:34PM -0700, Dave Hansen wrote:
> >>>> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> >>>>> +struct sgx_epc_page_ops {
> >>>>> +	bool (*get)(struct sgx_epc_page *epc_page);
> >>>>> +	void (*put)(struct sgx_epc_page *epc_page);
> >>>>> +	bool (*reclaim)(struct sgx_epc_page *epc_page);
> >>>>> +	void (*block)(struct sgx_epc_page *epc_page);
> >>>>> +	void (*write)(struct sgx_epc_page *epc_page);
> >>>>> +};
> >>>> Why do we need a fancy, slow (retpoline'd) set of function pointers when
> >>>> we only have one user of these (the SGX driver)?
> >>> KVM has its own implementation for these operations.
> >>
> >> That belongs in the changelog.
> >>
> >> Also, where is the implementation?  How can we assess this code that was
> >> built to create an abstraction without both of the users?
> > 
> > I can provide an early preview of the KVM reclaim code, but honestly
> > I think that would do more harm than good.  The VMX architecture for
> > EPC reclaim is complex, even for SGX standards.  Opening that can of
> > worms would likely derail this discussion.  That being said, this
> > abstraction isn't exactly what KVM will need, but it's pretty close
> > and gives us something to build on.
> 
> Please remove the abstraction code.  We don't introduce infrastructure
> which no one will use.

The infrastructure is used in the sense that it allows us to split the
userspace-facing code, i.e. the driver, into a separate module.  This
in turn allows virtualization of SGX without having to load the driver
or building it in the first place, e.g. to virtualize SGX on a system
that doesn't meet the driver's requirements.

We could eliminate the abstraction by moving the EPC management code
into the driver, but that would directly conflict with past feedback
and would need to be completely undone to enable KVM.  The abstraction
could be dumbed down to a single function, but as mentioned earlier,
that comes with its own costs.  I can dive into exactly what we lose
with a single function approach if this is a sticking point.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* RE: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-28  7:01     ` Jarkko Sakkinen
@ 2018-08-29  7:33       ` Huang, Kai
  2018-08-29 20:33         ` Sean Christopherson
  2018-08-31 12:17         ` Jarkko Sakkinen
  0 siblings, 2 replies; 103+ messages in thread
From: Huang, Kai @ 2018-08-29  7:33 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: platform-driver-x86, x86, nhorman, linux-kernel, Christopherson,
	Sean J, tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum,
	mingo, linux-sgx, Hansen, Dave

[snip..]

> > >
> > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);  static
> > > DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > >  static struct task_struct *ksgxswapd_tsk;  static
> > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > +static struct notifier_block sgx_pm_notifier; static u64
> > > +sgx_pm_cnt;
> > > +
> > > +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx
> > > +MSRs
> > > for each
> > > + * CPU. The entries are initialized when they are first used by
> > > sgx_einit().
> > > + */
> > > +struct sgx_lepubkeyhash {
> > > +	u64 msrs[4];
> > > +	u64 pm_cnt;
> >
> > May I ask why do we need pm_cnt here? In fact why do we need suspend
> > staff (namely, sgx_pm_cnt above, and related code in this patch) here
> > in this patch? From the patch commit message I don't see why we need
> > PM staff here. Please give comment why you need PM staff, or you may
> > consider to split the PM staff to another patch.
> 
> Refining the commit message probably makes more sense because without PM
> code sgx_einit() would be broken. The MSRs have been reset after waking up.
> 
> Some kind of counter is required to keep track of the power cycle. When going
> to sleep the sgx_pm_cnt is increased. sgx_einit() compares the current value of
> the global count to the value in the cache entry to see whether we are in a new
> power cycle.

You mean reset to Intel default? I think we can also just reset the cached MSR values on each power cycle, which would be simpler, IMHO?

I think we definitely need some code to handle S3-S5, but should be in separate patches, since I think the major impact of S3-S5 is entire EPC being destroyed. I think keeping pm_cnt is not sufficient enough to handle such case?

> 
> This brings up one question though: how do we deal with VM host going to sleep?
> VM guest would not be aware of this.

IMO VM just gets "sudden loss of EPC" after suspend & resume in host. SGX driver and SDK should be able to handle "sudden loss of EPC", ie, co-working together to re-establish the missing enclaves.

Actually supporting "sudden loss of EPC" is a requirement to support live migration of VM w/ SGX. Internally long time ago we had a discussion and the decision was we should support SGX live migration given two facts:

1) losing platform-dependent is not important. For example, losing sealing key is not a problem, as we could get secrets provisioned again from remote. 2) Both windows & linux driver commit to support "sudden loss of EPC".

I don't think we have to support in very first upstream driver, but I think we need to support someday.

Sean, 

Would you be able to comment here?

> 
> I think the best measure would be to add a new parameter to sgx_einit() that
> enforces update of the MSRs. The driver can then set this parameter in the case
> when sgx_einit() returns SGX_INVALID_LICENSE. This is coherent because the
> driver requires writable MSRs. It would not be coherent to do it directly in the
> core because KVM does not require writable MSRs.

IMHO this is not required, as I mentioned above.

And 
[snip...]

Thanks,
-Kai

^ permalink raw reply	[flat|nested] 103+ messages in thread

* RE: [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features
  2018-08-28  7:17     ` Jarkko Sakkinen
@ 2018-08-29  7:36       ` Huang, Kai
  2018-08-31 12:19         ` Jarkko Sakkinen
  0 siblings, 1 reply; 103+ messages in thread
From: Huang, Kai @ 2018-08-29  7:36 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: x86, platform-driver-x86, Hansen, Dave, Christopherson, Sean J,
	nhorman, npmccallum, linux-sgx, Kai Huang, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Borislav Petkov,
	Konrad Rzeszutek Wilk, David Woodhouse,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

> -----Original Message-----
> From: Jarkko Sakkinen [mailto:jarkko.sakkinen@linux.intel.com]
> Sent: Tuesday, August 28, 2018 7:17 PM
> To: Huang, Kai <kai.huang@intel.com>
> Cc: x86@kernel.org; platform-driver-x86@vger.kernel.org; Hansen, Dave
> <dave.hansen@intel.com>; Christopherson, Sean J
> <sean.j.christopherson@intel.com>; nhorman@redhat.com;
> npmccallum@redhat.com; linux-sgx@vger.kernel.org; Kai Huang
> <kai.huang@linux.intel.com>; Thomas Gleixner <tglx@linutronix.de>; Ingo
> Molnar <mingo@redhat.com>; H. Peter Anvin <hpa@zytor.com>; Borislav
> Petkov <bp@suse.de>; Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>;
> David Woodhouse <dwmw@amazon.co.uk>; open list:X86 ARCHITECTURE (32-
> BIT AND 64-BIT) <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU
> features
> 
> On Tue, Aug 28, 2018 at 12:07:41AM +0000, Huang, Kai wrote:
> > > +#define X86_FEATURE_SGX_LC		(16*32+30) /* supports SGX
> launch
> > > configuration */
> >
> > Sorry if it was me who wrote the comment "SGX launch configuration". I
> > think we should just use "SGX launch control". :)
> 
> Not sure if we should change though. The former is more self-explaining, the
> latter is "more official".

I'll let you decide.  To me the comment should explain what does "LC" mean, and to me it means "launch control". :)

Thanks,
-Kai
> 
> /Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-29  7:33       ` Huang, Kai
@ 2018-08-29 20:33         ` Sean Christopherson
  2018-08-29 20:58           ` Huang, Kai
  2018-08-31 12:17         ` Jarkko Sakkinen
  1 sibling, 1 reply; 103+ messages in thread
From: Sean Christopherson @ 2018-08-29 20:33 UTC (permalink / raw)
  To: Huang, Kai
  Cc: Jarkko Sakkinen, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

On Wed, Aug 29, 2018 at 12:33:54AM -0700, Huang, Kai wrote:
> [snip..]
> 
> > > >
> > > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);  static
> > > > DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > > >  static struct task_struct *ksgxswapd_tsk;  static
> > > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > > +static struct notifier_block sgx_pm_notifier; static u64
> > > > +sgx_pm_cnt;
> > > > +
> > > > +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx
> > > > +MSRs
> > > > for each
> > > > + * CPU. The entries are initialized when they are first used by
> > > > sgx_einit().
> > > > + */
> > > > +struct sgx_lepubkeyhash {
> > > > +	u64 msrs[4];
> > > > +	u64 pm_cnt;
> > >
> > > May I ask why do we need pm_cnt here? In fact why do we need suspend
> > > staff (namely, sgx_pm_cnt above, and related code in this patch) here
> > > in this patch? From the patch commit message I don't see why we need
> > > PM staff here. Please give comment why you need PM staff, or you may
> > > consider to split the PM staff to another patch.
> > 
> > Refining the commit message probably makes more sense because without PM
> > code sgx_einit() would be broken. The MSRs have been reset after waking up.
> > 
> > Some kind of counter is required to keep track of the power cycle. When going
> > to sleep the sgx_pm_cnt is increased. sgx_einit() compares the current value of
> > the global count to the value in the cache entry to see whether we are in a new
> > power cycle.
> 
> You mean reset to Intel default? I think we can also just reset the cached MSR
> values on each power cycle, which would be simpler, IMHO?

Refresh my brain, does hardware reset the MSRs on a transition to S3 or lower?

> I think we definitely need some code to handle S3-S5, but should be in
> separate patches, since I think the major impact of S3-S5 is entire EPC
> being destroyed. I think keeping pm_cnt is not sufficient enough to handle
> such case?
> > 
> > This brings up one question though: how do we deal with VM host going to sleep?
> > VM guest would not be aware of this.
> 
> IMO VM just gets "sudden loss of EPC" after suspend & resume in host. SGX driver
> and SDK should be able to handle "sudden loss of EPC", ie, co-working together to
> re-establish the missing enclaves.
> 
> Actually supporting "sudden loss of EPC" is a requirement to support live migration
> of VM w/ SGX. Internally long time ago we had a discussion and the decision was we
> should support SGX live migration given two facts:
> 
> 1) losing platform-dependent is not important. For example, losing sealing key is
> not a problem, as we could get secrets provisioned again from remote. 2) Both windows
> & linux driver commit to support "sudden loss of EPC".
> 
> I don't think we have to support in very first upstream driver, but I think we need
> to support someday.

Actually, we can easily support this in the driver, at least for SGX1
hardware.  SGX2 isn't difficult to handle, but we've intentionally
postponed those patches until SGX1 support is in mainline[1].
Accesses to the EPC after it is lost will cause faults.  Userspace
EPC accesses, e.g. ERESUME, will get a SIGSEGV that the process
should interpret as an "I should restart my enclave" event.  The
SDK already does this.  In the driver, we just need to be aware of
this potential behavior and not freak out.  Specifically, SGX_INVD
needs to not WARN on faults that may have been due to a the EPC
being nuked.  I think we can even remove the sgx_encl_pm_notifier()
code altogether.

[1] SGX1 hardware signals a #GP on an access to an invalid EPC page.
    SGX2 signals a #PF with the PF_SGX error code bit set.  This is
    problematic because the kernel looks at the PTEs for CR2 and sees
    nothing wrong, so it thinks it should just restart the
    instruction, leading to an infinite fault loop.  Resolving this
    is fairly straightforward, but a complete fix requires propagating
    PF_SGX down to the ENCLS fixup handler, which means plumbing the
    error code through the fixup handlers or smushing PF_SGX into
    trapnr.  Since there is a parallel effort to plumb the error code
    through the handlers, https://lkml.org/lkml/2018/8/6/924, we opted
    to do this in a separate series.

> Sean, 
> 
> Would you be able to comment here?
> 
> > 
> > I think the best measure would be to add a new parameter to sgx_einit() that
> > enforces update of the MSRs. The driver can then set this parameter in the case
> > when sgx_einit() returns SGX_INVALID_LICENSE. This is coherent because the
> > driver requires writable MSRs. It would not be coherent to do it directly in the
> > core because KVM does not require writable MSRs.
> 
> IMHO this is not required, as I mentioned above.
> 
> And 
> [snip...]
> 
> Thanks,
> -Kai

^ permalink raw reply	[flat|nested] 103+ messages in thread

* RE: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-29 20:33         ` Sean Christopherson
@ 2018-08-29 20:58           ` Huang, Kai
  2018-08-29 21:09             ` Sean Christopherson
  0 siblings, 1 reply; 103+ messages in thread
From: Huang, Kai @ 2018-08-29 20:58 UTC (permalink / raw)
  To: Christopherson, Sean J
  Cc: Jarkko Sakkinen, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

> -----Original Message-----
> From: Christopherson, Sean J
> Sent: Thursday, August 30, 2018 8:34 AM
> To: Huang, Kai <kai.huang@intel.com>
> Cc: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>; platform-driver-
> x86@vger.kernel.org; x86@kernel.org; nhorman@redhat.com; linux-
> kernel@vger.kernel.org; tglx@linutronix.de; suresh.b.siddha@intel.com; Ayoun,
> Serge <serge.ayoun@intel.com>; hpa@zytor.com; npmccallum@redhat.com;
> mingo@redhat.com; linux-sgx@vger.kernel.org; Hansen, Dave
> <dave.hansen@intel.com>
> Subject: Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
> 
> On Wed, Aug 29, 2018 at 12:33:54AM -0700, Huang, Kai wrote:
> > [snip..]
> >
> > > > >
> > > > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);
> > > > > static DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > > > >  static struct task_struct *ksgxswapd_tsk;  static
> > > > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > > > +static struct notifier_block sgx_pm_notifier; static u64
> > > > > +sgx_pm_cnt;
> > > > > +
> > > > > +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx
> > > > > +MSRs
> > > > > for each
> > > > > + * CPU. The entries are initialized when they are first used by
> > > > > sgx_einit().
> > > > > + */
> > > > > +struct sgx_lepubkeyhash {
> > > > > +	u64 msrs[4];
> > > > > +	u64 pm_cnt;
> > > >
> > > > May I ask why do we need pm_cnt here? In fact why do we need
> > > > suspend staff (namely, sgx_pm_cnt above, and related code in this
> > > > patch) here in this patch? From the patch commit message I don't
> > > > see why we need PM staff here. Please give comment why you need PM
> > > > staff, or you may consider to split the PM staff to another patch.
> > >
> > > Refining the commit message probably makes more sense because
> > > without PM code sgx_einit() would be broken. The MSRs have been reset
> after waking up.
> > >
> > > Some kind of counter is required to keep track of the power cycle.
> > > When going to sleep the sgx_pm_cnt is increased. sgx_einit()
> > > compares the current value of the global count to the value in the
> > > cache entry to see whether we are in a new power cycle.
> >
> > You mean reset to Intel default? I think we can also just reset the
> > cached MSR values on each power cycle, which would be simpler, IMHO?
> 
> Refresh my brain, does hardware reset the MSRs on a transition to S3 or lower?
> 
> > I think we definitely need some code to handle S3-S5, but should be in
> > separate patches, since I think the major impact of S3-S5 is entire
> > EPC being destroyed. I think keeping pm_cnt is not sufficient enough
> > to handle such case?
> > >
> > > This brings up one question though: how do we deal with VM host going to
> sleep?
> > > VM guest would not be aware of this.
> >
> > IMO VM just gets "sudden loss of EPC" after suspend & resume in host.
> > SGX driver and SDK should be able to handle "sudden loss of EPC", ie,
> > co-working together to re-establish the missing enclaves.
> >
> > Actually supporting "sudden loss of EPC" is a requirement to support
> > live migration of VM w/ SGX. Internally long time ago we had a
> > discussion and the decision was we should support SGX live migration given
> two facts:
> >
> > 1) losing platform-dependent is not important. For example, losing
> > sealing key is not a problem, as we could get secrets provisioned
> > again from remote. 2) Both windows & linux driver commit to support "sudden
> loss of EPC".
> >
> > I don't think we have to support in very first upstream driver, but I
> > think we need to support someday.
> 
> Actually, we can easily support this in the driver, at least for SGX1 hardware.

That's my guess too. Just want to check whether we are still on the same page :)

> SGX2 isn't difficult to handle, but we've intentionally postponed those patches
> until SGX1 support is in mainline[1].
> Accesses to the EPC after it is lost will cause faults.  Userspace EPC accesses, e.g.
> ERESUME, will get a SIGSEGV that the process should interpret as an "I should
> restart my enclave" event.  The SDK already does this.  In the driver, we just need
> to be aware of this potential behavior and not freak out.  Specifically, SGX_INVD
> needs to not WARN on faults that may have been due to a the EPC being nuked.
> I think we can even remove the sgx_encl_pm_notifier() code altogether.

Possibly we still need to do some cleanup, ie, all structures of enclaves, upon resume? 

Anyway I am just guessing.

Thanks,
-Kai

> 
> [1] SGX1 hardware signals a #GP on an access to an invalid EPC page.
>     SGX2 signals a #PF with the PF_SGX error code bit set.  This is
>     problematic because the kernel looks at the PTEs for CR2 and sees
>     nothing wrong, so it thinks it should just restart the
>     instruction, leading to an infinite fault loop.  Resolving this
>     is fairly straightforward, but a complete fix requires propagating
>     PF_SGX down to the ENCLS fixup handler, which means plumbing the
>     error code through the fixup handlers or smushing PF_SGX into
>     trapnr.  Since there is a parallel effort to plumb the error code
>     through the handlers, https://lkml.org/lkml/2018/8/6/924, we opted
>     to do this in a separate series.
> 
> > Sean,
> >
> > Would you be able to comment here?
> >
> > >
> > > I think the best measure would be to add a new parameter to
> > > sgx_einit() that enforces update of the MSRs. The driver can then
> > > set this parameter in the case when sgx_einit() returns
> > > SGX_INVALID_LICENSE. This is coherent because the driver requires
> > > writable MSRs. It would not be coherent to do it directly in the core because
> KVM does not require writable MSRs.
> >
> > IMHO this is not required, as I mentioned above.
> >
> > And
> > [snip...]
> >
> > Thanks,
> > -Kai

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-29 20:58           ` Huang, Kai
@ 2018-08-29 21:09             ` Sean Christopherson
  2018-08-30  1:45               ` Huang, Kai
  0 siblings, 1 reply; 103+ messages in thread
From: Sean Christopherson @ 2018-08-29 21:09 UTC (permalink / raw)
  To: Huang, Kai
  Cc: Jarkko Sakkinen, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

On Wed, Aug 29, 2018 at 01:58:09PM -0700, Huang, Kai wrote:
> > -----Original Message-----
> > From: Christopherson, Sean J
> > Sent: Thursday, August 30, 2018 8:34 AM
> > To: Huang, Kai <kai.huang@intel.com>
> > Cc: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>; platform-driver-
> > x86@vger.kernel.org; x86@kernel.org; nhorman@redhat.com; linux-
> > kernel@vger.kernel.org; tglx@linutronix.de; suresh.b.siddha@intel.com; Ayoun,
> > Serge <serge.ayoun@intel.com>; hpa@zytor.com; npmccallum@redhat.com;
> > mingo@redhat.com; linux-sgx@vger.kernel.org; Hansen, Dave
> > <dave.hansen@intel.com>
> > Subject: Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
> > 
> > On Wed, Aug 29, 2018 at 12:33:54AM -0700, Huang, Kai wrote:
> > > [snip..]
> > >
> > > > > >
> > > > > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);
> > > > > > static DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > > > > >  static struct task_struct *ksgxswapd_tsk;  static
> > > > > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > > > > +static struct notifier_block sgx_pm_notifier; static u64
> > > > > > +sgx_pm_cnt;
> > > > > > +
> > > > > > +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx
> > > > > > +MSRs
> > > > > > for each
> > > > > > + * CPU. The entries are initialized when they are first used by
> > > > > > sgx_einit().
> > > > > > + */
> > > > > > +struct sgx_lepubkeyhash {
> > > > > > +	u64 msrs[4];
> > > > > > +	u64 pm_cnt;
> > > > >
> > > > > May I ask why do we need pm_cnt here? In fact why do we need
> > > > > suspend staff (namely, sgx_pm_cnt above, and related code in this
> > > > > patch) here in this patch? From the patch commit message I don't
> > > > > see why we need PM staff here. Please give comment why you need PM
> > > > > staff, or you may consider to split the PM staff to another patch.
> > > >
> > > > Refining the commit message probably makes more sense because
> > > > without PM code sgx_einit() would be broken. The MSRs have been reset
> > after waking up.
> > > >
> > > > Some kind of counter is required to keep track of the power cycle.
> > > > When going to sleep the sgx_pm_cnt is increased. sgx_einit()
> > > > compares the current value of the global count to the value in the
> > > > cache entry to see whether we are in a new power cycle.
> > >
> > > You mean reset to Intel default? I think we can also just reset the
> > > cached MSR values on each power cycle, which would be simpler, IMHO?
> > 
> > Refresh my brain, does hardware reset the MSRs on a transition to S3 or lower?
> > 
> > > I think we definitely need some code to handle S3-S5, but should be in
> > > separate patches, since I think the major impact of S3-S5 is entire
> > > EPC being destroyed. I think keeping pm_cnt is not sufficient enough
> > > to handle such case?
> > > >
> > > > This brings up one question though: how do we deal with VM host going to
> > sleep?
> > > > VM guest would not be aware of this.
> > >
> > > IMO VM just gets "sudden loss of EPC" after suspend & resume in host.
> > > SGX driver and SDK should be able to handle "sudden loss of EPC", ie,
> > > co-working together to re-establish the missing enclaves.
> > >
> > > Actually supporting "sudden loss of EPC" is a requirement to support
> > > live migration of VM w/ SGX. Internally long time ago we had a
> > > discussion and the decision was we should support SGX live migration given
> > two facts:
> > >
> > > 1) losing platform-dependent is not important. For example, losing
> > > sealing key is not a problem, as we could get secrets provisioned
> > > again from remote. 2) Both windows & linux driver commit to support "sudden
> > loss of EPC".
> > >
> > > I don't think we have to support in very first upstream driver, but I
> > > think we need to support someday.
> > 
> > Actually, we can easily support this in the driver, at least for SGX1 hardware.
> 
> That's my guess too. Just want to check whether we are still on the same page :)
> 
> > SGX2 isn't difficult to handle, but we've intentionally postponed those patches
> > until SGX1 support is in mainline[1].
> > Accesses to the EPC after it is lost will cause faults.  Userspace EPC accesses, e.g.
> > ERESUME, will get a SIGSEGV that the process should interpret as an "I should
> > restart my enclave" event.  The SDK already does this.  In the driver, we just need
> > to be aware of this potential behavior and not freak out.  Specifically, SGX_INVD
> > needs to not WARN on faults that may have been due to a the EPC being nuked.
> > I think we can even remove the sgx_encl_pm_notifier() code altogether.
> 
> Possibly we still need to do some cleanup, ie, all structures of enclaves, upon resume? 

Not for functional reasons.  The driver will automatically do the
cleanup via SGX_INVD when it next accesses the enclave's pages and
takes a fault, e.g. during reclaim.  Proactively reclaiming the EPC
pages would probably affect performance, though not necessarily in
a good way.  And I think it would be a beneficial to get the driver
out of the suspend/hibernate/resume paths, e.g. zapping all enclaves
could noticeably impact suspend/resume latency.
 
> Anyway I am just guessing.
> 
> Thanks,
> -Kai
> 
> > 
> > [1] SGX1 hardware signals a #GP on an access to an invalid EPC page.
> >     SGX2 signals a #PF with the PF_SGX error code bit set.  This is
> >     problematic because the kernel looks at the PTEs for CR2 and sees
> >     nothing wrong, so it thinks it should just restart the
> >     instruction, leading to an infinite fault loop.  Resolving this
> >     is fairly straightforward, but a complete fix requires propagating
> >     PF_SGX down to the ENCLS fixup handler, which means plumbing the
> >     error code through the fixup handlers or smushing PF_SGX into
> >     trapnr.  Since there is a parallel effort to plumb the error code
> >     through the handlers, https://lkml.org/lkml/2018/8/6/924, we opted
> >     to do this in a separate series.
> > 
> > > Sean,
> > >
> > > Would you be able to comment here?
> > >
> > > >
> > > > I think the best measure would be to add a new parameter to
> > > > sgx_einit() that enforces update of the MSRs. The driver can then
> > > > set this parameter in the case when sgx_einit() returns
> > > > SGX_INVALID_LICENSE. This is coherent because the driver requires
> > > > writable MSRs. It would not be coherent to do it directly in the core because
> > KVM does not require writable MSRs.
> > >
> > > IMHO this is not required, as I mentioned above.
> > >
> > > And
> > > [snip...]
> > >
> > > Thanks,
> > > -Kai

^ permalink raw reply	[flat|nested] 103+ messages in thread

* RE: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-29 21:09             ` Sean Christopherson
@ 2018-08-30  1:45               ` Huang, Kai
  2018-08-31 17:43                 ` Sean Christopherson
  2018-09-03 18:15                 ` Jarkko Sakkinen
  0 siblings, 2 replies; 103+ messages in thread
From: Huang, Kai @ 2018-08-30  1:45 UTC (permalink / raw)
  To: Christopherson, Sean J
  Cc: Jarkko Sakkinen, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

> > > > > Some kind of counter is required to keep track of the power cycle.
> > > > > When going to sleep the sgx_pm_cnt is increased. sgx_einit()
> > > > > compares the current value of the global count to the value in
> > > > > the cache entry to see whether we are in a new power cycle.
> > > >
> > > > You mean reset to Intel default? I think we can also just reset
> > > > the cached MSR values on each power cycle, which would be simpler,
> IMHO?
> > >
> > > Refresh my brain, does hardware reset the MSRs on a transition to S3 or
> lower?

Sorry I missed this one. To be honest I don't know. I checked the SDM and all I can find is:

"On reset, the default value is the digest of Intel's signing key."

Jarkko may know.

> > >
> > > > I think we definitely need some code to handle S3-S5, but should
> > > > be in separate patches, since I think the major impact of S3-S5 is
> > > > entire EPC being destroyed. I think keeping pm_cnt is not
> > > > sufficient enough to handle such case?
> > > > >
> > > > > This brings up one question though: how do we deal with VM host
> > > > > going to
> > > sleep?
> > > > > VM guest would not be aware of this.
> > > >
> > > > IMO VM just gets "sudden loss of EPC" after suspend & resume in host.
> > > > SGX driver and SDK should be able to handle "sudden loss of EPC",
> > > > ie, co-working together to re-establish the missing enclaves.
> > > >
> > > > Actually supporting "sudden loss of EPC" is a requirement to
> > > > support live migration of VM w/ SGX. Internally long time ago we
> > > > had a discussion and the decision was we should support SGX live
> > > > migration given
> > > two facts:
> > > >
> > > > 1) losing platform-dependent is not important. For example, losing
> > > > sealing key is not a problem, as we could get secrets provisioned
> > > > again from remote. 2) Both windows & linux driver commit to
> > > > support "sudden
> > > loss of EPC".
> > > >
> > > > I don't think we have to support in very first upstream driver,
> > > > but I think we need to support someday.
> > >
> > > Actually, we can easily support this in the driver, at least for SGX1 hardware.
> >
> > That's my guess too. Just want to check whether we are still on the
> > same page :)
> >
> > > SGX2 isn't difficult to handle, but we've intentionally postponed
> > > those patches until SGX1 support is in mainline[1].
> > > Accesses to the EPC after it is lost will cause faults.  Userspace EPC accesses,
> e.g.
> > > ERESUME, will get a SIGSEGV that the process should interpret as an
> > > "I should restart my enclave" event.  The SDK already does this.  In
> > > the driver, we just need to be aware of this potential behavior and
> > > not freak out.  Specifically, SGX_INVD needs to not WARN on faults that may
> have been due to a the EPC being nuked.
> > > I think we can even remove the sgx_encl_pm_notifier() code altogether.
> >
> > Possibly we still need to do some cleanup, ie, all structures of enclaves, upon
> resume?
> 
> Not for functional reasons.  The driver will automatically do the cleanup via
> SGX_INVD when it next accesses the enclave's pages and takes a fault, e.g.
> during reclaim.  Proactively reclaiming the EPC pages would probably affect
> performance, though not necessarily in a good way.  And I think it would be a
> beneficial to get the driver out of the suspend/hibernate/resume paths, e.g.
> zapping all enclaves could noticeably impact suspend/resume latency.

Sure.

Thanks,
-Kai


^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-08-28 16:53       ` Dave Hansen
  2018-08-28 21:34         ` Sean Christopherson
@ 2018-08-31 11:10         ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-31 11:10 UTC (permalink / raw)
  To: Dave Hansen
  Cc: x86, platform-driver-x86, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Serge Ayoun, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Tue, Aug 28, 2018 at 09:53:11AM -0700, Dave Hansen wrote:
> >>>  extern bool sgx_enabled;
> >>>  extern bool sgx_lc_enabled;
> >>> +extern struct sgx_epc_bank sgx_epc_banks[SGX_MAX_EPC_BANKS];
> >>> +
> >>> +/*
> >>> + * enum sgx_epc_page_desc - defines bits and masks for an EPC page's desc
> >>
> >> Why are you bothering packing these bits?  This seems a rather
> >> convoluted way to store two integers.
> > 
> > To keep struct sgx_epc_page 64 bytes.
> 
> It's a list_head and a ulong now.  That doesn't add up to 64.

Ah, there used to be one more variable in it.

> If you properly describe the bounds and limits of banks we can possibly
> help you find a nice solution.  As it stands, they are totally opaque
> and we have no idea what is going on.

Great, I see what I can do. I understand now better what you are looking
for. Thanks Dave.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-08-28 21:34         ` Sean Christopherson
@ 2018-08-31 11:13           ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-31 11:13 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Dave Hansen, x86, platform-driver-x86, nhorman, npmccallum,
	linux-sgx, Serge Ayoun, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Suresh Siddha,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Tue, Aug 28, 2018 at 02:34:32PM -0700, Sean Christopherson wrote:
> On Tue, Aug 28, 2018 at 09:53:11AM -0700, Dave Hansen wrote:
> > >>> +		sgx_nr_epc_banks++;
> > >>> +	}
> > >>> +
> > >>> +	if (!sgx_nr_epc_banks) {
> > >>> +		pr_err("There are zero EPC banks.\n");
> > >>> +		return -ENODEV;
> > >>> +	}
> > >>> +
> > >>> +	return 0;
> > >>> +}
> > >>
> > >> Does this support hot-addition of a bank?  If not, why not?
> > ...
> > > I'm not aware that we would have an ACPI specification for SGX so this
> > > is all I have at the moment (does not show any ACPI event for
> > > hotplugging).
> > 
> > So you're saying the one platform you looked at don't support hotplug.
> > I was looking for a more broad statement about SGX.
> 
> Hardware doesn't support hotplug of EPC as the EPC size and location
> is locked during activation of SGX.  And IIRC, activation of SGX must
> be synchronized across all CPUs in a multi-socket platform, e.g. you
> can't late-enable SGX on a socket and due hotplugging that way.

Makes me wonder how on a multisocket platform would this work anyway
given that they have different fused keys?

> In a virtualized environment there are no such restrictions.  I am not
> aware of any explicit requirements or use cases for supporting hotplug
> of EPC, but that's probably only because virtualization of SGX is
> fairly nascent.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-28 21:22         ` Sean Christopherson
  2018-08-28 21:26           ` Dave Hansen
@ 2018-08-31 11:22           ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-31 11:22 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Dave Hansen, x86, platform-driver-x86, nhorman, npmccallum,
	linux-sgx, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Tue, Aug 28, 2018 at 02:22:44PM -0700, Sean Christopherson wrote:
> On Tue, Aug 28, 2018 at 07:07:33AM -0700, Dave Hansen wrote:
> > On 08/28/2018 01:35 AM, Jarkko Sakkinen wrote:
> > > On Mon, Aug 27, 2018 at 02:15:34PM -0700, Dave Hansen wrote:
> > >> On 08/27/2018 11:53 AM, Jarkko Sakkinen wrote:
> > >>> +struct sgx_epc_page_ops {
> > >>> +	bool (*get)(struct sgx_epc_page *epc_page);
> > >>> +	void (*put)(struct sgx_epc_page *epc_page);
> > >>> +	bool (*reclaim)(struct sgx_epc_page *epc_page);
> > >>> +	void (*block)(struct sgx_epc_page *epc_page);
> > >>> +	void (*write)(struct sgx_epc_page *epc_page);
> > >>> +};
> > >> Why do we need a fancy, slow (retpoline'd) set of function pointers when
> > >> we only have one user of these (the SGX driver)?
> > > KVM has its own implementation for these operations.
> > 
> > That belongs in the changelog.
> > 
> > Also, where is the implementation?  How can we assess this code that was
> > built to create an abstraction without both of the users?
> 
> I can provide an early preview of the KVM reclaim code, but honestly
> I think that would do more harm than good.  The VMX architecture for
> EPC reclaim is complex, even for SGX standards.  Opening that can of
> worms would likely derail this discussion.  That being said, this
> abstraction isn't exactly what KVM will need, but it's pretty close
> and gives us something to build on.
> 
> Regardless, this layer of indirection is justifiable even with a
> single implementation.  Reclaiming an EPC page is not a simple matter
> of copying the data somewhere else and marking the page not present.
> Actual eviction requires a reference to the Secure Enclave Control
> Structure (SECS) of the enclave that owns the page.  Software needs
> to ensure it doesn't violate the hardware-enforced access rules, e.g.
> most reclaim activites need to be done under a per-enclave lock.
> Not all pages have the same reclaim rules, e.g. an SECS can only
> be reclaimed after all its child pages have reclaimed, a VA page
> doesn't need to be blocked, etc...  And the list goes on...

To simplify a bit what Sean said about the key difference to a standard
page is that in SGX a page is part of a hierarchical structure. EPC
pages have hardware enforced dependencies to each other.

Examples: 

1. You cannot delete or swap SECS before its children have been deleted or
   swapped. You get SGX_CHILD_PRESENT erro from EREMOVE.
2. In order to swap or fault a page you need to have an EPC page that
   holds a version number for the page you want to swap. These are
   called Version Array (VA) pages.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-29  7:33       ` Huang, Kai
  2018-08-29 20:33         ` Sean Christopherson
@ 2018-08-31 12:17         ` Jarkko Sakkinen
  2018-08-31 18:15           ` Sean Christopherson
  1 sibling, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-31 12:17 UTC (permalink / raw)
  To: Huang, Kai
  Cc: platform-driver-x86, x86, nhorman, linux-kernel, Christopherson,
	Sean J, tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum,
	mingo, linux-sgx, Hansen, Dave

On Wed, Aug 29, 2018 at 07:33:54AM +0000, Huang, Kai wrote:
> [snip..]
> 
> > > >
> > > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);  static
> > > > DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > > >  static struct task_struct *ksgxswapd_tsk;  static
> > > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > > +static struct notifier_block sgx_pm_notifier; static u64
> > > > +sgx_pm_cnt;
> > > > +
> > > > +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx
> > > > +MSRs
> > > > for each
> > > > + * CPU. The entries are initialized when they are first used by
> > > > sgx_einit().
> > > > + */
> > > > +struct sgx_lepubkeyhash {
> > > > +	u64 msrs[4];
> > > > +	u64 pm_cnt;
> > >
> > > May I ask why do we need pm_cnt here? In fact why do we need suspend
> > > staff (namely, sgx_pm_cnt above, and related code in this patch) here
> > > in this patch? From the patch commit message I don't see why we need
> > > PM staff here. Please give comment why you need PM staff, or you may
> > > consider to split the PM staff to another patch.
> > 
> > Refining the commit message probably makes more sense because without PM
> > code sgx_einit() would be broken. The MSRs have been reset after waking up.
> > 
> > Some kind of counter is required to keep track of the power cycle. When going
> > to sleep the sgx_pm_cnt is increased. sgx_einit() compares the current value of
> > the global count to the value in the cache entry to see whether we are in a new
> > power cycle.
> 
> You mean reset to Intel default? I think we can also just reset the
> cached MSR values on each power cycle, which would be simpler, IMHO?

I don't really see that much difference in the complexity.

> I think we definitely need some code to handle S3-S5, but should be in
> separate patches, since I think the major impact of S3-S5 is entire
> EPC being destroyed. I think keeping pm_cnt is not sufficient enough
> to handle such case?

The driver has SGX_POWER_LOST_ENCLAVE for ioctls and it deletes the TCS
entries.

> > This brings up one question though: how do we deal with VM host going to sleep?
> > VM guest would not be aware of this.
> 
> IMO VM just gets "sudden loss of EPC" after suspend & resume in host.
> SGX driver and SDK should be able to handle "sudden loss of EPC", ie,
> co-working together to re-establish the missing enclaves.

This is not about EPC. It is already dealt by the driver. I'm concerned
about the MSR cache as it would mess up.

But I guess this logic is part of the KVM code anyway now that I think
more of it.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features
  2018-08-29  7:36       ` Huang, Kai
@ 2018-08-31 12:19         ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-08-31 12:19 UTC (permalink / raw)
  To: Huang, Kai
  Cc: x86, platform-driver-x86, Hansen, Dave, Christopherson, Sean J,
	nhorman, npmccallum, linux-sgx, Kai Huang, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Borislav Petkov,
	Konrad Rzeszutek Wilk, David Woodhouse,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Wed, Aug 29, 2018 at 07:36:13AM +0000, Huang, Kai wrote:
> > -----Original Message-----
> > From: Jarkko Sakkinen [mailto:jarkko.sakkinen@linux.intel.com]
> > Sent: Tuesday, August 28, 2018 7:17 PM
> > To: Huang, Kai <kai.huang@intel.com>
> > Cc: x86@kernel.org; platform-driver-x86@vger.kernel.org; Hansen, Dave
> > <dave.hansen@intel.com>; Christopherson, Sean J
> > <sean.j.christopherson@intel.com>; nhorman@redhat.com;
> > npmccallum@redhat.com; linux-sgx@vger.kernel.org; Kai Huang
> > <kai.huang@linux.intel.com>; Thomas Gleixner <tglx@linutronix.de>; Ingo
> > Molnar <mingo@redhat.com>; H. Peter Anvin <hpa@zytor.com>; Borislav
> > Petkov <bp@suse.de>; Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>;
> > David Woodhouse <dwmw@amazon.co.uk>; open list:X86 ARCHITECTURE (32-
> > BIT AND 64-BIT) <linux-kernel@vger.kernel.org>
> > Subject: Re: [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU
> > features
> > 
> > On Tue, Aug 28, 2018 at 12:07:41AM +0000, Huang, Kai wrote:
> > > > +#define X86_FEATURE_SGX_LC		(16*32+30) /* supports SGX
> > launch
> > > > configuration */
> > >
> > > Sorry if it was me who wrote the comment "SGX launch configuration". I
> > > think we should just use "SGX launch control". :)
> > 
> > Not sure if we should change though. The former is more self-explaining, the
> > latter is "more official".
> 
> I'll let you decide.  To me the comment should explain what does "LC"
> mean, and to me it means "launch control". :)

Yea, maybe it is better to change as SDM speaks about launch control...

> Thanks,
> -Kai
> > 
> > /Jarkko

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features
  2018-08-27 18:53 ` [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features Jarkko Sakkinen
  2018-08-28  0:07   ` Huang, Kai
@ 2018-08-31 16:18   ` Dr. Greg
  1 sibling, 0 replies; 103+ messages in thread
From: Dr. Greg @ 2018-08-31 16:18 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: x86, platform-driver-x86, dave.hansen, sean.j.christopherson,
	nhorman, npmccallum, linux-sgx, Kai Huang, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Borislav Petkov,
	Konrad Rzeszutek Wilk, David Woodhouse,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Mon, Aug 27, 2018 at 09:53:23PM +0300, Jarkko Sakkinen wrote:

Good morning, I hope the week has gone well for everyone.

> From: Kai Huang <kai.huang@linux.intel.com>
> 
> Add X86_FEATURE_SGX and X86_FEATURE_SGX_LC that define the bits
> determining whether the CPU supports SGX and user launch configuration
> i.e. using a custom root key rather the Intel proprietary key for
> enclave signing.

First of all thanks to Jarkko, Sean et.al who have been working on
Linux SGX eco-system support.  Given the nature and apparent mystique
surrounding this technology, we are assuming that Intel has you locked
away in dungeons somewhere... :-)

I direct engineering efforts for an SGX development company.  We are a
licensed Intel ISV, ie. we have a signing key on the launch enclave
whitelist.  Due to the nature of our products we designed an
independent implementation of the PSW which includes enclave loading
and execution, EPID provisioning and remote attestation
infrastructure.  We have also done initial engineering on the
feasibility of developing an independent authentication and
attestation service.

So I think we understand this technology about as well as anyone.

Our reflections on the patch series are not technical as much as
operational.  To wit; are you guys developing this driver 'blind',
ie. simply based on guidance from the SDM or are you testing them on
simulators or do you actually have real live hardware with these
capabilities?

If you boil these 'new' patches down they basically address three
primary areas of functionality; Enclave Dynamic Memory Management
(EDMM), Flexible Launch Control (Unlocked identity modulus signature
registers) and NUMA support.  You could also throw in virtualization
as that is another whole can of worms given a VM may not end up on the
same die, ie. TCB base.

Other then a smattering of machines which advertise basic SGX2
instruction support for EDMM, there is virtually no hardware available
to test any of this functionality on.  Also of interest, there is
virtually no guidance available as to when any of this functionality
will become available.

We don't see how the Linux/SGX community can effectively debug and
support this driver without some kind of an idea as to what hardware
to be acquiring to test this functionality.  I'm assuming that Intel
has 'preferred partners' which do have access to this knowledge, which
is fine, but it would seem odd to expect general community support of
a driver that uses this model.

It would be a significant statement in support of the community if the
documentation for the driver included a table of functionality and the
chip and chipset versions needed to support the stated functionality.
That would significantly increase the ability for this driver to be
supported and tested.

Once again, thanks for all the legwork on the driver, however you are
managing to exercise its functionality.

Dr. Greg

As always,
Dr. Greg Wettstein, Ph.D.   Enjellic Systems Development, LLC.
4206 N. 19th Ave.           Specializing in information infra-structure
Fargo, ND  58102            development.
PH: 701-281-1686
FAX: 701-281-3949           EMAIL: greg@enjellic.com
------------------------------------------------------------------------------
"The couple is registered at Herbergers, Target and Fleet Farm."
                                -- Wedding invitation
                                   West Central Minnesota

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-30  1:45               ` Huang, Kai
@ 2018-08-31 17:43                 ` Sean Christopherson
  2018-08-31 21:34                   ` Dr. Greg
  2018-09-03 18:15                 ` Jarkko Sakkinen
  1 sibling, 1 reply; 103+ messages in thread
From: Sean Christopherson @ 2018-08-31 17:43 UTC (permalink / raw)
  To: Huang, Kai
  Cc: Jarkko Sakkinen, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

On Wed, Aug 29, 2018 at 06:45:29PM -0700, Huang, Kai wrote:
> > > > > > Some kind of counter is required to keep track of the power cycle.
> > > > > > When going to sleep the sgx_pm_cnt is increased. sgx_einit()
> > > > > > compares the current value of the global count to the value in
> > > > > > the cache entry to see whether we are in a new power cycle.
> > > > >
> > > > > You mean reset to Intel default? I think we can also just reset
> > > > > the cached MSR values on each power cycle, which would be simpler,
> > IMHO?
> > > >
> > > > Refresh my brain, does hardware reset the MSRs on a transition to S3 or
> > lower?
> 
> Sorry I missed this one. To be honest I don't know. I checked the SDM and all I can find is:
> 
> "On reset, the default value is the digest of Intel's signing key."

I confirmed the MSRs are reset any time the EPC is lost.  Not sure
what happens if the MSRs contained a non-Intel value but feature
control is locked with SGX launch control disabled.  I'll post an
update when I have an answer.
 
> Jarkko may know.
> 
> > > >
> > > > > I think we definitely need some code to handle S3-S5, but should
> > > > > be in separate patches, since I think the major impact of S3-S5 is
> > > > > entire EPC being destroyed. I think keeping pm_cnt is not
> > > > > sufficient enough to handle such case?
> > > > > >
> > > > > > This brings up one question though: how do we deal with VM host
> > > > > > going to
> > > > sleep?
> > > > > > VM guest would not be aware of this.
> > > > >
> > > > > IMO VM just gets "sudden loss of EPC" after suspend & resume in host.
> > > > > SGX driver and SDK should be able to handle "sudden loss of EPC",
> > > > > ie, co-working together to re-establish the missing enclaves.
> > > > >
> > > > > Actually supporting "sudden loss of EPC" is a requirement to
> > > > > support live migration of VM w/ SGX. Internally long time ago we
> > > > > had a discussion and the decision was we should support SGX live
> > > > > migration given
> > > > two facts:
> > > > >
> > > > > 1) losing platform-dependent is not important. For example, losing
> > > > > sealing key is not a problem, as we could get secrets provisioned
> > > > > again from remote. 2) Both windows & linux driver commit to
> > > > > support "sudden
> > > > loss of EPC".
> > > > >
> > > > > I don't think we have to support in very first upstream driver,
> > > > > but I think we need to support someday.
> > > >
> > > > Actually, we can easily support this in the driver, at least for SGX1 hardware.
> > >
> > > That's my guess too. Just want to check whether we are still on the
> > > same page :)
> > >
> > > > SGX2 isn't difficult to handle, but we've intentionally postponed
> > > > those patches until SGX1 support is in mainline[1].
> > > > Accesses to the EPC after it is lost will cause faults.  Userspace EPC accesses,
> > e.g.
> > > > ERESUME, will get a SIGSEGV that the process should interpret as an
> > > > "I should restart my enclave" event.  The SDK already does this.  In
> > > > the driver, we just need to be aware of this potential behavior and
> > > > not freak out.  Specifically, SGX_INVD needs to not WARN on faults that may
> > have been due to a the EPC being nuked.
> > > > I think we can even remove the sgx_encl_pm_notifier() code altogether.
> > >
> > > Possibly we still need to do some cleanup, ie, all structures of enclaves, upon
> > resume?
> > 
> > Not for functional reasons.  The driver will automatically do the cleanup via
> > SGX_INVD when it next accesses the enclave's pages and takes a fault, e.g.
> > during reclaim.  Proactively reclaiming the EPC pages would probably affect
> > performance, though not necessarily in a good way.  And I think it would be a
> > beneficial to get the driver out of the suspend/hibernate/resume paths, e.g.
> > zapping all enclaves could noticeably impact suspend/resume latency.
> 
> Sure.
> 
> Thanks,
> -Kai
> 

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-31 12:17         ` Jarkko Sakkinen
@ 2018-08-31 18:15           ` Sean Christopherson
  2018-09-03 19:19             ` Jarkko Sakkinen
  0 siblings, 1 reply; 103+ messages in thread
From: Sean Christopherson @ 2018-08-31 18:15 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: Huang, Kai, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

On Fri, Aug 31, 2018 at 03:17:03PM +0300, Jarkko Sakkinen wrote:
> On Wed, Aug 29, 2018 at 07:33:54AM +0000, Huang, Kai wrote:
> > [snip..]
> > 
> > > > >
> > > > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);  static
> > > > > DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > > > >  static struct task_struct *ksgxswapd_tsk;  static
> > > > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > > > +static struct notifier_block sgx_pm_notifier; static u64
> > > > > +sgx_pm_cnt;
> > > > > +
> > > > > +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx
> > > > > +MSRs
> > > > > for each
> > > > > + * CPU. The entries are initialized when they are first used by
> > > > > sgx_einit().
> > > > > + */
> > > > > +struct sgx_lepubkeyhash {
> > > > > +	u64 msrs[4];
> > > > > +	u64 pm_cnt;
> > > >
> > > > May I ask why do we need pm_cnt here? In fact why do we need suspend
> > > > staff (namely, sgx_pm_cnt above, and related code in this patch) here
> > > > in this patch? From the patch commit message I don't see why we need
> > > > PM staff here. Please give comment why you need PM staff, or you may
> > > > consider to split the PM staff to another patch.
> > > 
> > > Refining the commit message probably makes more sense because without PM
> > > code sgx_einit() would be broken. The MSRs have been reset after waking up.
> > > 
> > > Some kind of counter is required to keep track of the power cycle. When going
> > > to sleep the sgx_pm_cnt is increased. sgx_einit() compares the current value of
> > > the global count to the value in the cache entry to see whether we are in a new
> > > power cycle.
> > 
> > You mean reset to Intel default? I think we can also just reset the
> > cached MSR values on each power cycle, which would be simpler, IMHO?
> 
> I don't really see that much difference in the complexity.

Tracking the validity of the cache means we're hosed if we miss any
condition that causes the MSRs to be reset.  I think we're better off
assuming the cache can be stale at any time, i.e. don't track power
cyles and instead handle EINIT failure due to INVALID_TOKEN by writing
the cache+MSRs with the desired hash and retrying EINIT.  EINIT is
interruptible and its latency is extremely variable in any case, e.g.
tens of thousands of cycles, so this rarely-hit "slow path" probably
wouldn't affect the worst case latency of EINIT.
 
> > I think we definitely need some code to handle S3-S5, but should be in
> > separate patches, since I think the major impact of S3-S5 is entire
> > EPC being destroyed. I think keeping pm_cnt is not sufficient enough
> > to handle such case?
> 
> The driver has SGX_POWER_LOST_ENCLAVE for ioctls and it deletes the TCS
> entries.
> 
> > > This brings up one question though: how do we deal with VM host going to sleep?
> > > VM guest would not be aware of this.
> > 
> > IMO VM just gets "sudden loss of EPC" after suspend & resume in host.
> > SGX driver and SDK should be able to handle "sudden loss of EPC", ie,
> > co-working together to re-establish the missing enclaves.
> 
> This is not about EPC. It is already dealt by the driver. I'm concerned
> about the MSR cache as it would mess up.
> 
> But I guess this logic is part of the KVM code anyway now that I think
> more of it.

Ya, I expect that VMMs will preserve VM's virtual pubkey MSRs, though
there might be scenarios where a VM has direct access to the hardware
MSRs.  This is probably a moot point since I don't think we want to
assume the kernel's cache is 100% accurate, regardless of environment.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-31 17:43                 ` Sean Christopherson
@ 2018-08-31 21:34                   ` Dr. Greg
  2018-09-03 19:27                     ` Jarkko Sakkinen
  0 siblings, 1 reply; 103+ messages in thread
From: Dr. Greg @ 2018-08-31 21:34 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Huang, Kai, Jarkko Sakkinen, platform-driver-x86, x86, nhorman,
	linux-kernel, tglx, suresh.b.siddha, Ayoun, Serge, hpa,
	npmccallum, mingo, linux-sgx, Hansen, Dave

On Fri, Aug 31, 2018 at 10:43:30AM -0700, Sean Christopherson wrote:

Good afternoon to everyone.

> > Sorry I missed this one. To be honest I don't know. I checked the
> > SDM and all I can find is:
> >
> > "On reset, the default value is the digest of Intel's signing key."

> I confirmed the MSRs are reset any time the EPC is lost.  Not sure
> what happens if the MSRs contained a non-Intel value but feature
> control is locked with SGX launch control disabled.  I'll post an
> update when I have an answer.

It was our interpretation from the SDM that the identity modulus
signature MSR's are 'trap-door' registers.  If flexible launch control
(FLC) is enabled the platform has one opportunity to write a new
signature value, after which the registers are locked from
modification until the next platform reset.

From a security architecture perspective it seemed that an FLC based
SGX implementation would use a modified version of TBOOT to securely
write that register once per platform boot/reset.  The architecture
that is being discussed where there is a need to continually check
whether or not the correct root signing key is loaded sounds a bit
clunky at best.

At worst it has potential security implications since it is the
reponsibility of the enclave launch control infrastructure to control
which enclaves are allowed to have the PROVISION_KEY attribute bit
set.

Have a good weekend.

Dr. Greg

As always,
Dr. G.W. Wettstein, Ph.D.   Enjellic Systems Development, LLC.
4206 N. 19th Ave.           Specializing in information infra-structure
Fargo, ND  58102            development.
PH: 701-281-1686
FAX: 701-281-3949           EMAIL: greg@enjellic.com
------------------------------------------------------------------------------
"Extensive interviews show that not one alcoholic has ever actually seen
 a pink elephant."
                                -- Yale University
                                   Center of Alcohol Studies

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 01/13] x86/sgx: Update MAINTAINERS
  2018-08-27 18:53 ` [PATCH v13 01/13] x86/sgx: Update MAINTAINERS Jarkko Sakkinen
@ 2018-09-03 12:56   ` Andy Shevchenko
  2018-09-03 19:10     ` Jarkko Sakkinen
  0 siblings, 1 reply; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-03 12:56 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, David S. Miller, Mauro Carvalho Chehab,
	Greg Kroah-Hartman, Andrew Morton, Arnd Bergmann,
	Linux Kernel Mailing List

On Mon, Aug 27, 2018 at 9:56 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
>
> Add the maintainer information for the SGX subsystem.
>
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> ---
>  MAINTAINERS | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 24b200d91b30..877fbc6ef7a7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7562,6 +7562,13 @@ L:       linux-gpio@vger.kernel.org
>  S:     Maintained
>  F:     drivers/gpio/gpio-intel-mid.c
>
> +INTEL SGX

It should go in between of

INTEL RDMA RNIC DRIVER
...
INTEL SHA MULTIBUFFER DRIVER

> +M:     Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> +L:     linux-sgx@vger.kernel.org
> +Q:     https://patchwork.kernel.org/project/intel-sgx/list/
> +F:     drivers/platform/x86/intel_sgx/
> +K:     \bSGX_
> +
>  INVENSENSE MPU-3050 GYROSCOPE DRIVER


-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 04/13] x86/sgx: Architectural structures
  2018-08-27 18:53 ` [PATCH v13 04/13] x86/sgx: Architectural structures Jarkko Sakkinen
  2018-08-27 19:41   ` Dave Hansen
@ 2018-09-03 13:16   ` Andy Shevchenko
  2018-09-03 19:17     ` Jarkko Sakkinen
  2018-09-04 16:04     ` Dave Hansen
  1 sibling, 2 replies; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-03 13:16 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Linux Kernel Mailing List

On Mon, Aug 27, 2018 at 9:57 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
>
> Add arch/x86/include/asm/sgx_arch.h, which contains definitions for the
> architectural data structures used by the CPU to implement the SGX.

> +/**
> + * enum sgx_encls_leaves - ENCLS leaf functions
> + * %ECREATE:   Create an enclave.
> + * %EADD:      Add a page to an enclave.
> + * %EINIT:     Launch an enclave.
> + * %EREMOVE:   Remove a page from an enclave.
> + * %EDBGRD:    Read a word from an enclve (peek).
> + * %EDBGWR:    Write a word to an enclave (poke).
> + * %EEXTEND:   Measure 256 bytes of an added enclave page.
> + * %ELDB:      Load a swapped page in blocked state.
> + * %ELDU:      Load a swapped page in unblocked state.
> + * %EBLOCK:    Change page state to blocked i.e. entering hardware threads
> + *             cannot access it and create new TLB entries.
> + * %EPA:       Create a Version Array (VA) page used to store isvsvn number
> + *             for a swapped EPC page.
> + * %EWB:       Swap an enclave page to the regular memory. Checks that all
> + *             threads have exited that were in the previous shoot-down
> + *             sequence.
> + * %ETRACK:    Start a new shoot down sequence. Used to together with EBLOCK
> + *             to make sure that a page is safe to swap.
> + */
> +enum sgx_encls_leaves {
> +       ECREATE = 0x0,
> +       EADD    = 0x1,
> +       EINIT   = 0x2,
> +       EREMOVE = 0x3,
> +       EDGBRD  = 0x4,
> +       EDGBWR  = 0x5,
> +       EEXTEND = 0x6,
> +       ELDB    = 0x7,
> +       ELDU    = 0x8,
> +       EBLOCK  = 0x9,
> +       EPA     = 0xA,
> +       EWB     = 0xB,
> +       ETRACK  = 0xC,
> +       EAUG    = 0xD,
> +       EMODPR  = 0xE,
> +       EMODT   = 0xF,
> +};

Hmm... This E prefix confuses me with (system wide) error codes. Has
it been discussed before? If so, can you point on the conclusion why
the current format is good?

> +enum sgx_miscselect {
> +       SGX_MISC_EXINFO         = 0x01,
> +};
> +
> +#define SGX_MISC_RESERVED_MASK 0xFFFFFFFFFFFFFFFEULL

Any idea why we are not using BIT_ULL() / BIT() and GENMASK_ULL() /
GENMASK() in the code?

> +enum sgx_attribute {
> +       SGX_ATTR_DEBUG          = 0x02,
> +       SGX_ATTR_MODE64BIT      = 0x04,
> +       SGX_ATTR_PROVISIONKEY   = 0x10,
> +       SGX_ATTR_EINITTOKENKEY  = 0x20,
> +};
> +
> +#define SGX_ATTR_RESERVED_MASK 0xFFFFFFFFFFFFFFC9ULL

Some times listing explicitly not-reserved bits might be better and
figuring out reserved mask is a simple ~ operation.

> +enum sgx_tcs_flags {
> +       SGX_TCS_DBGOPTIN        = 0x01,
> +};
> +
> +#define SGX_TCS_RESERVED_MASK 0xFFFFFFFFFFFFFFFEULL

> +#define SGX_SECINFO_PERMISSION_MASK    0x0000000000000007ULL
> +#define SGX_SECINFO_PAGE_TYPE_MASK     0x000000000000FF00ULL
> +#define SGX_SECINFO_RESERVED_MASK      0xFFFFFFFFFFFF00F8ULL

So, something like

MASK1 GENMASK_ULL
MASK2 GENMASK_ULL
MASK3 ~(MASK1  | MASK2)

?

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-27 18:53 ` [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves Jarkko Sakkinen
  2018-08-27 21:41   ` Huang, Kai
@ 2018-09-03 13:53   ` Jann Horn
  2018-09-04  9:55     ` Jarkko Sakkinen
  2018-09-04 16:05   ` Andy Shevchenko
  2 siblings, 1 reply; 103+ messages in thread
From: Jann Horn @ 2018-09-03 13:53 UTC (permalink / raw)
  To: jarkko.sakkinen
  Cc: the arch/x86 maintainers, platform-driver-x86, Dave Hansen,
	sean.j.christopherson, nhorman, npmccallum, linux-sgx,
	Thomas Gleixner, Ingo Molnar, H . Peter Anvin, suresh.b.siddha,
	serge.ayoun, kernel list

On Mon, Sep 3, 2018 at 3:33 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
>
> From: Sean Christopherson <sean.j.christopherson@intel.com>
>
> Add a function to perform ENCLS(EINIT), which initializes an enclave,
> which can be used by a driver for running enclaves and VMMs.
>
> Writing the LE hash MSRs is extraordinarily expensive, e.g. 3-4x slower
> than normal MSRs, so we use a per-cpu cache to track the last known value
> of the MSRs to avoid unnecessarily writing the MSRs with the current value.
>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
[...]
> +/**
> + * sgx_einit - initialize an enclave
> + * @sigstruct:         a pointer to the SIGSTRUCT
> + * @token:             a pointer to the EINITTOKEN
> + * @secs_page:         a pointer to the SECS EPC page
> + * @lepubkeyhash:      the desired value for IA32_SGXLEPUBKEYHASHx MSRs
> + *
> + * Try to perform EINIT operation. If the MSRs are writable, they are updated
> + * according to @lepubkeyhash.
> + *
> + * Return:
> + *   0 on success,
> + *   -errno on failure
> + *   SGX error code if EINIT fails
> + */
> +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken *token,
> +             struct sgx_epc_page *secs_page, u64 lepubkeyhash[4])
> +{
> +       struct sgx_lepubkeyhash __percpu *cache;
> +       bool cache_valid;
> +       int i, ret;
> +
> +       if (!sgx_lc_enabled)
> +               return __einit(sigstruct, token, sgx_epc_addr(secs_page));
> +
> +       cache = per_cpu(sgx_lepubkeyhash_cache, smp_processor_id());

At this point, preemption must be off, because smp_processor_id() is
called; I don't think it is off here? If you have hardware/emulation
on which you can test this, you may want to test your patches with
DEBUG_PREEMPT enabled.

> +       if (!cache) {
> +               cache = kzalloc(sizeof(struct sgx_lepubkeyhash), GFP_KERNEL);

But then here you do a GFP_KERNEL allocation, which can sleep.

Also: After "cache" has been allocated in this branch, when do you
store the reference to it? As far as I can tell, you never write to
sgx_lepubkeyhash_cache, and the allocation just leaks.

> +               if (!cache)
> +                       return -ENOMEM;
> +       }
> +
> +       cache_valid = cache->pm_cnt == sgx_pm_cnt;

The cache should probably not be treated as valid if it has just been
created and only contains zeroes, right?

> +       cache->pm_cnt = sgx_pm_cnt;

Can sgx_pm_cnt be modified concurrently? If so, please use at least
READ_ONCE() to document that and prevent the compiler from doing weird
stuff.

> +       preempt_disable();

And here you turn off preemption, but it should already have been off?

> +       for (i = 0; i < 4; i++) {
> +               if (cache_valid && lepubkeyhash[i] == cache->msrs[i])
> +                       continue;
> +
> +               wrmsrl(MSR_IA32_SGXLEPUBKEYHASH0 + i, lepubkeyhash[i]);
> +               cache->msrs[i] = lepubkeyhash[i];
> +       }
> +       ret = __einit(sigstruct, token, sgx_epc_addr(secs_page));
> +       preempt_enable();
> +       return ret;
> +}
> +EXPORT_SYMBOL(sgx_einit);
> +

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 06/13] x86/sgx: Detect Intel SGX
  2018-08-27 18:53 ` [PATCH v13 06/13] x86/sgx: Detect Intel SGX Jarkko Sakkinen
  2018-08-27 19:53   ` Dave Hansen
@ 2018-09-03 14:26   ` Andy Shevchenko
  2018-09-04  9:56     ` Jarkko Sakkinen
  1 sibling, 1 reply; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-03 14:26 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, suresh.b.siddha, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, serge.ayoun, Rafael J. Wysocki,
	Borislav Petkov, Reinette Chatre, Andi Kleen, Greg Kroah-Hartman,
	Kirill A. Shutemov, Linux Kernel Mailing List

On Mon, Aug 27, 2018 at 9:57 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
>
> From: Sean Christopherson <sean.j.christopherson@intel.com>
>
> Intel(R) SGX is a set of CPU instructions that can be used by applications
> to set aside private regions of code and data. The code outside the enclave
> is disallowed to access the memory inside the enclave by the CPU access
> control.
>
> Add a check for SGX to arch/x86 and a new config option, INTEL_SGX_CORE.
> Expose a boolean variable 'sgx_enabled' to query whether or not the SGX
> support is available.

> +       prompt "Intel SGX core functionality"
> +       def_bool n

Default 'default' is 'n'. Perhaps changing prompt to bool will make it
one line less.

> +#include <asm/sgx.h>
> +#include <asm/sgx_pr.h>

Don't we put linux/* followed by asm/* ?

> +#include <linux/freezer.h>
> +#include <linux/highmem.h>
> +#include <linux/kthread.h>
> +#include <linux/ratelimit.h>
> +#include <linux/sched/signal.h>
> +#include <linux/slab.h>

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-08-27 18:53 ` [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages Jarkko Sakkinen
  2018-08-27 21:07   ` Dave Hansen
@ 2018-09-03 14:41   ` Andy Shevchenko
  2018-09-04  9:59     ` Jarkko Sakkinen
  2018-09-04 17:49     ` Sean Christopherson
  1 sibling, 2 replies; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-03 14:41 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, suresh.b.siddha, Linux Kernel Mailing List

On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
>
> Add data structures to track Enclave Page Cache (EPC) pages.  EPC is
> divided into multiple banks (1-N) of which addresses and sizes can be
> enumerated with CPUID by the OS.
>
> On NUMA systems a node can have at most bank. A bank can be at most part of
> two nodes. SGX supports both nodes with a single memory controller and also
> sub-cluster nodes with severals memory controllers on a single die.

> -#include <asm/sgx.h>
> -#include <asm/sgx_pr.h>
>  #include <linux/freezer.h>
>  #include <linux/highmem.h>
>  #include <linux/kthread.h>
> +#include <linux/pagemap.h>
>  #include <linux/ratelimit.h>
>  #include <linux/sched/signal.h>
> +#include <linux/shmem_fs.h>
>  #include <linux/slab.h>
> +#include <asm/sgx.h>
> +#include <asm/sgx_pr.h>

Squash issues?

> +       va = ioremap_cache(addr, size);
> +       if (!va)
> +               return -ENOMEM;

I'm not sure this is a right API. Do we operate with memory? Does it
have I/O side effects?
If no, memremap() would be better to use.

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 08/13] x86/sgx: Add wrappers for ENCLS leaf functions
  2018-08-27 18:53 ` [PATCH v13 08/13] x86/sgx: Add wrappers for ENCLS leaf functions Jarkko Sakkinen
@ 2018-09-03 15:01   ` Andy Shevchenko
  2018-09-04 11:09     ` Jarkko Sakkinen
  0 siblings, 1 reply; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-03 15:01 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, serge.ayoun, suresh.b.siddha,
	Linux Kernel Mailing List

On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
>
> Add wrappers for Intel(R) SGX ENCLS opcode leaf functions except
> ENCLS(EINIT). ENCLS invokes privileged functions for managing (creation,
> initialization and swapping) and debugging enclaves.

> +#define ENCLS_FAULT_FLAG 0x40000000UL
> +#define ENCLS_FAULT_FLAG_ASM "$0x40000000"

Hmm... Why it can't have same name?

See, how _AC() macro is defined and being used.

> +#define ENCLS_TRAPNR(r) ((r) & ~ENCLS_FAULT_FLAG)

If result of macro is assigned to some variable and (r) by some reason
is 32-bit type
and you compile as 64-bit object, compiler will warn here.
Please, check this is not the case in any of use of this macro.
Otherwise you need a type casting, like

foo = bar & (u32)~BAR;

(or using typeof() might work)

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-30  1:45               ` Huang, Kai
  2018-08-31 17:43                 ` Sean Christopherson
@ 2018-09-03 18:15                 ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-03 18:15 UTC (permalink / raw)
  To: Huang, Kai
  Cc: Christopherson, Sean J, platform-driver-x86, x86, nhorman,
	linux-kernel, tglx, suresh.b.siddha, Ayoun, Serge, hpa,
	npmccallum, mingo, linux-sgx, Hansen, Dave

On Thu, Aug 30, 2018 at 01:45:29AM +0000, Huang, Kai wrote:
> > > > Refresh my brain, does hardware reset the MSRs on a transition to S3 or
> > lower?
> 
> Sorry I missed this one. To be honest I don't know. I checked the SDM and all I can find is:
> 
> "On reset, the default value is the digest of Intel's signing key."
> 
> Jarkko may know.

I found this out by testing. The cached MSR values stop working after
waking up from S3. Have not found anything better from the SDM but it
is the behavior that I've observed on my GLK NUC at least.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-27 18:53 ` [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager Jarkko Sakkinen
  2018-08-27 21:14   ` Dave Hansen
  2018-08-27 21:15   ` Dave Hansen
@ 2018-09-03 19:02   ` Andy Shevchenko
  2018-09-04 15:38     ` Jarkko Sakkinen
  2018-09-11 15:04   ` Sean Christopherson
  3 siblings, 1 reply; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-03 19:02 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, suresh.b.siddha, serge.ayoun,
	Linux Kernel Mailing List

On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
>
> Add a Enclave Page Cache (EPC) memory manager that can be used to
> allocate and free EPC pages. The swapper thread ksgxswapd reclaims pages
> on the event when the number of free EPC pages goes below
> %SGX_NR_LOW_PAGES up until it reaches %SGX_NR_HIGH_PAGES.
>
> Pages are reclaimed in LRU fashion from a global list. The consumers
> take care of calling EBLOCK (block page from new accesses), ETRACK
> (restart counting the entering hardware threads) and EWB (write page to
> the regular memory) because executing these operations usually (if not
> always) requires to do some subsystem-internal locking operations.

> +                       list_del(&page->list);

Is this page will be completely gone? Otherwise it might be needed to
reinit list head here as well.

> +       WARN(ret < 0, "sgx: cannot free page, reclaim in-progress");
> +       WARN(ret > 0, "sgx: EREMOVE returned %d (0x%x)", ret, ret);

I'm not sure (though it's easy to check) that you need sgx: prefix
here. WARN() might take pr_fmt() if defined.

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 01/13] x86/sgx: Update MAINTAINERS
  2018-09-03 12:56   ` Andy Shevchenko
@ 2018-09-03 19:10     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-03 19:10 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, David S. Miller, Mauro Carvalho Chehab,
	Greg Kroah-Hartman, Andrew Morton, Arnd Bergmann,
	Linux Kernel Mailing List

On Mon, Sep 03, 2018 at 03:56:05PM +0300, Andy Shevchenko wrote:
> On Mon, Aug 27, 2018 at 9:56 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> >
> > Add the maintainer information for the SGX subsystem.
> >
> > Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> > ---
> >  MAINTAINERS | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 24b200d91b30..877fbc6ef7a7 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -7562,6 +7562,13 @@ L:       linux-gpio@vger.kernel.org
> >  S:     Maintained
> >  F:     drivers/gpio/gpio-intel-mid.c
> >
> > +INTEL SGX
> 
> It should go in between of
> 
> INTEL RDMA RNIC DRIVER
> ...
> INTEL SHA MULTIBUFFER DRIVER

Thanks, I'll put into the correct place.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 04/13] x86/sgx: Architectural structures
  2018-09-03 13:16   ` Andy Shevchenko
@ 2018-09-03 19:17     ` Jarkko Sakkinen
  2018-09-04 16:04     ` Dave Hansen
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-03 19:17 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, Linux Kernel Mailing List

On Mon, Sep 03, 2018 at 04:16:42PM +0300, Andy Shevchenko wrote:
> On Mon, Aug 27, 2018 at 9:57 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> >
> > Add arch/x86/include/asm/sgx_arch.h, which contains definitions for the
> > architectural data structures used by the CPU to implement the SGX.
> 
> > +/**
> > + * enum sgx_encls_leaves - ENCLS leaf functions
> > + * %ECREATE:   Create an enclave.
> > + * %EADD:      Add a page to an enclave.
> > + * %EINIT:     Launch an enclave.
> > + * %EREMOVE:   Remove a page from an enclave.
> > + * %EDBGRD:    Read a word from an enclve (peek).
> > + * %EDBGWR:    Write a word to an enclave (poke).
> > + * %EEXTEND:   Measure 256 bytes of an added enclave page.
> > + * %ELDB:      Load a swapped page in blocked state.
> > + * %ELDU:      Load a swapped page in unblocked state.
> > + * %EBLOCK:    Change page state to blocked i.e. entering hardware threads
> > + *             cannot access it and create new TLB entries.
> > + * %EPA:       Create a Version Array (VA) page used to store isvsvn number
> > + *             for a swapped EPC page.
> > + * %EWB:       Swap an enclave page to the regular memory. Checks that all
> > + *             threads have exited that were in the previous shoot-down
> > + *             sequence.
> > + * %ETRACK:    Start a new shoot down sequence. Used to together with EBLOCK
> > + *             to make sure that a page is safe to swap.
> > + */
> > +enum sgx_encls_leaves {
> > +       ECREATE = 0x0,
> > +       EADD    = 0x1,
> > +       EINIT   = 0x2,
> > +       EREMOVE = 0x3,
> > +       EDGBRD  = 0x4,
> > +       EDGBWR  = 0x5,
> > +       EEXTEND = 0x6,
> > +       ELDB    = 0x7,
> > +       ELDU    = 0x8,
> > +       EBLOCK  = 0x9,
> > +       EPA     = 0xA,
> > +       EWB     = 0xB,
> > +       ETRACK  = 0xC,
> > +       EAUG    = 0xD,
> > +       EMODPR  = 0xE,
> > +       EMODT   = 0xF,
> > +};
> 
> Hmm... This E prefix confuses me with (system wide) error codes. Has
> it been discussed before? If so, can you point on the conclusion why
> the current format is good?

That is how they are prefixed in the SDM.

> > +enum sgx_miscselect {
> > +       SGX_MISC_EXINFO         = 0x01,
> > +};
> > +
> > +#define SGX_MISC_RESERVED_MASK 0xFFFFFFFFFFFFFFFEULL
> 
> Any idea why we are not using BIT_ULL() / BIT() and GENMASK_ULL() /
> GENMASK() in the code?

No good reason. I'll change it.

> > +enum sgx_attribute {
> > +       SGX_ATTR_DEBUG          = 0x02,
> > +       SGX_ATTR_MODE64BIT      = 0x04,
> > +       SGX_ATTR_PROVISIONKEY   = 0x10,
> > +       SGX_ATTR_EINITTOKENKEY  = 0x20,
> > +};
> > +
> > +#define SGX_ATTR_RESERVED_MASK 0xFFFFFFFFFFFFFFC9ULL
> 
> Some times listing explicitly not-reserved bits might be better and
> figuring out reserved mask is a simple ~ operation.

Yea, agreed.

> > +enum sgx_tcs_flags {
> > +       SGX_TCS_DBGOPTIN        = 0x01,
> > +};
> > +
> > +#define SGX_TCS_RESERVED_MASK 0xFFFFFFFFFFFFFFFEULL
> 
> > +#define SGX_SECINFO_PERMISSION_MASK    0x0000000000000007ULL
> > +#define SGX_SECINFO_PAGE_TYPE_MASK     0x000000000000FF00ULL
> > +#define SGX_SECINFO_RESERVED_MASK      0xFFFFFFFFFFFF00F8ULL
> 
> So, something like
> 
> MASK1 GENMASK_ULL
> MASK2 GENMASK_ULL
> MASK3 ~(MASK1  | MASK2)
> 
> ?

Definitely. I think it is just a matter of legacy why they are like they
are :-) These constants have gone over long time and they are not
usually places where you have to look for regressions. Thanks for
spotting these.

> 
> -- 
> With Best Regards,
> Andy Shevchenko

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-31 18:15           ` Sean Christopherson
@ 2018-09-03 19:19             ` Jarkko Sakkinen
  2018-09-03 23:45               ` Huang, Kai
  0 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-03 19:19 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Huang, Kai, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

On Fri, Aug 31, 2018 at 11:15:09AM -0700, Sean Christopherson wrote:
> On Fri, Aug 31, 2018 at 03:17:03PM +0300, Jarkko Sakkinen wrote:
> > On Wed, Aug 29, 2018 at 07:33:54AM +0000, Huang, Kai wrote:
> > > [snip..]
> > > 
> > > > > >
> > > > > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);  static
> > > > > > DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > > > > >  static struct task_struct *ksgxswapd_tsk;  static
> > > > > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > > > > +static struct notifier_block sgx_pm_notifier; static u64
> > > > > > +sgx_pm_cnt;
> > > > > > +
> > > > > > +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx
> > > > > > +MSRs
> > > > > > for each
> > > > > > + * CPU. The entries are initialized when they are first used by
> > > > > > sgx_einit().
> > > > > > + */
> > > > > > +struct sgx_lepubkeyhash {
> > > > > > +	u64 msrs[4];
> > > > > > +	u64 pm_cnt;
> > > > >
> > > > > May I ask why do we need pm_cnt here? In fact why do we need suspend
> > > > > staff (namely, sgx_pm_cnt above, and related code in this patch) here
> > > > > in this patch? From the patch commit message I don't see why we need
> > > > > PM staff here. Please give comment why you need PM staff, or you may
> > > > > consider to split the PM staff to another patch.
> > > > 
> > > > Refining the commit message probably makes more sense because without PM
> > > > code sgx_einit() would be broken. The MSRs have been reset after waking up.
> > > > 
> > > > Some kind of counter is required to keep track of the power cycle. When going
> > > > to sleep the sgx_pm_cnt is increased. sgx_einit() compares the current value of
> > > > the global count to the value in the cache entry to see whether we are in a new
> > > > power cycle.
> > > 
> > > You mean reset to Intel default? I think we can also just reset the
> > > cached MSR values on each power cycle, which would be simpler, IMHO?
> > 
> > I don't really see that much difference in the complexity.
> 
> Tracking the validity of the cache means we're hosed if we miss any
> condition that causes the MSRs to be reset.  I think we're better off
> assuming the cache can be stale at any time, i.e. don't track power
> cyles and instead handle EINIT failure due to INVALID_TOKEN by writing
> the cache+MSRs with the desired hash and retrying EINIT.  EINIT is
> interruptible and its latency is extremely variable in any case, e.g.
> tens of thousands of cycles, so this rarely-hit "slow path" probably
> wouldn't affect the worst case latency of EINIT.

Sounds a good refiniment. Pretty good solution to heal from host sleep
on the guest VM and then there is no need for driver changes.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-31 21:34                   ` Dr. Greg
@ 2018-09-03 19:27                     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-03 19:27 UTC (permalink / raw)
  To: Dr. Greg
  Cc: Sean Christopherson, Huang, Kai, platform-driver-x86, x86,
	nhorman, linux-kernel, tglx, suresh.b.siddha, Ayoun, Serge, hpa,
	npmccallum, mingo, linux-sgx, Hansen, Dave

On Fri, Aug 31, 2018 at 04:34:45PM -0500, Dr. Greg wrote:
> On Fri, Aug 31, 2018 at 10:43:30AM -0700, Sean Christopherson wrote:
> 
> Good afternoon to everyone.
> 
> > > Sorry I missed this one. To be honest I don't know. I checked the
> > > SDM and all I can find is:
> > >
> > > "On reset, the default value is the digest of Intel's signing key."
> 
> > I confirmed the MSRs are reset any time the EPC is lost.  Not sure
> > what happens if the MSRs contained a non-Intel value but feature
> > control is locked with SGX launch control disabled.  I'll post an
> > update when I have an answer.
> 
> It was our interpretation from the SDM that the identity modulus
> signature MSR's are 'trap-door' registers.  If flexible launch control
> (FLC) is enabled the platform has one opportunity to write a new
> signature value, after which the registers are locked from
> modification until the next platform reset.

In the driver we support only MSRs that are left writable by the BIOS
before locking the feature control.

> From a security architecture perspective it seemed that an FLC based
> SGX implementation would use a modified version of TBOOT to securely
> write that register once per platform boot/reset.  The architecture
> that is being discussed where there is a need to continually check
> whether or not the correct root signing key is loaded sounds a bit
> clunky at best.
> 
> At worst it has potential security implications since it is the
> reponsibility of the enclave launch control infrastructure to control
> which enclaves are allowed to have the PROVISION_KEY attribute bit
> set.

Based on the previous feedback supporting read-only MSRs in the driver
is an unwanted feature i.e. the kernel must be able to decide what gets
lauched (i.e. no launch enclave).

> Have a good weekend.
> 
> Dr. Greg
> 
> As always,
> Dr. G.W. Wettstein, Ph.D.   Enjellic Systems Development, LLC.
> 4206 N. 19th Ave.           Specializing in information infra-structure
> Fargo, ND  58102            development.
> PH: 701-281-1686
> FAX: 701-281-3949           EMAIL: greg@enjellic.com
> ------------------------------------------------------------------------------
> "Extensive interviews show that not one alcoholic has ever actually seen
>  a pink elephant."
>                                 -- Yale University
>                                    Center of Alcohol Studies

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* RE: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-09-03 19:19             ` Jarkko Sakkinen
@ 2018-09-03 23:45               ` Huang, Kai
  2018-09-04 14:54                 ` Sean Christopherson
  2018-09-04 15:26                 ` Jarkko Sakkinen
  0 siblings, 2 replies; 103+ messages in thread
From: Huang, Kai @ 2018-09-03 23:45 UTC (permalink / raw)
  To: Jarkko Sakkinen, Christopherson, Sean J
  Cc: platform-driver-x86, x86, nhorman, linux-kernel, tglx,
	suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo, linux-sgx,
	Hansen, Dave

> -----Original Message-----
> From: linux-sgx-owner@vger.kernel.org [mailto:linux-sgx-
> owner@vger.kernel.org] On Behalf Of Jarkko Sakkinen
> Sent: Tuesday, September 4, 2018 7:19 AM
> To: Christopherson, Sean J <sean.j.christopherson@intel.com>
> Cc: Huang, Kai <kai.huang@intel.com>; platform-driver-x86@vger.kernel.org;
> x86@kernel.org; nhorman@redhat.com; linux-kernel@vger.kernel.org;
> tglx@linutronix.de; suresh.b.siddha@intel.com; Ayoun, Serge
> <serge.ayoun@intel.com>; hpa@zytor.com; npmccallum@redhat.com;
> mingo@redhat.com; linux-sgx@vger.kernel.org; Hansen, Dave
> <dave.hansen@intel.com>
> Subject: Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
> 
> On Fri, Aug 31, 2018 at 11:15:09AM -0700, Sean Christopherson wrote:
> > On Fri, Aug 31, 2018 at 03:17:03PM +0300, Jarkko Sakkinen wrote:
> > > On Wed, Aug 29, 2018 at 07:33:54AM +0000, Huang, Kai wrote:
> > > > [snip..]
> > > >
> > > > > > >
> > > > > > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);
> > > > > > > static DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > > > > > >  static struct task_struct *ksgxswapd_tsk;  static
> > > > > > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > > > > > +static struct notifier_block sgx_pm_notifier; static u64
> > > > > > > +sgx_pm_cnt;
> > > > > > > +
> > > > > > > +/* The cache for the last known values of
> > > > > > > +IA32_SGXLEPUBKEYHASHx MSRs
> > > > > > > for each
> > > > > > > + * CPU. The entries are initialized when they are first
> > > > > > > + used by
> > > > > > > sgx_einit().
> > > > > > > + */
> > > > > > > +struct sgx_lepubkeyhash {
> > > > > > > +	u64 msrs[4];
> > > > > > > +	u64 pm_cnt;
> > > > > >
> > > > > > May I ask why do we need pm_cnt here? In fact why do we need
> > > > > > suspend staff (namely, sgx_pm_cnt above, and related code in
> > > > > > this patch) here in this patch? From the patch commit message
> > > > > > I don't see why we need PM staff here. Please give comment why
> > > > > > you need PM staff, or you may consider to split the PM staff to another
> patch.
> > > > >
> > > > > Refining the commit message probably makes more sense because
> > > > > without PM code sgx_einit() would be broken. The MSRs have been reset
> after waking up.
> > > > >
> > > > > Some kind of counter is required to keep track of the power
> > > > > cycle. When going to sleep the sgx_pm_cnt is increased.
> > > > > sgx_einit() compares the current value of the global count to
> > > > > the value in the cache entry to see whether we are in a new power cycle.
> > > >
> > > > You mean reset to Intel default? I think we can also just reset
> > > > the cached MSR values on each power cycle, which would be simpler,
> IMHO?
> > >
> > > I don't really see that much difference in the complexity.
> >
> > Tracking the validity of the cache means we're hosed if we miss any
> > condition that causes the MSRs to be reset.  I think we're better off
> > assuming the cache can be stale at any time, i.e. don't track power
> > cyles and instead handle EINIT failure due to INVALID_TOKEN by writing
> > the cache+MSRs with the desired hash and retrying EINIT.  EINIT is
> > interruptible and its latency is extremely variable in any case, e.g.
> > tens of thousands of cycles, so this rarely-hit "slow path" probably
> > wouldn't affect the worst case latency of EINIT.
> 
> Sounds a good refiniment. Pretty good solution to heal from host sleep on the
> guest VM and then there is no need for driver changes.

To me either way should be OK, keeping MSR cache or retrying EINIT, since EINIT should not be in performance critical path I think.

But INVALID_TOKEN is not only returned when MSRs are mismatched, so do you plan to check to rule out other cases that cause INVALID_TOKEN before retrying EINIT, or unconditionally  retry EINIT? And we should only retry once?

Thanks,
-Kai
> 
> /Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-09-03 13:53   ` Jann Horn
@ 2018-09-04  9:55     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-04  9:55 UTC (permalink / raw)
  To: Jann Horn
  Cc: the arch/x86 maintainers, platform-driver-x86, Dave Hansen,
	sean.j.christopherson, nhorman, npmccallum, linux-sgx,
	Thomas Gleixner, Ingo Molnar, H . Peter Anvin, suresh.b.siddha,
	serge.ayoun, kernel list

On Mon, Sep 03, 2018 at 03:53:24PM +0200, Jann Horn wrote:
> On Mon, Sep 3, 2018 at 3:33 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> >
> > From: Sean Christopherson <sean.j.christopherson@intel.com>
> >
> > Add a function to perform ENCLS(EINIT), which initializes an enclave,
> > which can be used by a driver for running enclaves and VMMs.
> >
> > Writing the LE hash MSRs is extraordinarily expensive, e.g. 3-4x slower
> > than normal MSRs, so we use a per-cpu cache to track the last known value
> > of the MSRs to avoid unnecessarily writing the MSRs with the current value.
> >
> > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> > Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> > Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> [...]
> > +/**
> > + * sgx_einit - initialize an enclave
> > + * @sigstruct:         a pointer to the SIGSTRUCT
> > + * @token:             a pointer to the EINITTOKEN
> > + * @secs_page:         a pointer to the SECS EPC page
> > + * @lepubkeyhash:      the desired value for IA32_SGXLEPUBKEYHASHx MSRs
> > + *
> > + * Try to perform EINIT operation. If the MSRs are writable, they are updated
> > + * according to @lepubkeyhash.
> > + *
> > + * Return:
> > + *   0 on success,
> > + *   -errno on failure
> > + *   SGX error code if EINIT fails
> > + */
> > +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken *token,
> > +             struct sgx_epc_page *secs_page, u64 lepubkeyhash[4])
> > +{
> > +       struct sgx_lepubkeyhash __percpu *cache;
> > +       bool cache_valid;
> > +       int i, ret;
> > +
> > +       if (!sgx_lc_enabled)
> > +               return __einit(sigstruct, token, sgx_epc_addr(secs_page));
> > +
> > +       cache = per_cpu(sgx_lepubkeyhash_cache, smp_processor_id());
> 
> At this point, preemption must be off, because smp_processor_id() is
> called; I don't think it is off here? If you have hardware/emulation
> on which you can test this, you may want to test your patches with
> DEBUG_PREEMPT enabled.

Yeah, it really should. Thanks for spotting.

> 
> > +       if (!cache) {
> > +               cache = kzalloc(sizeof(struct sgx_lepubkeyhash), GFP_KERNEL);
> 
> But then here you do a GFP_KERNEL allocation, which can sleep.

Yes, of course this would need to be moved outside of the region where
pre-emption is disabled.

> Also: After "cache" has been allocated in this branch, when do you
> store the reference to it? As far as I can tell, you never write to
> sgx_lepubkeyhash_cache, and the allocation just leaks.

I have assignment in my local tree but for some reason it was not
squashed to this commit :-/

> 
> > +               if (!cache)
> > +                       return -ENOMEM;
> > +       }
> > +
> > +       cache_valid = cache->pm_cnt == sgx_pm_cnt;
> 
> The cache should probably not be treated as valid if it has just been
> created and only contains zeroes, right?

The name of the local variable is probably a bit misleading but also
cached values are compared in the loop.

> 
> > +       cache->pm_cnt = sgx_pm_cnt;
> 
> Can sgx_pm_cnt be modified concurrently? If so, please use at least
> READ_ONCE() to document that and prevent the compiler from doing weird
> stuff.

No it cannot.

> 
> > +       preempt_disable();
> 
> And here you turn off preemption, but it should already have been off?

Yes.

I think Sean's suggestion to update cache on SGX_INVALID_TOKEN is way to
go in this and instead of fixing this I'll change the code to use that
as a measure to update the cache.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 06/13] x86/sgx: Detect Intel SGX
  2018-09-03 14:26   ` Andy Shevchenko
@ 2018-09-04  9:56     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-04  9:56 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, suresh.b.siddha, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, serge.ayoun, Rafael J. Wysocki,
	Borislav Petkov, Reinette Chatre, Andi Kleen, Greg Kroah-Hartman,
	Kirill A. Shutemov, Linux Kernel Mailing List

On Mon, Sep 03, 2018 at 05:26:43PM +0300, Andy Shevchenko wrote:
> On Mon, Aug 27, 2018 at 9:57 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> >
> > From: Sean Christopherson <sean.j.christopherson@intel.com>
> >
> > Intel(R) SGX is a set of CPU instructions that can be used by applications
> > to set aside private regions of code and data. The code outside the enclave
> > is disallowed to access the memory inside the enclave by the CPU access
> > control.
> >
> > Add a check for SGX to arch/x86 and a new config option, INTEL_SGX_CORE.
> > Expose a boolean variable 'sgx_enabled' to query whether or not the SGX
> > support is available.
> 
> > +       prompt "Intel SGX core functionality"
> > +       def_bool n
> 
> Default 'default' is 'n'. Perhaps changing prompt to bool will make it
> one line less.

Sure!

> > +#include <asm/sgx.h>
> > +#include <asm/sgx_pr.h>
> 
> Don't we put linux/* followed by asm/* ?

Yes.

> 
> > +#include <linux/freezer.h>
> > +#include <linux/highmem.h>
> > +#include <linux/kthread.h>
> > +#include <linux/ratelimit.h>
> > +#include <linux/sched/signal.h>
> > +#include <linux/slab.h>
> 
> -- 
> With Best Regards,
> Andy Shevchenko

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-09-03 14:41   ` Andy Shevchenko
@ 2018-09-04  9:59     ` Jarkko Sakkinen
  2018-09-04 17:49     ` Sean Christopherson
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-04  9:59 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, suresh.b.siddha, Linux Kernel Mailing List

On Mon, Sep 03, 2018 at 05:41:53PM +0300, Andy Shevchenko wrote:
> On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> >
> > Add data structures to track Enclave Page Cache (EPC) pages.  EPC is
> > divided into multiple banks (1-N) of which addresses and sizes can be
> > enumerated with CPUID by the OS.
> >
> > On NUMA systems a node can have at most bank. A bank can be at most part of
> > two nodes. SGX supports both nodes with a single memory controller and also
> > sub-cluster nodes with severals memory controllers on a single die.
> 
> > -#include <asm/sgx.h>
> > -#include <asm/sgx_pr.h>
> >  #include <linux/freezer.h>
> >  #include <linux/highmem.h>
> >  #include <linux/kthread.h>
> > +#include <linux/pagemap.h>
> >  #include <linux/ratelimit.h>
> >  #include <linux/sched/signal.h>
> > +#include <linux/shmem_fs.h>
> >  #include <linux/slab.h>
> > +#include <asm/sgx.h>
> > +#include <asm/sgx_pr.h>
> 
> Squash issues?

Yes :-/

> > +       va = ioremap_cache(addr, size);
> > +       if (!va)
> > +               return -ENOMEM;
> 
> I'm not sure this is a right API. Do we operate with memory? Does it
> have I/O side effects?
> If no, memremap() would be better to use.

Had this idea a long time ago but had forgotten it. EPC is from caching
perspective like regular memory.

> -- 
> With Best Regards,
> Andy Shevchenko
> 

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 08/13] x86/sgx: Add wrappers for ENCLS leaf functions
  2018-09-03 15:01   ` Andy Shevchenko
@ 2018-09-04 11:09     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-04 11:09 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, serge.ayoun, suresh.b.siddha,
	Linux Kernel Mailing List

On Mon, Sep 03, 2018 at 06:01:26PM +0300, Andy Shevchenko wrote:
> On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> >
> > Add wrappers for Intel(R) SGX ENCLS opcode leaf functions except
> > ENCLS(EINIT). ENCLS invokes privileged functions for managing (creation,
> > initialization and swapping) and debugging enclaves.
> 
> > +#define ENCLS_FAULT_FLAG 0x40000000UL
> > +#define ENCLS_FAULT_FLAG_ASM "$0x40000000"
> 
> Hmm... Why it can't have same name?
> 
> See, how _AC() macro is defined and being used.

Thanks, we'll migrate this to use _AC().

> > +#define ENCLS_TRAPNR(r) ((r) & ~ENCLS_FAULT_FLAG)
> 
> If result of macro is assigned to some variable and (r) by some reason
> is 32-bit type
> and you compile as 64-bit object, compiler will warn here.
> Please, check this is not the case in any of use of this macro.
> Otherwise you need a type casting, like
> 
> foo = bar & (u32)~BAR;
> 
> (or using typeof() might work)

Thanks for spotting this. I will check the use of this macro.

> 
> -- 
> With Best Regards,
> Andy Shevchenko

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-09-03 23:45               ` Huang, Kai
@ 2018-09-04 14:54                 ` Sean Christopherson
  2018-09-04 15:30                   ` Jarkko Sakkinen
  2018-09-04 15:26                 ` Jarkko Sakkinen
  1 sibling, 1 reply; 103+ messages in thread
From: Sean Christopherson @ 2018-09-04 14:54 UTC (permalink / raw)
  To: Huang, Kai
  Cc: Jarkko Sakkinen, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

On Mon, Sep 03, 2018 at 04:45:14PM -0700, Huang, Kai wrote:
> > -----Original Message-----
> > From: linux-sgx-owner@vger.kernel.org [mailto:linux-sgx-
> > owner@vger.kernel.org] On Behalf Of Jarkko Sakkinen
> > Sent: Tuesday, September 4, 2018 7:19 AM
> > To: Christopherson, Sean J <sean.j.christopherson@intel.com>
> > Cc: Huang, Kai <kai.huang@intel.com>; platform-driver-x86@vger.kernel.org;
> > x86@kernel.org; nhorman@redhat.com; linux-kernel@vger.kernel.org;
> > tglx@linutronix.de; suresh.b.siddha@intel.com; Ayoun, Serge
> > <serge.ayoun@intel.com>; hpa@zytor.com; npmccallum@redhat.com;
> > mingo@redhat.com; linux-sgx@vger.kernel.org; Hansen, Dave
> > <dave.hansen@intel.com>
> > Subject: Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
> > 
> > On Fri, Aug 31, 2018 at 11:15:09AM -0700, Sean Christopherson wrote:
> > > On Fri, Aug 31, 2018 at 03:17:03PM +0300, Jarkko Sakkinen wrote:
> > > > On Wed, Aug 29, 2018 at 07:33:54AM +0000, Huang, Kai wrote:
> > > > > [snip..]
> > > > >
> > > > > > > >
> > > > > > > > @@ -38,6 +39,18 @@ static LIST_HEAD(sgx_active_page_list);
> > > > > > > > static DEFINE_SPINLOCK(sgx_active_page_list_lock);
> > > > > > > >  static struct task_struct *ksgxswapd_tsk;  static
> > > > > > > > DECLARE_WAIT_QUEUE_HEAD(ksgxswapd_waitq);
> > > > > > > > +static struct notifier_block sgx_pm_notifier; static u64
> > > > > > > > +sgx_pm_cnt;
> > > > > > > > +
> > > > > > > > +/* The cache for the last known values of
> > > > > > > > +IA32_SGXLEPUBKEYHASHx MSRs
> > > > > > > > for each
> > > > > > > > + * CPU. The entries are initialized when they are first
> > > > > > > > + used by
> > > > > > > > sgx_einit().
> > > > > > > > + */
> > > > > > > > +struct sgx_lepubkeyhash {
> > > > > > > > +	u64 msrs[4];
> > > > > > > > +	u64 pm_cnt;
> > > > > > >
> > > > > > > May I ask why do we need pm_cnt here? In fact why do we need
> > > > > > > suspend staff (namely, sgx_pm_cnt above, and related code in
> > > > > > > this patch) here in this patch? From the patch commit message
> > > > > > > I don't see why we need PM staff here. Please give comment why
> > > > > > > you need PM staff, or you may consider to split the PM staff to another
> > patch.
> > > > > >
> > > > > > Refining the commit message probably makes more sense because
> > > > > > without PM code sgx_einit() would be broken. The MSRs have been reset
> > after waking up.
> > > > > >
> > > > > > Some kind of counter is required to keep track of the power
> > > > > > cycle. When going to sleep the sgx_pm_cnt is increased.
> > > > > > sgx_einit() compares the current value of the global count to
> > > > > > the value in the cache entry to see whether we are in a new power cycle.
> > > > >
> > > > > You mean reset to Intel default? I think we can also just reset
> > > > > the cached MSR values on each power cycle, which would be simpler,
> > IMHO?
> > > >
> > > > I don't really see that much difference in the complexity.
> > >
> > > Tracking the validity of the cache means we're hosed if we miss any
> > > condition that causes the MSRs to be reset.  I think we're better off
> > > assuming the cache can be stale at any time, i.e. don't track power
> > > cyles and instead handle EINIT failure due to INVALID_TOKEN by writing
> > > the cache+MSRs with the desired hash and retrying EINIT.  EINIT is
> > > interruptible and its latency is extremely variable in any case, e.g.
> > > tens of thousands of cycles, so this rarely-hit "slow path" probably
> > > wouldn't affect the worst case latency of EINIT.
> > 
> > Sounds a good refiniment. Pretty good solution to heal from host sleep on the
> > guest VM and then there is no need for driver changes.
> 
> To me either way should be OK, keeping MSR cache or retrying EINIT, since EINIT should not be in performance critical path I think.
> 
> But INVALID_TOKEN is not only returned when MSRs are mismatched, so do you plan to check to rule out other cases that cause INVALID_TOKEN before retrying EINIT, or unconditionally  retry EINIT? And we should only retry once?

I don't see any value in trying to rule out specific causes of
INVALID_TOKEN, but we should only retry EINIT if ret==INVALID_TOKEN
and RDMSR(HASH0) != sgx_lepubkeyhash[0].  Only the first MSR needs to
be checked for validity as they're a package deal, i.e. they'll all be
valid or all be reset.  There shouldn't be a limit on retry attempts,
e.g. the MSRs could theoretically be reset between WRMSR and EINIT.

> 
> Thanks,
> -Kai
> > 
> > /Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-09-03 23:45               ` Huang, Kai
  2018-09-04 14:54                 ` Sean Christopherson
@ 2018-09-04 15:26                 ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-04 15:26 UTC (permalink / raw)
  To: Huang, Kai
  Cc: Christopherson, Sean J, platform-driver-x86, x86, nhorman,
	linux-kernel, tglx, suresh.b.siddha, Ayoun, Serge, hpa,
	npmccallum, mingo, linux-sgx, Hansen, Dave

On Mon, Sep 03, 2018 at 11:45:14PM +0000, Huang, Kai wrote:
> But INVALID_TOKEN is not only returned when MSRs are mismatched, so do
> you plan to check to rule out other cases that cause INVALID_TOKEN
> before retrying EINIT, or unconditionally  retry EINIT? And we should
> only retry once?

In the case of this error we will do wrmsrs and retry einit once.
This is how I understood it at least.

Q: Do we have to care about VMM sleep anyway? I mean if VMM always traps
EINIT it can write the MSRs with guest values if it has been sleeping.

If the answer is no, then retrying once should be a complete solution
and we don't need pm_cnt.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-09-04 14:54                 ` Sean Christopherson
@ 2018-09-04 15:30                   ` Jarkko Sakkinen
  2018-09-04 16:35                     ` Sean Christopherson
  0 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-04 15:30 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Huang, Kai, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

On Tue, Sep 04, 2018 at 07:54:51AM -0700, Sean Christopherson wrote:
> I don't see any value in trying to rule out specific causes of
> INVALID_TOKEN, but we should only retry EINIT if ret==INVALID_TOKEN
> and RDMSR(HASH0) != sgx_lepubkeyhash[0].  Only the first MSR needs to
> be checked for validity as they're a package deal, i.e. they'll all be
> valid or all be reset.  There shouldn't be a limit on retry attempts,
> e.g. the MSRs could theoretically be reset between WRMSR and EINIT.

Why is doing rdmsrs necessary? With the INVALID_TOKEN error we know we
are out-of-sync i.e. have been sleeping and then one just needs to do
wrmsrs.

I think one retry should be enough given that VMM traps EINIT. One retry
is needed to take care of the guest itself (or host if we are running on
bare metal) having been in a sleep state.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-09-03 19:02   ` Andy Shevchenko
@ 2018-09-04 15:38     ` Jarkko Sakkinen
  2018-09-04 15:45       ` Sean Christopherson
  0 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-04 15:38 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, suresh.b.siddha, serge.ayoun,
	Linux Kernel Mailing List

On Mon, Sep 03, 2018 at 10:02:16PM +0300, Andy Shevchenko wrote:
> On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> >
> > Add a Enclave Page Cache (EPC) memory manager that can be used to
> > allocate and free EPC pages. The swapper thread ksgxswapd reclaims pages
> > on the event when the number of free EPC pages goes below
> > %SGX_NR_LOW_PAGES up until it reaches %SGX_NR_HIGH_PAGES.
> >
> > Pages are reclaimed in LRU fashion from a global list. The consumers
> > take care of calling EBLOCK (block page from new accesses), ETRACK
> > (restart counting the entering hardware threads) and EWB (write page to
> > the regular memory) because executing these operations usually (if not
> > always) requires to do some subsystem-internal locking operations.
> 
> > +                       list_del(&page->list);
> 
> Is this page will be completely gone? Otherwise it might be needed to
> reinit list head here as well.

The swapper cannot access the page once it has been removed from the
list of active pages so it does not matter whether this is list_del()
or list_del_init().

> > +       WARN(ret < 0, "sgx: cannot free page, reclaim in-progress");
> > +       WARN(ret > 0, "sgx: EREMOVE returned %d (0x%x)", ret, ret);
> 
> I'm not sure (though it's easy to check) that you need sgx: prefix
> here. WARN() might take pr_fmt() if defined.

Sean, you took care of this one. Was it so that WARN() does not respect
pr_fmt?

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-09-04 15:38     ` Jarkko Sakkinen
@ 2018-09-04 15:45       ` Sean Christopherson
  0 siblings, 0 replies; 103+ messages in thread
From: Sean Christopherson @ 2018-09-04 15:45 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: Andy Shevchenko, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, nhorman, npmccallum, linux-sgx,
	Thomas Gleixner, Ingo Molnar, H. Peter Anvin, suresh.b.siddha,
	serge.ayoun, Linux Kernel Mailing List

On Tue, Sep 04, 2018 at 06:38:03PM +0300, Jarkko Sakkinen wrote:
> On Mon, Sep 03, 2018 at 10:02:16PM +0300, Andy Shevchenko wrote:
> > On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
> > <jarkko.sakkinen@linux.intel.com> wrote:
> > >
> > > +       WARN(ret < 0, "sgx: cannot free page, reclaim in-progress");
> > > +       WARN(ret > 0, "sgx: EREMOVE returned %d (0x%x)", ret, ret);
> > 
> > I'm not sure (though it's easy to check) that you need sgx: prefix
> > here. WARN() might take pr_fmt() if defined.
> 
> Sean, you took care of this one. Was it so that WARN() does not respect
> pr_fmt?

Yep, WARN() doesn't respect pr_fmt.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 04/13] x86/sgx: Architectural structures
  2018-09-03 13:16   ` Andy Shevchenko
  2018-09-03 19:17     ` Jarkko Sakkinen
@ 2018-09-04 16:04     ` Dave Hansen
  2018-09-04 16:06       ` Andy Shevchenko
  2018-09-05 17:32       ` Jarkko Sakkinen
  1 sibling, 2 replies; 103+ messages in thread
From: Dave Hansen @ 2018-09-04 16:04 UTC (permalink / raw)
  To: Andy Shevchenko, Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Linux Kernel Mailing List

On 09/03/2018 06:16 AM, Andy Shevchenko wrote:
>> +       EBLOCK  = 0x9,
>> +       EPA     = 0xA,
>> +       EWB     = 0xB,
>> +       ETRACK  = 0xC,
>> +       EAUG    = 0xD,
>> +       EMODPR  = 0xE,
>> +       EMODT   = 0xF,
>> +};
> Hmm... This E prefix confuses me with (system wide) error codes. Has
> it been discussed before? If so, can you point on the conclusion why
> the current format is good?

Making them SGX_EWHATEVER isn't a horrible idea.



^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-08-27 18:53 ` [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves Jarkko Sakkinen
  2018-08-27 21:41   ` Huang, Kai
  2018-09-03 13:53   ` Jann Horn
@ 2018-09-04 16:05   ` Andy Shevchenko
  2 siblings, 0 replies; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-04 16:05 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, Thomas Gleixner, Ingo Molnar,
	H. Peter Anvin, suresh.b.siddha, serge.ayoun,
	Linux Kernel Mailing List

On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
>
> From: Sean Christopherson <sean.j.christopherson@intel.com>
>
> Add a function to perform ENCLS(EINIT), which initializes an enclave,
> which can be used by a driver for running enclaves and VMMs.
>
> Writing the LE hash MSRs is extraordinarily expensive, e.g. 3-4x slower
> than normal MSRs, so we use a per-cpu cache to track the last known value
> of the MSRs to avoid unnecessarily writing the MSRs with the current value.
>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>

> +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken *token,
> +             struct sgx_epc_page *secs_page, u64 lepubkeyhash[4]);

This [4] doesn't make any sense in a C when used in function call
parameter list.

> +/* The cache for the last known values of IA32_SGXLEPUBKEYHASHx MSRs for each
> + * CPU. The entries are initialized when they are first used by sgx_einit().
> + */
> +struct sgx_lepubkeyhash {
> +       u64 msrs[4];

4 is MAGIC.

> +       u64 pm_cnt;
> +};

> +int sgx_einit(struct sgx_sigstruct *sigstruct, struct sgx_einittoken *token,
> +             struct sgx_epc_page *secs_page, u64 lepubkeyhash[4])

Same two comments about [4].

> +{

> +       cache = per_cpu(sgx_lepubkeyhash_cache, smp_processor_id());

> +       if (!cache) {

How often it's being expected to happen?

> +               cache = kzalloc(sizeof(struct sgx_lepubkeyhash), GFP_KERNEL);
> +               if (!cache)
> +                       return -ENOMEM;
> +       }

> +       for (i = 0; i < 4; i++) {

Same MAGIC?

> +       }

> +}

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 04/13] x86/sgx: Architectural structures
  2018-09-04 16:04     ` Dave Hansen
@ 2018-09-04 16:06       ` Andy Shevchenko
  2018-09-05 17:32       ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-04 16:06 UTC (permalink / raw)
  To: Dave Hansen
  Cc: Jarkko Sakkinen, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Linux Kernel Mailing List

On Tue, Sep 4, 2018 at 7:04 PM Dave Hansen <dave.hansen@intel.com> wrote:
>
> On 09/03/2018 06:16 AM, Andy Shevchenko wrote:
> >> +       EBLOCK  = 0x9,
> >> +       EPA     = 0xA,
> >> +       EWB     = 0xB,
> >> +       ETRACK  = 0xC,
> >> +       EAUG    = 0xD,
> >> +       EMODPR  = 0xE,
> >> +       EMODT   = 0xF,
> >> +};
> > Hmm... This E prefix confuses me with (system wide) error codes. Has
> > it been discussed before? If so, can you point on the conclusion why
> > the current format is good?
>
> Making them SGX_EWHATEVER isn't a horrible idea.

+1 here. Namespace will not shadow SDM naming scheme.

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-09-04 15:30                   ` Jarkko Sakkinen
@ 2018-09-04 16:35                     ` Sean Christopherson
  2018-09-04 22:13                       ` Huang, Kai
  2018-09-05 17:39                       ` Jarkko Sakkinen
  0 siblings, 2 replies; 103+ messages in thread
From: Sean Christopherson @ 2018-09-04 16:35 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: Huang, Kai, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

On Tue, Sep 04, 2018 at 06:30:21PM +0300, Jarkko Sakkinen wrote:
> On Tue, Sep 04, 2018 at 07:54:51AM -0700, Sean Christopherson wrote:
> > I don't see any value in trying to rule out specific causes of
> > INVALID_TOKEN, but we should only retry EINIT if ret==INVALID_TOKEN
> > and RDMSR(HASH0) != sgx_lepubkeyhash[0].  Only the first MSR needs to
> > be checked for validity as they're a package deal, i.e. they'll all be
> > valid or all be reset.  There shouldn't be a limit on retry attempts,
> > e.g. the MSRs could theoretically be reset between WRMSR and EINIT.
> 
> Why is doing rdmsrs necessary? With the INVALID_TOKEN error we know we
> are out-of-sync i.e. have been sleeping and then one just needs to do
> wrmsrs.

As Kai mentioned, INVALID_TOKEN is returned for other reasons, e.g. a
production enclave trying to use a debug token or reserved bits set in
the token.  And in the KVM case, the hash and token are provided by
the guest, so it's entirely possible the enclave/token is not signed
with the key specified in the hash.  RDMSR is relatively inexpensive
compared to the overall cost of EINIT.  Though of course EINIT failure
isn't exactly a fast path, so I'm ok if you want to opt for simplicity
and retry on INVALID_TOKEN without checking the MSRs, just make sure
to add a comment indicating we're intentionally not checking the MSRs.
 
> I think one retry should be enough given that VMM traps EINIT. One retry
> is needed to take care of the guest itself (or host if we are running on
> bare metal) having been in a sleep state.

Assuming we do RDMSR(hash0), that should be sufficient to prevent
infinite retry and it protects against the MSRs being lost between
WRMSR and EINIT during retry.  That being said, I'm ok retrying only
once, especially if you want to omit the RDMSR.  Disabling preemption
should prevent the kernel from suspending between WRMSR and EINIT,
I'm just being paranoid.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-09-03 14:41   ` Andy Shevchenko
  2018-09-04  9:59     ` Jarkko Sakkinen
@ 2018-09-04 17:49     ` Sean Christopherson
  2018-09-04 18:01       ` Andy Shevchenko
  1 sibling, 1 reply; 103+ messages in thread
From: Sean Christopherson @ 2018-09-04 17:49 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: Jarkko Sakkinen, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, nhorman, npmccallum, linux-sgx,
	serge.ayoun, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	suresh.b.siddha, Linux Kernel Mailing List

On Mon, Sep 03, 2018 at 05:41:53PM +0300, Andy Shevchenko wrote:
> On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> 
> > +       va = ioremap_cache(addr, size);
> > +       if (!va)
> > +               return -ENOMEM;
> 
> I'm not sure this is a right API. Do we operate with memory? Does it
> have I/O side effects?
> If no, memremap() would be better to use.

Preserving __iomem is desirable.  There aren't side effects per se,
but direct non-enclave accesses to the EPC get abort page semantics so
the kernel shouldn't be directly dereferencing a pointer to the EPC.
Though by that argument, sgx_epc_bank.va, sgx_epc_addr's return and
all ENCLS helpers should be tagged __iomem.

For documentation purposes, maybe it would be better to use __private
or "#define __sgx_epc __iomem" and use that?

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-08-27 18:53 ` [PATCH v13 11/13] platform/x86: Intel SGX driver Jarkko Sakkinen
@ 2018-09-04 17:59   ` Andy Shevchenko
  2018-09-05 17:33     ` Jarkko Sakkinen
  0 siblings, 1 reply; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-04 17:59 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, shay.katz-zamir,
	suresh.b.siddha, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, ebiggers,
	Linux Kernel Mailing List

On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
>
> Intel Software Guard eXtensions (SGX) is a set of CPU instructions that
> can be used by applications to set aside private regions of code and
> data. The code outside the enclave is disallowed to access the memory
> inside the enclave by the CPU access control.
>
> SGX driver provides a ioctl API for loading and initializing enclaves.
> Address range for enclaves is reserved with mmap() and they are
> destroyed with munmap(). Enclave construction, measurement and
> initialization is done with the provided the ioctl API.

> +/*
> + * This file is provided under a dual BSD/GPLv2 license.  When using or
> + * redistributing this file, you may do so under either license.
> + *
> + * GPL LICENSE SUMMARY
> + *
> + * Copyright(c) 2016-2017 Intel Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of version 2 of the GNU General Public License as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * General Public License for more details.
> + *
> + * Contact Information:
> + * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> + * Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
> + *
> + * BSD LICENSE
> + *
> + * Copyright(c) 2016-2017 Intel Corporation.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + *
> + *   * Redistributions of source code must retain the above copyright
> + *     notice, this list of conditions and the following disclaimer.
> + *   * Redistributions in binary form must reproduce the above copyright
> + *     notice, this list of conditions and the following disclaimer in
> + *     the documentation and/or other materials provided with the
> + *     distribution.
> + *   * Neither the name of Intel Corporation nor the names of its
> + *     contributors may be used to endorse or promote products derived
> + *     from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + *

Can't we just put one line with SPDX identifier?

> + * Authors:

> + *

Redundant line.

> + * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> + * Suresh Siddha <suresh.b.siddha@intel.com>
> + */

> +/**

> + * struct sgx_enclave_add_page - parameter structure for the
> + *                               %SGX_IOC_ENCLAVE_ADD_PAGE ioctl

I don't think multi-line would work nice for short description line.

> + * @addr:      address within the ELRANGE
> + * @src:       address for the page data
> + * @secinfo:   address for the SECINFO data
> + * @mrmask:    bitmask for the measured 256 byte chunks
> + */

> +config INTEL_SGX
> +       tristate "Intel(R) SGX Driver"

Spell SGX fully here.

> +       default n

Drop this.

> +++ b/drivers/platform/x86/intel_sgx/Makefile
> @@ -0,0 +1,13 @@
> +#
> +# Intel SGX
> +#

No SPDX?  (Same, btw, for Kconfig)

> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)

Should be /* */ in headers AFAIR.

Btw, shouldn't be this file rather under include/linux/platform_data/x86/ ?

> +#define sgx_pr_ratelimited(level, encl, fmt, ...)                      \
> +       pr_ ## level ## _ratelimited("[%d:0x%p] " fmt,                  \
> +                                    pid_nr((encl)->tgid),              \
> +                                    (void *)(encl)->base, ##__VA_ARGS__)
> +#define sgx_dbg(encl, fmt, ...) \
> +       sgx_pr_ratelimited(debug, encl, fmt, ##__VA_ARGS__)
> +#define sgx_info(encl, fmt, ...) \
> +       sgx_pr_ratelimited(info, encl, fmt, ##__VA_ARGS__)
> +#define sgx_warn(encl, fmt, ...) \
> +       sgx_pr_ratelimited(warn, encl, fmt, ##__VA_ARGS__)
> +#define sgx_err(encl, fmt, ...) \
> +       sgx_pr_ratelimited(err, encl, fmt, ##__VA_ARGS__)
> +#define sgx_crit(encl, fmt, ...) \
> +       sgx_pr_ratelimited(crit, encl, fmt, ##__VA_ARGS__)

Rate limited versions do not guarantee all info to be printed (as far
as I heard).
If you are going to use them everywhere it would be nice to see that
RL versions are in use.
So, please, add suffix _rl at least to your helper macros.

> +#define SGX_ENCL_PAGE_PCMD_OFFSET(encl_page, encl)             \
> +({                                                             \
> +       unsigned long ret;                                      \
> +       ret = SGX_ENCL_PAGE_BACKING_INDEX(encl_page, encl);     \

> +       ((ret & 31) * 128);                                     \

What these magic numbers are about?

> +})

> +#define SGX_INVD(ret, encl, fmt, ...)          \
> +do {                                           \
> +       if (WARN(ret, "sgx: " fmt, ##__VA_ARGS__))      \
> +               sgx_invalidate(encl, true);     \
> +} while (0)

Perhaps INVD -> INV as I can see as a pattern in kernel.

> +#include <asm/mman.h>

linux/* first

> +#include <linux/delay.h>
> +#include <linux/file.h>
> +#include <linux/hashtable.h>
> +#include <linux/highmem.h>
> +#include <linux/ratelimit.h>
> +#include <linux/sched/signal.h>
> +#include <linux/shmem_fs.h>
> +#include <linux/slab.h>
> +#include <linux/suspend.h>

> +                       if ((entry->desc & SGX_ENCL_PAGE_LOADED) &&
> +                           (entry->desc & SGX_ENCL_PAGE_TCS) &&
> +                           !sgx_encl_find(encl->mm, addr, &vma))

> +               if ((entry->desc & SGX_ENCL_PAGE_LOADED) &&
> +                   !(entry->desc & SGX_ENCL_PAGE_RECLAIMED)) {
> +                       if (!__sgx_free_page(entry->epc_page))
> +                               entry->desc &= ~SGX_ENCL_PAGE_LOADED;

> +static int sgx_measure(struct sgx_epc_page *secs_page,
> +                      struct sgx_epc_page *epc_page,
> +                      u16 mrmask)
> +{

> +       int ret = 0;

I would rather expect this to be closer to where it's used.

> +       void *secs;
> +       void *epc;
> +       int i;
> +       int j;
> +
> +       if (!mrmask)
> +               return ret;

return 0; ?

> +
> +       secs = sgx_epc_addr(secs_page);
> +       epc = sgx_epc_addr(epc_page);
> +

... ret = 0;

Actually, it's not needed, since you are always call __eextend() at
least once (see above check for !mrmask).

> +       for (i = 0, j = 1; i < 0x1000 && !ret; i += 0x100, j <<= 1) {
> +               if (!(j & mrmask))
> +                       continue;
> +
> +               ret = __eextend(secs, (void *)((unsigned long)epc + i));
> +       }

Can we rewrite this like

unsigned long tmp = mrmask;

for_each_set_bit(j, ...) {
 ret = ...(... + j * 0x100));
 if (ret)
  break;
}

?

> +       struct sgx_encl *encl;

> +       encl = container_of(work, struct sgx_encl, add_page_work);

Could this assignment be directly in definition block?

> +       } while (!kref_put(&encl->refcount, sgx_encl_release) && !is_empty);

isn't it the same as  !(... || ...) ?

> +}

> +static u32 sgx_calc_ssaframesize(u32 miscselect, u64 xfrm)
> +{
> +       u32 size_max = PAGE_SIZE;
> +       u32 size;
> +       int i;
> +

> +       for (i = 2; i < 64; i++) {
> +               if (!((1 << i) & xfrm))
> +                       continue;

DECLARE_BITMAP(tmp, 64);

tmp = bitmap_from_u64(tmp, xfrm & ~3);
for_each_set_bit(i, tmp) {
 ...
}

> +
> +               size = SGX_SSA_GPRS_SIZE + sgx_xsave_size_tbl[i];
> +               if (miscselect & SGX_MISC_EXINFO)
> +                       size += SGX_SSA_MISC_EXINFO_SIZE;

> +               if (size > size_max)
> +                       size_max = size;

size_max = max(size_max, size);

> +       }
> +

> +       return (size_max + PAGE_SIZE - 1) >> PAGE_SHIFT;

snd_sgbuf_aligned_pages() is the same. Perhaps time to create a helper
here and in the future it can be moved to some generic one?

Ooops, it's actually PFN_UP().

> +}
> +
> +static int sgx_validate_secs(const struct sgx_secs *secs,
> +                            unsigned long ssaframesize)
> +{
> +       int i;
> +
> +       if (secs->size < (2 * PAGE_SIZE) ||

> +           (secs->size & (secs->size - 1)) != 0)

is_power_of_2()

> +               return -EINVAL;
> +
> +       if (secs->base & (secs->size - 1))
> +               return -EINVAL;
> +
> +       if (secs->attributes & SGX_ATTR_RESERVED_MASK ||
> +           secs->miscselect & sgx_misc_reserved)
> +               return -EINVAL;

> +       if ((secs->xfrm & 0x3) != 0x3 || (secs->xfrm & ~sgx_xfrm_mask))
> +               return -EINVAL;

Some magic is here

> +
> +       /* Check that BNDREGS and BNDCSR are equal. */

> +       if (((secs->xfrm >> 3) & 1) != ((secs->xfrm >> 4) & 1))

Perhaps

(!!(... & BIT(3)) ^ !!(... & BIT(4))) ?

...and actually define those magic bits?

> +               return -EINVAL;
> +
> +       if (!secs->ssa_frame_size || ssaframesize > secs->ssa_frame_size)
> +               return -EINVAL;
> +

> +       for (i = 0; i < SGX_SECS_RESERVED1_SIZE; i++)
> +               if (secs->reserved1[i])
> +                       return -EINVAL;
> +
> +       for (i = 0; i < SGX_SECS_RESERVED2_SIZE; i++)
> +               if (secs->reserved2[i])
> +                       return -EINVAL;
> +
> +       for (i = 0; i < SGX_SECS_RESERVED3_SIZE; i++)
> +               if (secs->reserved3[i])
> +                       return -EINVAL;
> +
> +       for (i = 0; i < SGX_SECS_RESERVED4_SIZE; i++)
> +               if (secs->reserved4[i])
> +                       return -EINVAL;

Can you use memchr_inv() in all above cases?

> +       return 0;
> +}
> +

> +       struct sgx_encl *encl =
> +               container_of(mn, struct sgx_encl, mmu_notifier);

One line?

> +       backing = shmem_file_setup("[dev/sgx]", secs->size + PAGE_SIZE,
> +                                  VM_NORESERVE);
> +       if (IS_ERR(backing))

> +               return (void *)backing;

ERR_CAST() please.

> +       pcmd = shmem_file_setup("[dev/sgx]", (secs->size + PAGE_SIZE) >> 5,
> +                               VM_NORESERVE);
> +       if (IS_ERR(pcmd)) {
> +               fput(backing);

> +               return (void *)pcmd;

Ditto.

> +       }

> +int sgx_encl_create(struct sgx_encl *encl, struct sgx_secs *secs)
> +{
> +       struct vm_area_struct *vma;
> +       struct sgx_pageinfo pginfo;
> +       struct sgx_secinfo secinfo;
> +       struct sgx_epc_page *secs_epc;
> +       long ret;
> +
> +       secs_epc = sgx_alloc_page(&encl->secs.impl, 0);
> +       if (IS_ERR(secs_epc)) {

> +               ret = PTR_ERR(secs_epc);
> +               return ret;

One line.

> +       }

> +       pginfo.addr = 0;
> +       pginfo.contents = (unsigned long)secs;
> +       pginfo.metadata = (unsigned long)&secinfo;
> +       pginfo.secs = 0;
> +       memset(&secinfo, 0, sizeof(secinfo));

+ blank line here.

> +       ret = __ecreate((void *)&pginfo, sgx_epc_addr(secs_epc));

> +

- blank line here.

> +       if (ret) {
> +               sgx_dbg(encl, "ECREATE returned %ld\n", ret);
> +               return ret;
> +       }

> +       down_read(&current->mm->mmap_sem);
> +       ret = sgx_encl_find(current->mm, secs->base, &vma);

> +       if (ret != -ENOENT) {

> +               if (!ret)
> +                       ret = -EINVAL;

> +               return ret;

return ret ? ret : -EINVAL;

> +       }

> +}

> +       for (i = 0; i < SGX_SECINFO_RESERVED_SIZE; i++)
> +               if (secinfo->reserved[i])
> +                       return -EINVAL;

memchr_inv() ?

> +       if (offset & (PAGE_SIZE - 1))
> +               return false;

~PAGE_MASK ?

> +       if ((tcs->fs_limit & 0xFFF) != 0xFFF)
> +               return -EINVAL;
> +
> +       if ((tcs->gs_limit & 0xFFF) != 0xFFF)
> +               return -EINVAL;

Are they ~PAGE_MASK as well? Please define properly.

> +       if (sgx_validate_secinfo(secinfo))
> +               return -EINVAL;

+ blank line

> +       if (page_type == SGX_SECINFO_TCS) {
> +               ret = sgx_validate_tcs(encl, data);
> +               if (ret)
> +                       return ret;
> +       }

+ blank line

> +       ret = sgx_encl_grow(encl);
> +       if (ret)
> +               return ret;

+ blank line

> +       mutex_lock(&encl->lock);
> +       if (encl->flags & (SGX_ENCL_INITIALIZED | SGX_ENCL_DEAD)) {
> +               mutex_unlock(&encl->lock);
> +               return -EINVAL;
> +       }

+ blank line

> +       encl_page = sgx_encl_alloc_page(encl, addr);
> +       if (IS_ERR(encl_page)) {
> +               mutex_unlock(&encl->lock);
> +               return PTR_ERR(encl_page);
> +       }

+ blank line

> +       ret = __sgx_encl_add_page(encl, encl_page, data, secinfo, mrmask);
> +       if (ret)
> +               sgx_encl_free_page(encl_page);

+ blank line

> +       mutex_unlock(&encl->lock);

> +       u64 mrsigner[4];

Magic 4.

> +       for (i = 0; i < SGX_EINIT_SLEEP_COUNT; i++) {
> +               for (j = 0; j < SGX_EINIT_SPIN_COUNT; j++) {
> +                       ret = sgx_einit(sigstruct, token, encl->secs.epc_page,
> +                                       mrsigner);

> +                       if (ret == SGX_UNMASKED_EVENT)
> +                               continue;

> +                       else
> +                               break;

Seems redundant

> +               }

> +       while (!list_empty(&encl->va_pages)) {
> +               va_page = list_first_entry(&encl->va_pages, struct sgx_va_page,
> +                                          list);

list_for_each_entry_safe() ?

> +               list_del(&va_page->list);
> +               sgx_free_page(va_page->epc_page);
> +               kfree(va_page);
> +       }

--
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-09-04 17:49     ` Sean Christopherson
@ 2018-09-04 18:01       ` Andy Shevchenko
  2018-09-04 18:17         ` Sean Christopherson
  0 siblings, 1 reply; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-04 18:01 UTC (permalink / raw)
  To: sean.j.christopherson
  Cc: Jarkko Sakkinen, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, nhorman, npmccallum, linux-sgx,
	serge.ayoun, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	suresh.b.siddha, Linux Kernel Mailing List

On Tue, Sep 4, 2018 a> +/**

> > > +       va = ioremap_cache(addr, size);
> > > +       if (!va)
> > > +               return -ENOMEM;
> >
> > I'm not sure this is a right API. Do we operate with memory? Does it
> > have I/O side effects?
> > If no, memremap() would be better to use.
>
> Preserving __iomem is desirable.  There aren't side effects per se,
> but direct non-enclave accesses to the EPC get abort page semantics so
> the kernel shouldn't be directly dereferencing a pointer to the EPC.
> Though by that argument, sgx_epc_bank.va, sgx_epc_addr's return and
> all ENCLS helpers should be tagged __iomem.

Why?
Does it related to *any* I/O?

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-09-04 18:01       ` Andy Shevchenko
@ 2018-09-04 18:17         ` Sean Christopherson
  2018-09-05 17:36           ` Jarkko Sakkinen
  0 siblings, 1 reply; 103+ messages in thread
From: Sean Christopherson @ 2018-09-04 18:17 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: Jarkko Sakkinen, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, nhorman, npmccallum, linux-sgx,
	serge.ayoun, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	suresh.b.siddha, Linux Kernel Mailing List

On Tue, Sep 04, 2018 at 09:01:15PM +0300, Andy Shevchenko wrote:
> On Tue, Sep 4, 2018 a> +/**
> 
> > > > +       va = ioremap_cache(addr, size);
> > > > +       if (!va)
> > > > +               return -ENOMEM;
> > >
> > > I'm not sure this is a right API. Do we operate with memory? Does it
> > > have I/O side effects?
> > > If no, memremap() would be better to use.
> >
> > Preserving __iomem is desirable.  There aren't side effects per se,
> > but direct non-enclave accesses to the EPC get abort page semantics so
> > the kernel shouldn't be directly dereferencing a pointer to the EPC.
> > Though by that argument, sgx_epc_bank.va, sgx_epc_addr's return and
> > all ENCLS helpers should be tagged __iomem.
> 
> Why?
> Does it related to *any* I/O?

No, hence my other comment that __private or a new tag altogether may
be more appropriate.  The noderef attribute is what we truly care
about.

^ permalink raw reply	[flat|nested] 103+ messages in thread

* RE: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-09-04 16:35                     ` Sean Christopherson
@ 2018-09-04 22:13                       ` Huang, Kai
  2018-09-05 17:39                       ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Huang, Kai @ 2018-09-04 22:13 UTC (permalink / raw)
  To: Christopherson, Sean J, Jarkko Sakkinen
  Cc: platform-driver-x86, x86, nhorman, linux-kernel, tglx,
	suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo, linux-sgx,
	Hansen, Dave


> -----Original Message-----
> From: platform-driver-x86-owner@vger.kernel.org [mailto:platform-driver-x86-
> owner@vger.kernel.org] On Behalf Of Sean Christopherson
> Sent: Wednesday, September 5, 2018 4:36 AM
> To: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> Cc: Huang, Kai <kai.huang@intel.com>; platform-driver-x86@vger.kernel.org;
> x86@kernel.org; nhorman@redhat.com; linux-kernel@vger.kernel.org;
> tglx@linutronix.de; suresh.b.siddha@intel.com; Ayoun, Serge
> <serge.ayoun@intel.com>; hpa@zytor.com; npmccallum@redhat.com;
> mingo@redhat.com; linux-sgx@vger.kernel.org; Hansen, Dave
> <dave.hansen@intel.com>
> Subject: Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
> 
> On Tue, Sep 04, 2018 at 06:30:21PM +0300, Jarkko Sakkinen wrote:
> > On Tue, Sep 04, 2018 at 07:54:51AM -0700, Sean Christopherson wrote:
> > > I don't see any value in trying to rule out specific causes of
> > > INVALID_TOKEN, but we should only retry EINIT if ret==INVALID_TOKEN
> > > and RDMSR(HASH0) != sgx_lepubkeyhash[0].  Only the first MSR needs
> > > to be checked for validity as they're a package deal, i.e. they'll
> > > all be valid or all be reset.  There shouldn't be a limit on retry
> > > attempts, e.g. the MSRs could theoretically be reset between WRMSR and
> EINIT.
> >
> > Why is doing rdmsrs necessary? With the INVALID_TOKEN error we know we
> > are out-of-sync i.e. have been sleeping and then one just needs to do
> > wrmsrs.
> 
> As Kai mentioned, INVALID_TOKEN is returned for other reasons, e.g. a
> production enclave trying to use a debug token or reserved bits set in the token.
> And in the KVM case, the hash and token are provided by the guest, so it's
> entirely possible the enclave/token is not signed with the key specified in the
> hash.  RDMSR is relatively inexpensive compared to the overall cost of EINIT.
> Though of course EINIT failure isn't exactly a fast path, so I'm ok if you want to
> opt for simplicity and retry on INVALID_TOKEN without checking the MSRs, just
> make sure to add a comment indicating we're intentionally not checking the
> MSRs.
> 
> > I think one retry should be enough given that VMM traps EINIT. One
> > retry is needed to take care of the guest itself (or host if we are
> > running on bare metal) having been in a sleep state.
> 
> Assuming we do RDMSR(hash0), that should be sufficient to prevent infinite retry
> and 

IMHO probably we need to review this assumption w/ crypto guys, at least Intel internally.

Thanks,
-Kai

it protects against the MSRs being lost between WRMSR and EINIT during
> retry.  That being said, I'm ok retrying only once, especially if you want to omit
> the RDMSR.  Disabling preemption should prevent the kernel from suspending
> between WRMSR and EINIT, I'm just being paranoid.



^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 04/13] x86/sgx: Architectural structures
  2018-09-04 16:04     ` Dave Hansen
  2018-09-04 16:06       ` Andy Shevchenko
@ 2018-09-05 17:32       ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-05 17:32 UTC (permalink / raw)
  To: Dave Hansen
  Cc: Andy Shevchenko, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, sean.j.christopherson, nhorman, npmccallum,
	linux-sgx, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Linux Kernel Mailing List

On Tue, Sep 04, 2018 at 09:04:44AM -0700, Dave Hansen wrote:
> On 09/03/2018 06:16 AM, Andy Shevchenko wrote:
> >> +       EBLOCK  = 0x9,
> >> +       EPA     = 0xA,
> >> +       EWB     = 0xB,
> >> +       ETRACK  = 0xC,
> >> +       EAUG    = 0xD,
> >> +       EMODPR  = 0xE,
> >> +       EMODT   = 0xF,
> >> +};
> > Hmm... This E prefix confuses me with (system wide) error codes. Has
> > it been discussed before? If so, can you point on the conclusion why
> > the current format is good?
> 
> Making them SGX_EWHATEVER isn't a horrible idea.

OK, going with that.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-09-04 17:59   ` Andy Shevchenko
@ 2018-09-05 17:33     ` Jarkko Sakkinen
  2018-09-05 17:36       ` Andy Shevchenko
  0 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-05 17:33 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, shay.katz-zamir,
	suresh.b.siddha, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, ebiggers,
	Linux Kernel Mailing List

On Tue, Sep 04, 2018 at 08:59:58PM +0300, Andy Shevchenko wrote:
> On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> >
> > Intel Software Guard eXtensions (SGX) is a set of CPU instructions that
> > can be used by applications to set aside private regions of code and
> > data. The code outside the enclave is disallowed to access the memory
> > inside the enclave by the CPU access control.
> >
> > SGX driver provides a ioctl API for loading and initializing enclaves.
> > Address range for enclaves is reserved with mmap() and they are
> > destroyed with munmap(). Enclave construction, measurement and
> > initialization is done with the provided the ioctl API.
> 
> > +/*
> > + * This file is provided under a dual BSD/GPLv2 license.  When using or
> > + * redistributing this file, you may do so under either license.
> > + *
> > + * GPL LICENSE SUMMARY
> > + *
> > + * Copyright(c) 2016-2017 Intel Corporation.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of version 2 of the GNU General Public License as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful, but
> > + * WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> > + * General Public License for more details.
> > + *
> > + * Contact Information:
> > + * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> > + * Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
> > + *
> > + * BSD LICENSE
> > + *
> > + * Copyright(c) 2016-2017 Intel Corporation.
> > + *
> > + * Redistribution and use in source and binary forms, with or without
> > + * modification, are permitted provided that the following conditions
> > + * are met:
> > + *
> > + *   * Redistributions of source code must retain the above copyright
> > + *     notice, this list of conditions and the following disclaimer.
> > + *   * Redistributions in binary form must reproduce the above copyright
> > + *     notice, this list of conditions and the following disclaimer in
> > + *     the documentation and/or other materials provided with the
> > + *     distribution.
> > + *   * Neither the name of Intel Corporation nor the names of its
> > + *     contributors may be used to endorse or promote products derived
> > + *     from this software without specific prior written permission.
> > + *
> > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> > + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> > + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> > + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > + *
> 
> Can't we just put one line with SPDX identifier?
> 
> > + * Authors:
> 
> > + *
> 
> Redundant line.
> 
> > + * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> > + * Suresh Siddha <suresh.b.siddha@intel.com>
> > + */
> 
> > +/**
> 
> > + * struct sgx_enclave_add_page - parameter structure for the
> > + *                               %SGX_IOC_ENCLAVE_ADD_PAGE ioctl
> 
> I don't think multi-line would work nice for short description line.
> 
> > + * @addr:      address within the ELRANGE
> > + * @src:       address for the page data
> > + * @secinfo:   address for the SECINFO data
> > + * @mrmask:    bitmask for the measured 256 byte chunks
> > + */
> 
> > +config INTEL_SGX
> > +       tristate "Intel(R) SGX Driver"
> 
> Spell SGX fully here.
> 
> > +       default n
> 
> Drop this.
> 
> > +++ b/drivers/platform/x86/intel_sgx/Makefile
> > @@ -0,0 +1,13 @@
> > +#
> > +# Intel SGX
> > +#
> 
> No SPDX?  (Same, btw, for Kconfig)
> 
> > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
> 
> Should be /* */ in headers AFAIR.
> 
> Btw, shouldn't be this file rather under include/linux/platform_data/x86/ ?
> 
> > +#define sgx_pr_ratelimited(level, encl, fmt, ...)                      \
> > +       pr_ ## level ## _ratelimited("[%d:0x%p] " fmt,                  \
> > +                                    pid_nr((encl)->tgid),              \
> > +                                    (void *)(encl)->base, ##__VA_ARGS__)
> > +#define sgx_dbg(encl, fmt, ...) \
> > +       sgx_pr_ratelimited(debug, encl, fmt, ##__VA_ARGS__)
> > +#define sgx_info(encl, fmt, ...) \
> > +       sgx_pr_ratelimited(info, encl, fmt, ##__VA_ARGS__)
> > +#define sgx_warn(encl, fmt, ...) \
> > +       sgx_pr_ratelimited(warn, encl, fmt, ##__VA_ARGS__)
> > +#define sgx_err(encl, fmt, ...) \
> > +       sgx_pr_ratelimited(err, encl, fmt, ##__VA_ARGS__)
> > +#define sgx_crit(encl, fmt, ...) \
> > +       sgx_pr_ratelimited(crit, encl, fmt, ##__VA_ARGS__)
> 
> Rate limited versions do not guarantee all info to be printed (as far
> as I heard).
> If you are going to use them everywhere it would be nice to see that
> RL versions are in use.
> So, please, add suffix _rl at least to your helper macros.
> 
> > +#define SGX_ENCL_PAGE_PCMD_OFFSET(encl_page, encl)             \
> > +({                                                             \
> > +       unsigned long ret;                                      \
> > +       ret = SGX_ENCL_PAGE_BACKING_INDEX(encl_page, encl);     \
> 
> > +       ((ret & 31) * 128);                                     \
> 
> What these magic numbers are about?
> 
> > +})
> 
> > +#define SGX_INVD(ret, encl, fmt, ...)          \
> > +do {                                           \
> > +       if (WARN(ret, "sgx: " fmt, ##__VA_ARGS__))      \
> > +               sgx_invalidate(encl, true);     \
> > +} while (0)
> 
> Perhaps INVD -> INV as I can see as a pattern in kernel.
> 
> > +#include <asm/mman.h>
> 
> linux/* first
> 
> > +#include <linux/delay.h>
> > +#include <linux/file.h>
> > +#include <linux/hashtable.h>
> > +#include <linux/highmem.h>
> > +#include <linux/ratelimit.h>
> > +#include <linux/sched/signal.h>
> > +#include <linux/shmem_fs.h>
> > +#include <linux/slab.h>
> > +#include <linux/suspend.h>
> 
> > +                       if ((entry->desc & SGX_ENCL_PAGE_LOADED) &&
> > +                           (entry->desc & SGX_ENCL_PAGE_TCS) &&
> > +                           !sgx_encl_find(encl->mm, addr, &vma))
> 
> > +               if ((entry->desc & SGX_ENCL_PAGE_LOADED) &&
> > +                   !(entry->desc & SGX_ENCL_PAGE_RECLAIMED)) {
> > +                       if (!__sgx_free_page(entry->epc_page))
> > +                               entry->desc &= ~SGX_ENCL_PAGE_LOADED;
> 
> > +static int sgx_measure(struct sgx_epc_page *secs_page,
> > +                      struct sgx_epc_page *epc_page,
> > +                      u16 mrmask)
> > +{
> 
> > +       int ret = 0;
> 
> I would rather expect this to be closer to where it's used.
> 
> > +       void *secs;
> > +       void *epc;
> > +       int i;
> > +       int j;
> > +
> > +       if (!mrmask)
> > +               return ret;
> 
> return 0; ?
> 
> > +
> > +       secs = sgx_epc_addr(secs_page);
> > +       epc = sgx_epc_addr(epc_page);
> > +
> 
> ... ret = 0;
> 
> Actually, it's not needed, since you are always call __eextend() at
> least once (see above check for !mrmask).
> 
> > +       for (i = 0, j = 1; i < 0x1000 && !ret; i += 0x100, j <<= 1) {
> > +               if (!(j & mrmask))
> > +                       continue;
> > +
> > +               ret = __eextend(secs, (void *)((unsigned long)epc + i));
> > +       }
> 
> Can we rewrite this like
> 
> unsigned long tmp = mrmask;
> 
> for_each_set_bit(j, ...) {
>  ret = ...(... + j * 0x100));
>  if (ret)
>   break;
> }
> 
> ?
> 
> > +       struct sgx_encl *encl;
> 
> > +       encl = container_of(work, struct sgx_encl, add_page_work);
> 
> Could this assignment be directly in definition block?
> 
> > +       } while (!kref_put(&encl->refcount, sgx_encl_release) && !is_empty);
> 
> isn't it the same as  !(... || ...) ?
> 
> > +}
> 
> > +static u32 sgx_calc_ssaframesize(u32 miscselect, u64 xfrm)
> > +{
> > +       u32 size_max = PAGE_SIZE;
> > +       u32 size;
> > +       int i;
> > +
> 
> > +       for (i = 2; i < 64; i++) {
> > +               if (!((1 << i) & xfrm))
> > +                       continue;
> 
> DECLARE_BITMAP(tmp, 64);
> 
> tmp = bitmap_from_u64(tmp, xfrm & ~3);
> for_each_set_bit(i, tmp) {
>  ...
> }
> 
> > +
> > +               size = SGX_SSA_GPRS_SIZE + sgx_xsave_size_tbl[i];
> > +               if (miscselect & SGX_MISC_EXINFO)
> > +                       size += SGX_SSA_MISC_EXINFO_SIZE;
> 
> > +               if (size > size_max)
> > +                       size_max = size;
> 
> size_max = max(size_max, size);
> 
> > +       }
> > +
> 
> > +       return (size_max + PAGE_SIZE - 1) >> PAGE_SHIFT;
> 
> snd_sgbuf_aligned_pages() is the same. Perhaps time to create a helper
> here and in the future it can be moved to some generic one?
> 
> Ooops, it's actually PFN_UP().
> 
> > +}
> > +
> > +static int sgx_validate_secs(const struct sgx_secs *secs,
> > +                            unsigned long ssaframesize)
> > +{
> > +       int i;
> > +
> > +       if (secs->size < (2 * PAGE_SIZE) ||
> 
> > +           (secs->size & (secs->size - 1)) != 0)
> 
> is_power_of_2()
> 
> > +               return -EINVAL;
> > +
> > +       if (secs->base & (secs->size - 1))
> > +               return -EINVAL;
> > +
> > +       if (secs->attributes & SGX_ATTR_RESERVED_MASK ||
> > +           secs->miscselect & sgx_misc_reserved)
> > +               return -EINVAL;
> 
> > +       if ((secs->xfrm & 0x3) != 0x3 || (secs->xfrm & ~sgx_xfrm_mask))
> > +               return -EINVAL;
> 
> Some magic is here
> 
> > +
> > +       /* Check that BNDREGS and BNDCSR are equal. */
> 
> > +       if (((secs->xfrm >> 3) & 1) != ((secs->xfrm >> 4) & 1))
> 
> Perhaps
> 
> (!!(... & BIT(3)) ^ !!(... & BIT(4))) ?
> 
> ...and actually define those magic bits?
> 
> > +               return -EINVAL;
> > +
> > +       if (!secs->ssa_frame_size || ssaframesize > secs->ssa_frame_size)
> > +               return -EINVAL;
> > +
> 
> > +       for (i = 0; i < SGX_SECS_RESERVED1_SIZE; i++)
> > +               if (secs->reserved1[i])
> > +                       return -EINVAL;
> > +
> > +       for (i = 0; i < SGX_SECS_RESERVED2_SIZE; i++)
> > +               if (secs->reserved2[i])
> > +                       return -EINVAL;
> > +
> > +       for (i = 0; i < SGX_SECS_RESERVED3_SIZE; i++)
> > +               if (secs->reserved3[i])
> > +                       return -EINVAL;
> > +
> > +       for (i = 0; i < SGX_SECS_RESERVED4_SIZE; i++)
> > +               if (secs->reserved4[i])
> > +                       return -EINVAL;
> 
> Can you use memchr_inv() in all above cases?
> 
> > +       return 0;
> > +}
> > +
> 
> > +       struct sgx_encl *encl =
> > +               container_of(mn, struct sgx_encl, mmu_notifier);
> 
> One line?
> 
> > +       backing = shmem_file_setup("[dev/sgx]", secs->size + PAGE_SIZE,
> > +                                  VM_NORESERVE);
> > +       if (IS_ERR(backing))
> 
> > +               return (void *)backing;
> 
> ERR_CAST() please.
> 
> > +       pcmd = shmem_file_setup("[dev/sgx]", (secs->size + PAGE_SIZE) >> 5,
> > +                               VM_NORESERVE);
> > +       if (IS_ERR(pcmd)) {
> > +               fput(backing);
> 
> > +               return (void *)pcmd;
> 
> Ditto.
> 
> > +       }
> 
> > +int sgx_encl_create(struct sgx_encl *encl, struct sgx_secs *secs)
> > +{
> > +       struct vm_area_struct *vma;
> > +       struct sgx_pageinfo pginfo;
> > +       struct sgx_secinfo secinfo;
> > +       struct sgx_epc_page *secs_epc;
> > +       long ret;
> > +
> > +       secs_epc = sgx_alloc_page(&encl->secs.impl, 0);
> > +       if (IS_ERR(secs_epc)) {
> 
> > +               ret = PTR_ERR(secs_epc);
> > +               return ret;
> 
> One line.
> 
> > +       }
> 
> > +       pginfo.addr = 0;
> > +       pginfo.contents = (unsigned long)secs;
> > +       pginfo.metadata = (unsigned long)&secinfo;
> > +       pginfo.secs = 0;
> > +       memset(&secinfo, 0, sizeof(secinfo));
> 
> + blank line here.
> 
> > +       ret = __ecreate((void *)&pginfo, sgx_epc_addr(secs_epc));
> 
> > +
> 
> - blank line here.
> 
> > +       if (ret) {
> > +               sgx_dbg(encl, "ECREATE returned %ld\n", ret);
> > +               return ret;
> > +       }
> 
> > +       down_read(&current->mm->mmap_sem);
> > +       ret = sgx_encl_find(current->mm, secs->base, &vma);
> 
> > +       if (ret != -ENOENT) {
> 
> > +               if (!ret)
> > +                       ret = -EINVAL;
> 
> > +               return ret;
> 
> return ret ? ret : -EINVAL;
> 
> > +       }
> 
> > +}
> 
> > +       for (i = 0; i < SGX_SECINFO_RESERVED_SIZE; i++)
> > +               if (secinfo->reserved[i])
> > +                       return -EINVAL;
> 
> memchr_inv() ?
> 
> > +       if (offset & (PAGE_SIZE - 1))
> > +               return false;
> 
> ~PAGE_MASK ?
> 
> > +       if ((tcs->fs_limit & 0xFFF) != 0xFFF)
> > +               return -EINVAL;
> > +
> > +       if ((tcs->gs_limit & 0xFFF) != 0xFFF)
> > +               return -EINVAL;
> 
> Are they ~PAGE_MASK as well? Please define properly.
> 
> > +       if (sgx_validate_secinfo(secinfo))
> > +               return -EINVAL;
> 
> + blank line
> 
> > +       if (page_type == SGX_SECINFO_TCS) {
> > +               ret = sgx_validate_tcs(encl, data);
> > +               if (ret)
> > +                       return ret;
> > +       }
> 
> + blank line
> 
> > +       ret = sgx_encl_grow(encl);
> > +       if (ret)
> > +               return ret;
> 
> + blank line
> 
> > +       mutex_lock(&encl->lock);
> > +       if (encl->flags & (SGX_ENCL_INITIALIZED | SGX_ENCL_DEAD)) {
> > +               mutex_unlock(&encl->lock);
> > +               return -EINVAL;
> > +       }
> 
> + blank line
> 
> > +       encl_page = sgx_encl_alloc_page(encl, addr);
> > +       if (IS_ERR(encl_page)) {
> > +               mutex_unlock(&encl->lock);
> > +               return PTR_ERR(encl_page);
> > +       }
> 
> + blank line
> 
> > +       ret = __sgx_encl_add_page(encl, encl_page, data, secinfo, mrmask);
> > +       if (ret)
> > +               sgx_encl_free_page(encl_page);
> 
> + blank line
> 
> > +       mutex_unlock(&encl->lock);
> 
> > +       u64 mrsigner[4];
> 
> Magic 4.
> 
> > +       for (i = 0; i < SGX_EINIT_SLEEP_COUNT; i++) {
> > +               for (j = 0; j < SGX_EINIT_SPIN_COUNT; j++) {
> > +                       ret = sgx_einit(sigstruct, token, encl->secs.epc_page,
> > +                                       mrsigner);
> 
> > +                       if (ret == SGX_UNMASKED_EVENT)
> > +                               continue;
> 
> > +                       else
> > +                               break;
> 
> Seems redundant
> 
> > +               }
> 
> > +       while (!list_empty(&encl->va_pages)) {
> > +               va_page = list_first_entry(&encl->va_pages, struct sgx_va_page,
> > +                                          list);
> 
> list_for_each_entry_safe() ?
> 
> > +               list_del(&va_page->list);
> > +               sgx_free_page(va_page->epc_page);
> > +               kfree(va_page);
> > +       }
> 
> --
> With Best Regards,
> Andy Shevchenko

Thanks, very detailed! Does not make sense to ack these separately so I
just say that I try to fix them all with care.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages
  2018-09-04 18:17         ` Sean Christopherson
@ 2018-09-05 17:36           ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-05 17:36 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Andy Shevchenko, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, nhorman, npmccallum, linux-sgx,
	serge.ayoun, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	suresh.b.siddha, Linux Kernel Mailing List

On Tue, Sep 04, 2018 at 11:17:35AM -0700, Sean Christopherson wrote:
> On Tue, Sep 04, 2018 at 09:01:15PM +0300, Andy Shevchenko wrote:
> > On Tue, Sep 4, 2018 a> +/**
> > 
> > > > > +       va = ioremap_cache(addr, size);
> > > > > +       if (!va)
> > > > > +               return -ENOMEM;
> > > >
> > > > I'm not sure this is a right API. Do we operate with memory? Does it
> > > > have I/O side effects?
> > > > If no, memremap() would be better to use.
> > >
> > > Preserving __iomem is desirable.  There aren't side effects per se,
> > > but direct non-enclave accesses to the EPC get abort page semantics so
> > > the kernel shouldn't be directly dereferencing a pointer to the EPC.
> > > Though by that argument, sgx_epc_bank.va, sgx_epc_addr's return and
> > > all ENCLS helpers should be tagged __iomem.
> > 
> > Why?
> > Does it related to *any* I/O?
> 
> No, hence my other comment that __private or a new tag altogether may
> be more appropriate.  The noderef attribute is what we truly care
> about.

My proposal is that we go with memremap() and use

#define __sgx_epc __attribute__((noderef))

It makes sense to check that direct EPC pointers are not passed to
functions when they are not supposed to.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-09-05 17:33     ` Jarkko Sakkinen
@ 2018-09-05 17:36       ` Andy Shevchenko
  2018-09-06  9:21         ` Jarkko Sakkinen
  0 siblings, 1 reply; 103+ messages in thread
From: Andy Shevchenko @ 2018-09-05 17:36 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, shay.katz-zamir,
	suresh.b.siddha, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, Eric Biggers,
	Linux Kernel Mailing List

On Wed, Sep 5, 2018 at 8:34 PM Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
> On Tue, Sep 04, 2018 at 08:59:58PM +0300, Andy Shevchenko wrote:
> > On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
> > <jarkko.sakkinen@linux.intel.com> wrote:

> Thanks, very detailed! Does not make sense to ack these separately so I
> just say that I try to fix them all with care.

Just comment on which you disagree.
I think one of them is the header file location. It seems I missed
it's current place.

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves
  2018-09-04 16:35                     ` Sean Christopherson
  2018-09-04 22:13                       ` Huang, Kai
@ 2018-09-05 17:39                       ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-05 17:39 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Huang, Kai, platform-driver-x86, x86, nhorman, linux-kernel,
	tglx, suresh.b.siddha, Ayoun, Serge, hpa, npmccallum, mingo,
	linux-sgx, Hansen, Dave

On Tue, Sep 04, 2018 at 09:35:46AM -0700, Sean Christopherson wrote:
> On Tue, Sep 04, 2018 at 06:30:21PM +0300, Jarkko Sakkinen wrote:
> > On Tue, Sep 04, 2018 at 07:54:51AM -0700, Sean Christopherson wrote:
> > > I don't see any value in trying to rule out specific causes of
> > > INVALID_TOKEN, but we should only retry EINIT if ret==INVALID_TOKEN
> > > and RDMSR(HASH0) != sgx_lepubkeyhash[0].  Only the first MSR needs to
> > > be checked for validity as they're a package deal, i.e. they'll all be
> > > valid or all be reset.  There shouldn't be a limit on retry attempts,
> > > e.g. the MSRs could theoretically be reset between WRMSR and EINIT.
> > 
> > Why is doing rdmsrs necessary? With the INVALID_TOKEN error we know we
> > are out-of-sync i.e. have been sleeping and then one just needs to do
> > wrmsrs.
> 
> As Kai mentioned, INVALID_TOKEN is returned for other reasons, e.g. a
> production enclave trying to use a debug token or reserved bits set in
> the token.  And in the KVM case, the hash and token are provided by
> the guest, so it's entirely possible the enclave/token is not signed
> with the key specified in the hash.  RDMSR is relatively inexpensive
> compared to the overall cost of EINIT.  Though of course EINIT failure
> isn't exactly a fast path, so I'm ok if you want to opt for simplicity
> and retry on INVALID_TOKEN without checking the MSRs, just make sure
> to add a comment indicating we're intentionally not checking the MSRs.

Great!

> > I think one retry should be enough given that VMM traps EINIT. One retry
> > is needed to take care of the guest itself (or host if we are running on
> > bare metal) having been in a sleep state.
> 
> Assuming we do RDMSR(hash0), that should be sufficient to prevent
> infinite retry and it protects against the MSRs being lost between
> WRMSR and EINIT during retry.  That being said, I'm ok retrying only
> once, especially if you want to omit the RDMSR.  Disabling preemption
> should prevent the kernel from suspending between WRMSR and EINIT,
> I'm just being paranoid.

But they are in the same preempt-disabled-region already?

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-09-05 17:36       ` Andy Shevchenko
@ 2018-09-06  9:21         ` Jarkko Sakkinen
  2018-09-06 17:35           ` Miguel Ojeda
  0 siblings, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-06  9:21 UTC (permalink / raw)
  To: Andy Shevchenko
  Cc: maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, shay.katz-zamir,
	suresh.b.siddha, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, Eric Biggers,
	Linux Kernel Mailing List

On Wed, Sep 05, 2018 at 08:36:54PM +0300, Andy Shevchenko wrote:
> On Wed, Sep 5, 2018 at 8:34 PM Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> > On Tue, Sep 04, 2018 at 08:59:58PM +0300, Andy Shevchenko wrote:
> > > On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
> > > <jarkko.sakkinen@linux.intel.com> wrote:
> 
> > Thanks, very detailed! Does not make sense to ack these separately so I
> > just say that I try to fix them all with care.
> 
> Just comment on which you disagree.
> I think one of them is the header file location. It seems I missed
> it's current place.
> 
> -- 
> With Best Regards,
> Andy Shevchenko

Ah, right, sorry forgot to comment it in LKML.

There is another open. If I grep through the kernel tree I see SPDX
headers that are decorated both with C99- and C89-style comments. I
guess I ended up using C99-style because when I was instructed to add
SPDX headers in the first place that was the example I was given. Still
checkpatch.pl complains about C99-style comments.

Which one is right and why the kernel tree is polluted with C99-headers
when they do not pass checkpatch.pl? How those commits were ever
accepted?

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-09-06  9:21         ` Jarkko Sakkinen
@ 2018-09-06 17:35           ` Miguel Ojeda
  2018-09-07  0:50             ` Joe Perches
  2018-09-10 18:33             ` Jarkko Sakkinen
  0 siblings, 2 replies; 103+ messages in thread
From: Miguel Ojeda @ 2018-09-06 17:35 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: Andy Shevchenko, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, shay.katz-zamir, Siddha,
	Suresh B, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, Eric Biggers,
	Linux Kernel Mailing List

Hi Jarkko,

On Thu, Sep 6, 2018 at 11:21 AM, Jarkko Sakkinen
<jarkko.sakkinen@linux.intel.com> wrote:
> There is another open. If I grep through the kernel tree I see SPDX
> headers that are decorated both with C99- and C89-style comments. I
> guess I ended up using C99-style because when I was instructed to add
> SPDX headers in the first place that was the example I was given. Still
> checkpatch.pl complains about C99-style comments.
>
> Which one is right and why the kernel tree is polluted with C99-headers
> when they do not pass checkpatch.pl? How those commits were ever
> accepted?

See Documentation/process/license-rules.rst. Headers should go with
C-style comments:

   The SPDX license identifier is added in form of a comment.  The comment
   style depends on the file type::

      C source: // SPDX-License-Identifier: <SPDX License Expression>
      C header: /* SPDX-License-Identifier: <SPDX License Expression> */

And:

   If a specific tool cannot handle the standard comment style, then the
   appropriate comment mechanism which the tool accepts shall be used. This
   is the reason for having the "/\* \*/" style comment in C header
   files. There was build breakage observed with generated .lds files where
   'ld' failed to parse the C++ comment. This has been fixed by now, but
   there are still older assembler tools which cannot handle C++ style
   comments.

The ones that got in are probably either old or they slipped through
(and they do not break the build).

Cheers,
Miguel

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-09-06 17:35           ` Miguel Ojeda
@ 2018-09-07  0:50             ` Joe Perches
  2018-09-07 17:02               ` Sean Christopherson
  2018-09-10 18:37               ` Jarkko Sakkinen
  2018-09-10 18:33             ` Jarkko Sakkinen
  1 sibling, 2 replies; 103+ messages in thread
From: Joe Perches @ 2018-09-07  0:50 UTC (permalink / raw)
  To: Miguel Ojeda, Jarkko Sakkinen
  Cc: Andy Shevchenko, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, shay.katz-zamir, Siddha,
	Suresh B, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, Eric Biggers,
	Linux Kernel Mailing List

On Thu, 2018-09-06 at 19:35 +0200, Miguel Ojeda wrote:
> > Which one is right and why the kernel tree is polluted with C99-headers
> > when they do not pass checkpatch.pl?

checkpatch ignores c99 headers since 2016.

$ git log --stat -p -1 dadf680de3c2eb4cba9840619991eda0cfe98778
commit dadf680de3c2eb4cba9840619991eda0cfe98778
Author: Joe Perches <joe@perches.com>
Date:   Tue Aug 2 14:04:33 2016 -0700

    checkpatch: allow c99 style // comments
    
    Sanitise the lines that contain c99 comments so that the error doesn't
    get emitted.
    
    Link: http://lkml.kernel.org/r/d4d22c34ad7bcc1bceb52f0742f76b7a6d585235.1468368420.git.joe@perches.com
    Signed-off-by: Joe Perches <joe@perches.com>
    Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
    Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
 scripts/checkpatch.pl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index a4476b61e93f..79273003d5e7 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -55,6 +55,7 @@ my $spelling_file = "$D/spelling.txt";
 my $codespell = 0;
 my $codespellfile = "/usr/share/codespell/dictionary.txt";
 my $color = 1;
+my $allow_c99_comments = 1;
 
 sub help {
        my ($exitcode) = @_;
@@ -1144,6 +1145,11 @@ sub sanitise_line {
                $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@;
        }
 
+       if ($allow_c99_comments && $res =~ m@(//.*$)@) {
+               my $match = $1;
+               $res =~ s/\Q$match\E/"$;" x length($match)/e;
+       }
+
        return $res;
 }
 

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-09-07  0:50             ` Joe Perches
@ 2018-09-07 17:02               ` Sean Christopherson
  2018-09-10 18:37               ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Sean Christopherson @ 2018-09-07 17:02 UTC (permalink / raw)
  To: Joe Perches
  Cc: Miguel Ojeda, Jarkko Sakkinen, Andy Shevchenko,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, nhorman, npmccallum, linux-sgx,
	serge.ayoun, shay.katz-zamir, Siddha, Suresh B, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Darren Hart, Andy Shevchenko,
	Herbert Xu, Eric Biggers, Linux Kernel Mailing List

On Thu, Sep 06, 2018 at 05:50:01PM -0700, Joe Perches wrote:
> On Thu, 2018-09-06 at 19:35 +0200, Miguel Ojeda wrote:
> > > Which one is right and why the kernel tree is polluted with C99-headers
> > > when they do not pass checkpatch.pl?
> 
> checkpatch ignores c99 headers since 2016.

Jarkko was referring to c99 comments for the SPDX license.  checkpatch
explicitly requires c-style comments for headers and assembly files as
dictated by Documentation/process/license-rules.rst.  

$ grep -r SPDX **/*.h | grep \/\/ | wc -l
665

$ grep -r SPDX **/*.S | grep \/\/ | wc -l
22

$ git show 9f3a89926d6df
commit 9f3a89926d6dfc30a4fd1bbcb92cc7b218d3786d
Author: Rob Herring <robh@kernel.org>
Date:   Tue Apr 10 16:33:13 2018 -0700

    checkpatch.pl: add SPDX license tag check

    Add SPDX license tag check based on the rules defined in
    Documentation/process/license-rules.rst.  To summarize, SPDX license
    tags should be on the 1st line (or 2nd line in scripts) using the
    appropriate comment style for the file type.

    Link: http://lkml.kernel.org/r/20180202154026.15298-1-robh@kernel.org
    Signed-off-by: Rob Herring <robh@kernel.org>
    Signed-off-by: Joe Perches <joe@perches.com>
    Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
    Cc: Andy Whitcroft <apw@canonical.com>
    Cc: Joe Perches <joe@perches.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Igor Stoppa <igor.stoppa@huawei.com>
    Cc: Jonathan Corbet <corbet@lwn.net>
    Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
    Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index b464a4c3f863..0f022b56f117 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2257,6 +2257,8 @@ sub process {

        my $camelcase_file_seeded = 0;

+       my $checklicenseline = 1;
+
        sanitise_line_reset();
        my $line;
        foreach my $rawline (@rawlines) {
@@ -2448,6 +2450,7 @@ sub process {
                        } else {
                                $check = $check_orig;
                        }
+                       $checklicenseline = 1;
                        next;
                }

@@ -2911,6 +2914,30 @@ sub process {
                        }
                }

+# check for using SPDX license tag at beginning of files
+               if ($realline == $checklicenseline) {
+                       if ($rawline =~ /^[ \+]\s*\#\!\s*\//) {
+                               $checklicenseline = 2;
+                       } elsif ($rawline =~ /^\+/) {
+                               my $comment = "";
+                               if ($realfile =~ /\.(h|s|S)$/) {
+                                       $comment = '/*';
+                               } elsif ($realfile =~ /\.(c|dts|dtsi)$/) {
+                                       $comment = '//';
+                               } elsif (($checklicenseline == 2) || $realfile =~ /\.(sh|pl|py|awk|tc)$/) {
+                                       $comment = '#';
+                               } elsif ($realfile =~ /\.rst$/) {
+                                       $comment = '..';
+                               }
+
+                               if ($comment !~ /^$/ &&
+                                   $rawline !~ /^\+\Q$comment\E SPDX-License-Identifier: /) {
+                                       WARN("SPDX_LICENSE_TAG",
+                                            "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr);
+                               }
+                       }
+               }
+
 # check we are in a valid source file if not then ignore this hunk
                next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/);




^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-09-06 17:35           ` Miguel Ojeda
  2018-09-07  0:50             ` Joe Perches
@ 2018-09-10 18:33             ` Jarkko Sakkinen
  1 sibling, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-10 18:33 UTC (permalink / raw)
  To: Miguel Ojeda
  Cc: Andy Shevchenko, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, shay.katz-zamir, Siddha,
	Suresh B, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, Eric Biggers,
	Linux Kernel Mailing List

On Thu, Sep 06, 2018 at 07:35:46PM +0200, Miguel Ojeda wrote:
> Hi Jarkko,
> 
> On Thu, Sep 6, 2018 at 11:21 AM, Jarkko Sakkinen
> <jarkko.sakkinen@linux.intel.com> wrote:
> > There is another open. If I grep through the kernel tree I see SPDX
> > headers that are decorated both with C99- and C89-style comments. I
> > guess I ended up using C99-style because when I was instructed to add
> > SPDX headers in the first place that was the example I was given. Still
> > checkpatch.pl complains about C99-style comments.
> >
> > Which one is right and why the kernel tree is polluted with C99-headers
> > when they do not pass checkpatch.pl? How those commits were ever
> > accepted?
> 
> See Documentation/process/license-rules.rst. Headers should go with
> C-style comments:
> 
>    The SPDX license identifier is added in form of a comment.  The comment
>    style depends on the file type::
> 
>       C source: // SPDX-License-Identifier: <SPDX License Expression>
>       C header: /* SPDX-License-Identifier: <SPDX License Expression> */
> 
> And:
> 
>    If a specific tool cannot handle the standard comment style, then the
>    appropriate comment mechanism which the tool accepts shall be used. This
>    is the reason for having the "/\* \*/" style comment in C header
>    files. There was build breakage observed with generated .lds files where
>    'ld' failed to parse the C++ comment. This has been fixed by now, but
>    there are still older assembler tools which cannot handle C++ style
>    comments.
> 
> The ones that got in are probably either old or they slipped through
> (and they do not break the build).

Thank you, this clears things up. Highly appreciated!

> Cheers,
> Miguel

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-09-07  0:50             ` Joe Perches
  2018-09-07 17:02               ` Sean Christopherson
@ 2018-09-10 18:37               ` Jarkko Sakkinen
  2018-09-10 21:22                 ` Joe Perches
  1 sibling, 1 reply; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-10 18:37 UTC (permalink / raw)
  To: Joe Perches
  Cc: Miguel Ojeda, Andy Shevchenko,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, shay.katz-zamir, Siddha,
	Suresh B, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, Eric Biggers,
	Linux Kernel Mailing List

On Thu, Sep 06, 2018 at 05:50:01PM -0700, Joe Perches wrote:
> On Thu, 2018-09-06 at 19:35 +0200, Miguel Ojeda wrote:
> > > Which one is right and why the kernel tree is polluted with C99-headers
> > > when they do not pass checkpatch.pl?
> 
> checkpatch ignores c99 headers since 2016.

For headers I get these warnings:

WARNING: Missing or malformed SPDX-License-Identifier tag in line 1
#243: FILE: drivers/platform/x86/intel_sgx/sgx.h:1:
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 11/13] platform/x86: Intel SGX driver
  2018-09-10 18:37               ` Jarkko Sakkinen
@ 2018-09-10 21:22                 ` Joe Perches
  0 siblings, 0 replies; 103+ messages in thread
From: Joe Perches @ 2018-09-10 21:22 UTC (permalink / raw)
  To: Jarkko Sakkinen
  Cc: Miguel Ojeda, Andy Shevchenko,
	maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
	Platform Driver, Dave Hansen, sean.j.christopherson, nhorman,
	npmccallum, linux-sgx, serge.ayoun, shay.katz-zamir, Siddha,
	Suresh B, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Darren Hart, Andy Shevchenko, Herbert Xu, Eric Biggers,
	Linux Kernel Mailing List

On Mon, 2018-09-10 at 21:37 +0300, Jarkko Sakkinen wrote:
> On Thu, Sep 06, 2018 at 05:50:01PM -0700, Joe Perches wrote:
> > On Thu, 2018-09-06 at 19:35 +0200, Miguel Ojeda wrote:
> > > > Which one is right and why the kernel tree is polluted with C99-headers
> > > > when they do not pass checkpatch.pl?
> > 
> > checkpatch ignores c99 headers since 2016.
> 
> For headers I get these warnings:
> 
> WARNING: Missing or malformed SPDX-License-Identifier tag in line 1
> #243: FILE: drivers/platform/x86/intel_sgx/sgx.h:1:
> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)

Because .h files are supposed to use /* */


^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-08-27 18:53 ` [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager Jarkko Sakkinen
                     ` (2 preceding siblings ...)
  2018-09-03 19:02   ` Andy Shevchenko
@ 2018-09-11 15:04   ` Sean Christopherson
  2018-09-16 11:40     ` Jarkko Sakkinen
  3 siblings, 1 reply; 103+ messages in thread
From: Sean Christopherson @ 2018-09-11 15:04 UTC (permalink / raw)
  To: Jarkko Sakkinen, x86, platform-driver-x86
  Cc: dave.hansen, nhorman, npmccallum, linux-sgx, Thomas Gleixner,
	Ingo Molnar, H. Peter Anvin, Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Mon, 2018-08-27 at 21:53 +0300, Jarkko Sakkinen wrote:
> Add a Enclave Page Cache (EPC) memory manager that can be used to
> allocate and free EPC pages. The swapper thread ksgxswapd reclaims pages
> on the event when the number of free EPC pages goes below
> %SGX_NR_LOW_PAGES up until it reaches %SGX_NR_HIGH_PAGES.
> 
> Pages are reclaimed in LRU fashion from a global list. The consumers
> take care of calling EBLOCK (block page from new accesses), ETRACK
> (restart counting the entering hardware threads) and EWB (write page to
> the regular memory) because executing these operations usually (if not
> always) requires to do some subsystem-internal locking operations.
> 
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> ---
>  arch/x86/include/asm/sgx.h      |  56 ++++--
>  arch/x86/kernel/cpu/intel_sgx.c | 322 ++++++++++++++++++++++++++++++++
>  2 files changed, 362 insertions(+), 16 deletions(-)

...

> +/**
> + * sgx_reclaim_pages - reclaim EPC pages from the consumers
> + *
> + * Takes a fixed chunk of pages from the global list of consumed EPC pages and
> + * tries to swap them. Only the pages that are either being freed by the
> + * consumer or actively used are skipped.
> + */
> +static void sgx_reclaim_pages(void)
> +{
> +	struct sgx_epc_page *chunk[SGX_NR_TO_SCAN + 1];

The array size should simply be SGX_NR_TO_SCAN.  The +1 is a remnant
from the previous version that bounded the for-loops with "!chunk[i]"
check instead of "i < j".  No functional issue, essentially just an
unused variable.

> +	struct sgx_epc_page *epc_page;
> +	struct sgx_epc_bank *bank;
> +	int i, j;
> +
> +	spin_lock(&sgx_active_page_list_lock);
> +	for (i = 0, j = 0; i < SGX_NR_TO_SCAN; i++) {
> +		if (list_empty(&sgx_active_page_list))
> +			break;
> +
> +		epc_page = list_first_entry(&sgx_active_page_list,
> +					    struct sgx_epc_page, list);
> +		list_del_init(&epc_page->list);
> +
> +		if (epc_page->impl->ops->get(epc_page))
> +			chunk[j++] = epc_page;
> +		else
> +			epc_page->desc &= ~SGX_EPC_PAGE_RECLAIMABLE;
> +	}
> +	spin_unlock(&sgx_active_page_list_lock);
> +
> +	for (i = 0; i < j; i++) {
> +		epc_page = chunk[i];
> +		if (epc_page->impl->ops->reclaim(epc_page))
> +			continue;
> +
> +		spin_lock(&sgx_active_page_list_lock);
> +		list_add_tail(&epc_page->list, &sgx_active_page_list);
> +		spin_unlock(&sgx_active_page_list_lock);
> +
> +		epc_page->impl->ops->put(epc_page);
> +		chunk[i] = NULL;
> +	}
> +
> +	for (i = 0; i < j; i++) {
> +		epc_page = chunk[i];
> +		if (epc_page)
> +			epc_page->impl->ops->block(epc_page);
> +	}
> +
> +	for (i = 0; i < j; i++) {
> +		epc_page = chunk[i];
> +		if (epc_page) {
> +			epc_page->impl->ops->write(epc_page);
> +			epc_page->impl->ops->put(epc_page);
> +
> +			/*
> +			 * Put the page back on the free list only after we
> +			 * have put() our reference to the owner of the EPC
> +			 * page, otherwise the page could be re-allocated and
> +			 * we'd call put() on the wrong impl.
> +			 */
> +			epc_page->desc &= ~SGX_EPC_PAGE_RECLAIMABLE;
> +
> +			bank = sgx_epc_bank(epc_page);
> +			spin_lock(&bank->lock);
> +			bank->pages[bank->free_cnt++] = epc_page;
> +			spin_unlock(&bank->lock);
> +		}
> +	}
> +}


^ permalink raw reply	[flat|nested] 103+ messages in thread

* Re: [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager
  2018-09-11 15:04   ` Sean Christopherson
@ 2018-09-16 11:40     ` Jarkko Sakkinen
  0 siblings, 0 replies; 103+ messages in thread
From: Jarkko Sakkinen @ 2018-09-16 11:40 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: x86, platform-driver-x86, dave.hansen, nhorman, npmccallum,
	linux-sgx, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
	Suresh Siddha, Serge Ayoun,
	open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)

On Tue, Sep 11, 2018 at 08:04:39AM -0700, Sean Christopherson wrote:
> > +static void sgx_reclaim_pages(void)
> > +{
> > +	struct sgx_epc_page *chunk[SGX_NR_TO_SCAN + 1];
> 
> The array size should simply be SGX_NR_TO_SCAN.  The +1 is a remnant
> from the previous version that bounded the for-loops with "!chunk[i]"
> check instead of "i < j".  No functional issue, essentially just an
> unused variable.

Thanks, yep, it is cruft.

/Jarkko

^ permalink raw reply	[flat|nested] 103+ messages in thread

end of thread, other threads:[~2018-09-16 11:40 UTC | newest]

Thread overview: 103+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-27 18:53 [PATCH v13 00/13] Intel SGX1 support Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 01/13] x86/sgx: Update MAINTAINERS Jarkko Sakkinen
2018-09-03 12:56   ` Andy Shevchenko
2018-09-03 19:10     ` Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 02/13] x86/cpufeature: Add SGX and SGX_LC CPU features Jarkko Sakkinen
2018-08-28  0:07   ` Huang, Kai
2018-08-28  7:17     ` Jarkko Sakkinen
2018-08-29  7:36       ` Huang, Kai
2018-08-31 12:19         ` Jarkko Sakkinen
2018-08-31 16:18   ` Dr. Greg
2018-08-27 18:53 ` [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX Jarkko Sakkinen
2018-08-27 19:39   ` Dave Hansen
2018-08-28  7:23     ` Jarkko Sakkinen
2018-08-28 10:21   ` Borislav Petkov
2018-08-28 10:38     ` Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 04/13] x86/sgx: Architectural structures Jarkko Sakkinen
2018-08-27 19:41   ` Dave Hansen
2018-08-28  8:08     ` Jarkko Sakkinen
2018-09-03 13:16   ` Andy Shevchenko
2018-09-03 19:17     ` Jarkko Sakkinen
2018-09-04 16:04     ` Dave Hansen
2018-09-04 16:06       ` Andy Shevchenko
2018-09-05 17:32       ` Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 05/13] x86/msr: Add SGX definitions to msr-index.h Jarkko Sakkinen
2018-08-27 19:42   ` Dave Hansen
2018-08-28  8:11     ` Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 06/13] x86/sgx: Detect Intel SGX Jarkko Sakkinen
2018-08-27 19:53   ` Dave Hansen
2018-08-28  8:28     ` Jarkko Sakkinen
2018-09-03 14:26   ` Andy Shevchenko
2018-09-04  9:56     ` Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 07/13] x86/sgx: Add data structures for tracking the EPC pages Jarkko Sakkinen
2018-08-27 21:07   ` Dave Hansen
2018-08-28 10:30     ` Jarkko Sakkinen
2018-08-28 16:53       ` Dave Hansen
2018-08-28 21:34         ` Sean Christopherson
2018-08-31 11:13           ` Jarkko Sakkinen
2018-08-31 11:10         ` Jarkko Sakkinen
2018-09-03 14:41   ` Andy Shevchenko
2018-09-04  9:59     ` Jarkko Sakkinen
2018-09-04 17:49     ` Sean Christopherson
2018-09-04 18:01       ` Andy Shevchenko
2018-09-04 18:17         ` Sean Christopherson
2018-09-05 17:36           ` Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 08/13] x86/sgx: Add wrappers for ENCLS leaf functions Jarkko Sakkinen
2018-09-03 15:01   ` Andy Shevchenko
2018-09-04 11:09     ` Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 09/13] x86/sgx: Enclave Page Cache (EPC) memory manager Jarkko Sakkinen
2018-08-27 21:14   ` Dave Hansen
2018-08-28  8:36     ` Jarkko Sakkinen
2018-08-27 21:15   ` Dave Hansen
2018-08-28  8:35     ` Jarkko Sakkinen
2018-08-28 14:07       ` Dave Hansen
2018-08-28 21:22         ` Sean Christopherson
2018-08-28 21:26           ` Dave Hansen
2018-08-28 21:52             ` Sean Christopherson
2018-08-31 11:22           ` Jarkko Sakkinen
2018-09-03 19:02   ` Andy Shevchenko
2018-09-04 15:38     ` Jarkko Sakkinen
2018-09-04 15:45       ` Sean Christopherson
2018-09-11 15:04   ` Sean Christopherson
2018-09-16 11:40     ` Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 10/13] x86/sgx: Add sgx_einit() for initializing enclaves Jarkko Sakkinen
2018-08-27 21:41   ` Huang, Kai
2018-08-28  7:01     ` Jarkko Sakkinen
2018-08-29  7:33       ` Huang, Kai
2018-08-29 20:33         ` Sean Christopherson
2018-08-29 20:58           ` Huang, Kai
2018-08-29 21:09             ` Sean Christopherson
2018-08-30  1:45               ` Huang, Kai
2018-08-31 17:43                 ` Sean Christopherson
2018-08-31 21:34                   ` Dr. Greg
2018-09-03 19:27                     ` Jarkko Sakkinen
2018-09-03 18:15                 ` Jarkko Sakkinen
2018-08-31 12:17         ` Jarkko Sakkinen
2018-08-31 18:15           ` Sean Christopherson
2018-09-03 19:19             ` Jarkko Sakkinen
2018-09-03 23:45               ` Huang, Kai
2018-09-04 14:54                 ` Sean Christopherson
2018-09-04 15:30                   ` Jarkko Sakkinen
2018-09-04 16:35                     ` Sean Christopherson
2018-09-04 22:13                       ` Huang, Kai
2018-09-05 17:39                       ` Jarkko Sakkinen
2018-09-04 15:26                 ` Jarkko Sakkinen
2018-09-03 13:53   ` Jann Horn
2018-09-04  9:55     ` Jarkko Sakkinen
2018-09-04 16:05   ` Andy Shevchenko
2018-08-27 18:53 ` [PATCH v13 11/13] platform/x86: Intel SGX driver Jarkko Sakkinen
2018-09-04 17:59   ` Andy Shevchenko
2018-09-05 17:33     ` Jarkko Sakkinen
2018-09-05 17:36       ` Andy Shevchenko
2018-09-06  9:21         ` Jarkko Sakkinen
2018-09-06 17:35           ` Miguel Ojeda
2018-09-07  0:50             ` Joe Perches
2018-09-07 17:02               ` Sean Christopherson
2018-09-10 18:37               ` Jarkko Sakkinen
2018-09-10 21:22                 ` Joe Perches
2018-09-10 18:33             ` Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 12/13] platform/x86: ptrace() support for the " Jarkko Sakkinen
2018-08-27 18:53 ` [PATCH v13 13/13] x86/sgx: Driver documentation Jarkko Sakkinen
2018-08-27 19:40   ` Randy Dunlap
2018-08-28  7:58     ` Jarkko Sakkinen
2018-08-28  8:03   ` Jarkko Sakkinen

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