From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_NEOMUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94B79C433F4 for ; Thu, 30 Aug 2018 07:47:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D45A620645 for ; Thu, 30 Aug 2018 07:47:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D45A620645 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727755AbeH3LsH (ORCPT ); Thu, 30 Aug 2018 07:48:07 -0400 Received: from mail.bootlin.com ([62.4.15.54]:47931 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727247AbeH3LsH (ORCPT ); Thu, 30 Aug 2018 07:48:07 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 8F9E2208C7; Thu, 30 Aug 2018 09:47:15 +0200 (CEST) Received: from localhost (AAubervilliers-681-1-92-107.w90-88.abo.wanadoo.fr [90.88.33.107]) by mail.bootlin.com (Postfix) with ESMTPSA id 4FB8522A3E; Thu, 30 Aug 2018 09:47:05 +0200 (CEST) Date: Thu, 30 Aug 2018 09:47:04 +0200 From: Maxime Ripard To: Georgi Djakov Cc: Rob Herring , "open list:THERMAL" , Greg Kroah-Hartman , "Rafael J. Wysocki" , Michael Turquette , Kevin Hilman , Vincent Guittot , Saravana Kannan , Bjorn Andersson , Amit Kucheria , seansw@qti.qualcomm.com, daidavid1@codeaurora.org, Evan Green , Mark Rutland , Lorenzo Pieralisi , Alexandre Bailon , Arnd Bergmann , "linux-kernel@vger.kernel.org" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-arm-msm , devicetree@vger.kernel.org Subject: Re: [PATCH v7 2/8] dt-bindings: Introduce interconnect provider bindings Message-ID: <20180830074704.56x5xzfhauhd7ncy@flea> References: <20180731161340.13000-1-georgi.djakov@linaro.org> <20180731161340.13000-3-georgi.djakov@linaro.org> <20180820153207.xx5outviph7ec76p@flea> <672e6c6c-222f-5e7f-5d0c-acc8da68b1ab@linaro.org> <20180827151140.luysp2kfbcq6patg@flea> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="7643npv2arymjmqd" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --7643npv2arymjmqd Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Wed, Aug 29, 2018 at 03:33:29PM +0300, Georgi Djakov wrote: > On 08/27/2018 06:11 PM, Maxime Ripard wrote: > > On Fri, Aug 24, 2018 at 10:35:23AM -0500, Rob Herring wrote: > >> On Fri, Aug 24, 2018 at 9:51 AM Georgi Djakov wrote: > >>> > >>> Hi Maxime, > >>> > >>> On 08/20/2018 06:32 PM, Maxime Ripard wrote: > >>>> Hi Georgi, > >>>> > >>>> On Tue, Aug 07, 2018 at 05:54:38PM +0300, Georgi Djakov wrote: > >>>>>> There is also a patch series from Maxime Ripard that's addressing = the > >>>>>> same general area. See "dt-bindings: Add a dma-parent property". We > >>>>>> don't need multiple ways to address describing the device to memory > >>>>>> paths, so you all had better work out a common solution. > >>>>> > >>>>> Looks like this fits exactly into the interconnect API concept. I s= ee > >>>>> MBUS as interconnect provider and display/camera as consumers, that > >>>>> report their bandwidth needs. I am also planning to add support for > >>>>> priority. > >>>> > >>>> Thanks for working on this. After looking at your serie, the one thi= ng > >>>> I'm a bit uncertain about (and the most important one to us) is how = we > >>>> would be able to tell through which interconnect the DMA are done. > >>>> > >>>> This is important to us since our topology is actually quite simple = as > >>>> you've seen, but the RAM is not mapped on that bus and on the CPU's, > >>>> so we need to apply an offset to each buffer being DMA'd. > >>> > >>> Ok, i see - your problem is not about bandwidth scaling but about usi= ng > >>> different memory ranges by the driver to access the same location. So > >>> this is not really the same and your problem is different. Also the > >>> interconnect bindings are describing a path and endpoints. However i = am > >>> open to any ideas. > >> > >> It may be different things you need, but both are related to the path > >> between a bus master and memory. We can't have each 'problem' > >> described in a different way. Well, we could as long as each platform > >> has different problems, but that's unlikely. > >> > >> It could turn out that the only commonality is property naming > >> convention, but that's still better than 2 independent solutions. > >=20 > > Yeah, I really don't think the two issues are unrelated. Can we maybe > > have a particular interconnect-names value to mark the interconnect > > being used to perform DMA? >=20 > We can call one of the paths "dma" and use it to perform DMA for the > current device. I don't see a problem with this. The name of the path is > descriptive and makes sense. And by doing we avoid adding more DT > properties, which would be an other option. That works for me. If Rob is fine with it too, I'll send an updated version of my serie based on yours. Thanks! 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