From: Andrea Merello <andrea.merello@gmail.com>
To: vkoul@kernel.org, dan.j.williams@intel.com,
michal.simek@xilinx.com, appana.durga.rao@xilinx.com,
dmaengine@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, devicetree@vger.kernel.org,
radhey.shyam.pandey@xilinx.com,
Andrea Merello <andrea.merello@gmail.com>
Subject: [PATCH v5 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property
Date: Fri, 7 Sep 2018 08:24:58 +0200 [thread overview]
Message-ID: <20180907062502.8241-3-andrea.merello@gmail.com> (raw)
In-Reply-To: <20180907062502.8241-1-andrea.merello@gmail.com>
The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add documentation for it.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
---
Changes in v2:
- change property name
- property is now optional
- cc DT maintainer
Changes in v3:
- reword
- cc DT maintainerS and ML
Changes in v4:
- specify the unit, the valid range and the default value
Changes in v5:
- commit message trivial fix
- fix spaces before tab
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index a2b8bfaec43c..5df4eac7300c 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -41,6 +41,10 @@ Optional properties:
- xlnx,include-sg: Tells configured for Scatter-mode in
the hardware.
Optional properties for AXI DMA:
+- xlnx,sg-length-width: Should be set to the width in bits of the length
+ register as configured in h/w. Takes values {8...26}. If the property
+ is missing or invalid then the default value 23 is used. This is the
+ maximum value that is supported by all IP versions.
- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
--
2.17.1
next prev parent reply other threads:[~2018-09-07 6:25 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-07 6:24 [PATCH v5 1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation Andrea Merello
2018-09-07 6:24 ` [PATCH v5 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors Andrea Merello
2018-09-18 16:21 ` Vinod
2018-09-28 7:11 ` Andrea Merello
2018-10-02 14:58 ` Vinod
2018-09-07 6:24 ` Andrea Merello [this message]
2018-09-10 18:19 ` [PATCH v5 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property Rob Herring
2018-09-07 6:24 ` [PATCH v5 4/7] dmaengine: xilinx_dma: program hardware supported buffer length Andrea Merello
2018-09-18 16:25 ` Vinod
2018-09-28 6:53 ` Andrea Merello
2018-10-02 14:56 ` Vinod
2018-10-08 6:46 ` Andrea Merello
2018-09-07 6:25 ` [PATCH v5 5/7] dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather Andrea Merello
2018-09-07 6:25 ` [PATCH v5 6/7] dt-bindings: dmaengine: xilinx_dma: drop has-sg property Andrea Merello
2018-09-07 6:25 ` [PATCH v5 7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP Andrea Merello
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