From: Greg KH <gregkh@linuxfoundation.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: stable@vger.kernel.org, will.deacon@arm.com,
mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, catalin.marinas@arm.com
Subject: Re: [stable PATCH 2/2] arm64: Handle mismatched cache type
Date: Wed, 12 Sep 2018 21:38:34 +0200 [thread overview]
Message-ID: <20180912193834.GG21563@kroah.com> (raw)
In-Reply-To: <1536052210-11625-2-git-send-email-suzuki.poulose@arm.com>
On Tue, Sep 04, 2018 at 10:10:10AM +0100, Suzuki K Poulose wrote:
> commit 314d53d297980676011e6fd83dac60db4a01dc70 upstream
>
> Track mismatches in the cache type register (CTR_EL0), other
> than the D/I min line sizes and trap user accesses if there are any.
>
> Fixes: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
> Cc: <stable@vger.kernel.org> # v4.9
Same 4.9 question here as well.
thanks,
greg k-h
next prev parent reply other threads:[~2018-09-12 19:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-04 9:10 [stable PATCH 1/2] arm64: Fix mismatched cache line size detection Suzuki K Poulose
2018-09-04 9:10 ` [stable PATCH 2/2] arm64: Handle mismatched cache type Suzuki K Poulose
2018-09-12 19:38 ` Greg KH [this message]
2018-09-12 19:38 ` [stable PATCH 1/2] arm64: Fix mismatched cache line size detection Greg KH
2018-09-13 9:54 ` Suzuki K Poulose
2018-09-13 12:19 ` Greg KH
2018-09-13 12:40 ` Greg KH
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