From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9482AECE562 for ; Mon, 17 Sep 2018 23:39:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 35E832146D for ; Mon, 17 Sep 2018 23:39:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 35E832146D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=goodmis.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728058AbeIRFJZ (ORCPT ); Tue, 18 Sep 2018 01:09:25 -0400 Received: from mail.kernel.org ([198.145.29.99]:35556 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725849AbeIRFJY (ORCPT ); Tue, 18 Sep 2018 01:09:24 -0400 Received: from gandalf.local.home (cpe-66-24-56-78.stny.res.rr.com [66.24.56.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7C5972088F; Mon, 17 Sep 2018 23:39:42 +0000 (UTC) Date: Mon, 17 Sep 2018 19:39:40 -0400 From: Steven Rostedt To: Sai Prakash Ranjan Cc: Ingo Molnar , Laura Abbott , Kees Cook , Anton Vorontsov , Rob Herring , devicetree@vger.kernel.org, Colin Cross , Jason Baron , Tony Luck , Arnd Bergmann , Catalin Marinas , Will Deacon , Joel Fernandes , Masami Hiramatsu , Joe Perches , Jim Cromie , Rajendra Nayak , Vivek Gautam , Sibi Sankar , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Greg Kroah-Hartman , Ingo Molnar , Tom Zanussi , Prasad Sodagudi , tsoni@codeaurora.org, Bryan Huntsman , Tingwei Zhang Subject: Re: [PATCH 5/6] arm64/io: Add header for instrumentation of io operations Message-ID: <20180917193940.3d68ef88@gandalf.local.home> In-Reply-To: References: X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 9 Sep 2018 01:57:06 +0530 Sai Prakash Ranjan wrote: > The new asm-generic/io-instrumented.h will keep arch code > clean and separate from instrumented version which traces > io register accesses. This instrumented header can later > be included in arm as well for tracing io register accesses. > Looks good to me. Acked-by: Steven Rostedt (VMware) -- Steve > Suggested-by: Will Deacon > Signed-off-by: Sai Prakash Ranjan > --- > arch/arm64/include/asm/io.h | 25 ++++++--------- > include/asm-generic/io-instrumented.h | 45 +++++++++++++++++++++++++++ > 2 files changed, 54 insertions(+), 16 deletions(-) > create mode 100644 include/asm-generic/io-instrumented.h > > diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h > index 35b2e50f17fb..768a6a8c5778 100644 > --- a/arch/arm64/include/asm/io.h > +++ b/arch/arm64/include/asm/io.h > @@ -36,32 +36,27 @@ > /* > * Generic IO read/write. These perform native-endian accesses. > */ > -#define __raw_writeb __raw_writeb > -static inline void __raw_writeb(u8 val, volatile void __iomem *addr) > +static inline void arch_raw_writeb(u8 val, volatile void __iomem *addr) > { > asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr)); > } > > -#define __raw_writew __raw_writew > -static inline void __raw_writew(u16 val, volatile void __iomem *addr) > +static inline void arch_raw_writew(u16 val, volatile void __iomem *addr) > { > asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr)); > } > > -#define __raw_writel __raw_writel > -static inline void __raw_writel(u32 val, volatile void __iomem *addr) > +static inline void arch_raw_writel(u32 val, volatile void __iomem *addr) > { > asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); > } > > -#define __raw_writeq __raw_writeq > -static inline void __raw_writeq(u64 val, volatile void __iomem *addr) > +static inline void arch_raw_writeq(u64 val, volatile void __iomem *addr) > { > asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); > } > > -#define __raw_readb __raw_readb > -static inline u8 __raw_readb(const volatile void __iomem *addr) > +static inline u8 arch_raw_readb(const volatile void __iomem *addr) > { > u8 val; > asm volatile(ALTERNATIVE("ldrb %w0, [%1]", > @@ -71,8 +66,7 @@ static inline u8 __raw_readb(const volatile void __iomem *addr) > return val; > } > > -#define __raw_readw __raw_readw > -static inline u16 __raw_readw(const volatile void __iomem *addr) > +static inline u16 arch_raw_readw(const volatile void __iomem *addr) > { > u16 val; > > @@ -83,8 +77,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr) > return val; > } > > -#define __raw_readl __raw_readl > -static inline u32 __raw_readl(const volatile void __iomem *addr) > +static inline u32 arch_raw_readl(const volatile void __iomem *addr) > { > u32 val; > asm volatile(ALTERNATIVE("ldr %w0, [%1]", > @@ -94,8 +87,7 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) > return val; > } > > -#define __raw_readq __raw_readq > -static inline u64 __raw_readq(const volatile void __iomem *addr) > +static inline u64 arch_raw_readq(const volatile void __iomem *addr) > { > u64 val; > asm volatile(ALTERNATIVE("ldr %0, [%1]", > @@ -193,6 +185,7 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); > #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) > #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); }) > > +#include > #include > > /* > diff --git a/include/asm-generic/io-instrumented.h b/include/asm-generic/io-instrumented.h > new file mode 100644 > index 000000000000..7b050e2487ed > --- /dev/null > +++ b/include/asm-generic/io-instrumented.h > @@ -0,0 +1,45 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef _ASM_GENERIC_IO_INSTRUMENTED_H > +#define _ASM_GENERIC_IO_INSTRUMENTED_H > + > +#if defined(CONFIG_TRACING_EVENTS_IO) > +#include > + > +extern struct tracepoint __tracepoint_io_write; > +extern struct tracepoint __tracepoint_io_read; > +#define io_tracepoint_active(t) static_key_false(&(t).key) > +extern void do_trace_io_write(const char *type, void *addr); > +extern void do_trace_io_read(const char *type, void *addr); > +#else > +#define io_tracepoint_active(t) false > +static inline void do_trace_io_write(const char *type, void *addr) {} > +static inline void do_trace_io_read(const char *type, void *addr) {} > +#endif /* CONFIG_TRACING_EVENTS_IO */ > + > +#define __raw_write(v, a, _l) ({ \ > + volatile void __iomem *_a = (a); \ > + if (io_tracepoint_active(__tracepoint_io_write)) \ > + do_trace_io_write(__stringify(write##_l), (void __force *)(_a));\ > + arch_raw_write##_l((v), _a); \ > + }) > + > +#define __raw_writeb(v, a) __raw_write((v), a, b) > +#define __raw_writew(v, a) __raw_write((v), a, w) > +#define __raw_writel(v, a) __raw_write((v), a, l) > +#define __raw_writeq(v, a) __raw_write((v), a, q) > + > +#define __raw_read(a, _l, _t) ({ \ > + _t __a; \ > + const volatile void __iomem *_a = (a); \ > + if (io_tracepoint_active(__tracepoint_io_read)) \ > + do_trace_io_read(__stringify(read##_l), (void __force *)(_a)); \ > + __a = arch_raw_read##_l(_a); \ > + __a; \ > + }) > + > +#define __raw_readb(a) __raw_read((a), b, u8) > +#define __raw_readw(a) __raw_read((a), w, u16) > +#define __raw_readl(a) __raw_read((a), l, u32) > +#define __raw_readq(a) __raw_read((a), q, u64) > + > +#endif /* _ASM_GENERIC_IO_INSTRUMENTED_H */