From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4092CECE561 for ; Thu, 20 Sep 2018 09:58:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CB07E21527 for ; Thu, 20 Sep 2018 09:58:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB07E21527 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731900AbeITPkm (ORCPT ); Thu, 20 Sep 2018 11:40:42 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:7295 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727633AbeITPkm (ORCPT ); Thu, 20 Sep 2018 11:40:42 -0400 X-UUID: 8c491479145349289964abb744d3652b-20180920 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1281241049; Thu, 20 Sep 2018 17:57:58 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 20 Sep 2018 17:57:56 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 20 Sep 2018 17:57:56 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Rob Herring CC: James Liao , Fan Chen , , , , , , Weiyi Lu Subject: [PATCH v1 0/3] update Mediatek MT2712 clock Date: Thu, 20 Sep 2018 17:57:24 +0800 Message-ID: <20180920095727.11868-2-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.12.5.2.gbdf23ab In-Reply-To: <20180920095727.11868-1-weiyi.lu@mediatek.com> References: <20180920095727.11868-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: D346A50080EA793DF0670B764E2C66A0B5A194E46A784B18A6278D5681F8C99E2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series is based on v4.19-rc1. Basically, it's for the 3rd ECO design change of MT2712. And also add support for switching pll reference source for some MT2712 projects. *** BLURB HERE *** Weiyi Lu (3): dt-bindings: clock: add clock for MT2712 clk: mediatek: update clock driver of MT2712 clk: mediatek: mt2712: add pll reference support drivers/clk/mediatek/clk-mt2712.c | 95 ++++++++++++++++++++++++++-------- include/dt-bindings/clock/mt2712-clk.h | 3 +- 2 files changed, 76 insertions(+), 22 deletions(-) -- 2.12.5.2.gbdf23ab