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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Jingoo Han <jingoohan1@gmail.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	<Gustavo.Pimentel@synopsys.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Santosh Shilimkar <ssantosh@kernel.org>,
	Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: [RFC PATCH 28/40] PCI: dwc: Fix ATU identification for designware version >= 4.80
Date: Fri, 21 Sep 2018 15:51:43 +0530	[thread overview]
Message-ID: <20180921102155.22839-29-kishon@ti.com> (raw)
In-Reply-To: <20180921102155.22839-1-kishon@ti.com>

Synopsys designware version >= 4.80 uses a separate register space
for programming ATU. The current code identifies if there exists a
separate register space by accessing the register address of ATUs
in designware version < 4.80. Accessing this address results in
abort in the case of K2G.

Fix it here by adding "version" member to struct dw_pcie. This should
be set by platform specific drivers and designware core will use it
to identify if the platform has a separate ATU space. For platforms
which hasn't populated the version member, the old method of
identification will still be used.

Since identifying if iATU is enabled or not is specific to both
host mode and device mode, setting of iatu_unroll_enabled is moved
from pcie-designware-host.c to pcie-designware.c

Use the register space having reg-names as "atu" for the ATU
address space. For platforms which hasn't populated atu register space,
use the existing hard coded address.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 .../pci/controller/dwc/pcie-designware-host.c | 16 ------
 drivers/pci/controller/dwc/pcie-designware.c  | 50 +++++++++++++++++--
 drivers/pci/controller/dwc/pcie-designware.h  |  9 ++--
 3 files changed, 52 insertions(+), 23 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 29a05759a294..37ea4f7e77b0 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -637,17 +637,6 @@ static struct pci_ops dw_pcie_ops = {
 	.write = dw_pcie_wr_conf,
 };
 
-static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
-{
-	u32 val;
-
-	val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
-	if (val == 0xffffffff)
-		return 1;
-
-	return 0;
-}
-
 void dw_pcie_setup_rc(struct pcie_port *pp)
 {
 	u32 val, ctrl, num_ctrls;
@@ -694,11 +683,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	 * we should not program the ATU here.
 	 */
 	if (!pp->ops->rd_other_conf) {
-		/* Get iATU unroll support */
-		pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
-		dev_dbg(pci->dev, "iATU unroll: %s\n",
-			pci->iatu_unroll_enabled ? "enabled" : "disabled");
-
 		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
 					  PCIE_ATU_TYPE_MEM, pp->mem_base,
 					  pp->mem_bus_addr, pp->mem_size);
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 778c4f76a884..881f9c3786ae 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -92,16 +92,27 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
 {
 	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
+	void __iomem *base = pci->atu_base;
+	u32 val;
+	int ret;
+
+	ret = dw_pcie_read(base + offset + reg, 0x4, &val);
+	if (ret)
+		dev_err(pci->dev, "read DBI address failed\n");
 
-	return dw_pcie_readl_dbi(pci, offset + reg);
+	return val;
 }
 
 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
 				     u32 val)
 {
 	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
+	void __iomem *base = pci->atu_base;
+	int ret;
 
-	dw_pcie_writel_dbi(pci, offset + reg, val);
+	ret = dw_pcie_write(base + offset + reg, 0x4, val);
+	if (ret)
+		dev_err(pci->dev, "write DBI address failed\n");
 }
 
 static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
@@ -186,16 +197,27 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
 {
 	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
+	void __iomem *base = pci->atu_base;
+	u32 val;
+	int ret;
+
+	ret = dw_pcie_read(base + offset + reg, 0x4, &val);
+	if (ret)
+		dev_err(pci->dev, "read DBI address failed\n");
 
-	return dw_pcie_readl_dbi(pci, offset + reg);
+	return val;
 }
 
 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
 				     u32 val)
 {
 	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
+	void __iomem *base = pci->atu_base;
+	int ret;
 
-	dw_pcie_writel_dbi(pci, offset + reg, val);
+	ret = dw_pcie_write(base + offset + reg, 0x4, val);
+	if (ret)
+		dev_err(pci->dev, "write DBI address failed\n");
 }
 
 static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
@@ -339,6 +361,17 @@ int dw_pcie_link_up(struct dw_pcie *pci)
 		(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
 }
 
+static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
+{
+	u32 val;
+
+	val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
+	if (val == 0xffffffff)
+		return 1;
+
+	return 0;
+}
+
 void dw_pcie_setup(struct dw_pcie *pci)
 {
 	int ret;
@@ -347,6 +380,15 @@ void dw_pcie_setup(struct dw_pcie *pci)
 	struct device *dev = pci->dev;
 	struct device_node *np = dev->of_node;
 
+	if (pci->version >= 0x480A || (!pci->version &&
+				       dw_pcie_iatu_unroll_enabled(pci))) {
+		pci->iatu_unroll_enabled = true;
+		if (!pci->atu_base)
+			pci->atu_base = pci->dbi_base + PCIE_ATU_BASE_OFFSET;
+	}
+	dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
+		"enabled" : "disabled");
+
 	ret = of_property_read_u32(np, "num-lanes", &lanes);
 	if (ret)
 		lanes = 0;
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index a4d939536faf..b8ff37d1563b 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -85,6 +85,7 @@
  * iATU Unroll-specific register definitions
  * From 4.80 core version the address translation will be made by unroll
  */
+#define PCIE_ATU_BASE_OFFSET		(0x3 << 20)
 #define PCIE_ATU_UNR_REGION_CTRL1	0x00
 #define PCIE_ATU_UNR_REGION_CTRL2	0x04
 #define PCIE_ATU_UNR_LOWER_BASE		0x08
@@ -95,10 +96,10 @@
 
 /* Register address builder */
 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)	\
-			((0x3 << 20) | ((region) << 9))
+			((region) << 9)
 
-#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region)				\
-			((0x3 << 20) | ((region) << 9) | (0x1 << 8))
+#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region)		\
+			(((region) << 9) | (0x1 << 8))
 
 #define MAX_MSI_IRQS			256
 #define MAX_MSI_IRQS_PER_CTRL		32
@@ -220,11 +221,13 @@ struct dw_pcie {
 	struct device		*dev;
 	void __iomem		*dbi_base;
 	void __iomem		*dbi_base2;
+	void __iomem		*atu_base;
 	u32			num_viewport;
 	u8			iatu_unroll_enabled;
 	struct pcie_port	pp;
 	struct dw_pcie_ep	ep;
 	const struct dw_pcie_ops *ops;
+	unsigned int		version;
 };
 
 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
-- 
2.17.1


  parent reply	other threads:[~2018-09-21 10:24 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-21 10:21 [RFC PATCH 00/40] Cleanup pci-keystone.c and Add AM654 PCIe Support Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 01/40] PCI: keystone: Use quirk to limit MRRS for K2G Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 02/40] PCI: keystone: Use quirk to set MRRS for PCI host bridge Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 03/40] PCI: keystone: Move dw_pcie_setup_rc out of ks_pcie_establish_link() Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 04/40] PCI: keystone: Do not initiate link training multiple times Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 05/40] PCI: keystone: Remove unused argument from ks_dw_pcie_host_init() Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 06/40] PCI: keystone: Add start_link/stop_link dw_pcie_ops Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 07/40] PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 08/40] PCI: keystone: Cleanup MSI/legacy interrupt configuration and handling Kishon Vijay Abraham I
2021-07-03 21:01   ` Krzysztof Wilczyński
2021-07-05  8:21     ` Kishon Vijay Abraham I
2021-07-06 20:34       ` Krzysztof Wilczyński
2018-09-21 10:21 ` [RFC PATCH 09/40] PCI: keystone: Remove redundant platform_set_drvdata Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 10/40] PCI: keystone: Use uniform function naming convention Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 11/40] dt-bindings: PCI: keystone: Add bindings to get device control module Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 12/40] PCI: keystone: Use syscon APIs to get device id from " Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 13/40] dt-bindings: PCI: keystone: Add "reg-names" binding information Kishon Vijay Abraham I
     [not found]   ` <5baa1b0e.1c69fb81.4f57b.32f7@mx.google.com>
2018-11-02  7:19     ` Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 14/40] PCI: keystone: Use platform_get_resource_byname to get memory resources Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 15/40] PCI: keystone: Cleanup PHY handling Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 16/40] PCI: keystone: Invoke pm_runtime APIs to enable clock Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 17/40] PCI: keystone: Cleanup configuration space access Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 18/40] PCI: keystone: Get number of OB windows from DT and cleanup MEM space configuration Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 19/40] PCI: keystone: Cleanup set_dbi_mode and get_dbi_mode Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 20/40] PCI: keystone: Cleanup ks_pcie_link_up() Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 21/40] PCI: keystone: Add debug error message for all errors Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 22/40] PCI: keystone: Reorder header file in alphabetical order Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 23/40] PCI: keystone: Cleanup macros defined in pci-keystone.c Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 24/40] PCI: keystone: Move initializations to appropriate places Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 25/40] dt-bindings: PCI: Add dt-binding to configure PCIe mode Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 26/40] PCI: keystone: Explicitly set the " Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 27/40] dt-bindings: PCI: Document "atu" reg-names Kishon Vijay Abraham I
2018-09-21 10:21 ` Kishon Vijay Abraham I [this message]
2018-09-21 10:21 ` [RFC PATCH 29/40] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 30/40] dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 31/40] PCI: keystone: Add support for PCIe in AM654x Platforms Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 32/40] phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking reset callback Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 33/40] dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 34/40] phy: ti: Add a new SERDES driver for TI's " Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 35/40] ARM: dts: keystone-k2e: Use the updated binding to describe PCIe in k2e Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 36/40] arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its Kishon Vijay Abraham I
2018-09-21 19:42   ` Nishanth Menon
2018-09-21 10:21 ` [RFC PATCH 37/40] arm64: dts: k3-am6: Add Main System Control Module node Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 38/40] arm64: dts: k3-am6: Add mux-controller dt node required for muxing SERDES Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 39/40] arm64: dts: k3-am6: Add SERDES DT node Kishon Vijay Abraham I
2018-09-21 10:21 ` [RFC PATCH 40/40] arm64: dts: k3-am6: Add Root Complex PCIe dt node Kishon Vijay Abraham I
2018-10-12 13:47 ` [RFC PATCH 00/40] Cleanup pci-keystone.c and Add AM654 PCIe Support Lorenzo Pieralisi

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