* [PATCH 1/3] drm/exynos: drm_plane: Correct exynos_drm_plane_reset [not found] ` <CGME20180921122612eucas1p2f3e0b6cf2e15553bd4d7114722c2a217@eucas1p2.samsung.com> @ 2018-09-21 12:24 ` Christoph Manszewski 0 siblings, 0 replies; 3+ messages in thread From: Christoph Manszewski @ 2018-09-21 12:24 UTC (permalink / raw) To: dri-devel Cc: Christoph Manszewski, Inki Dae, Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, David Airlie, Kukjin Kim, Krzysztof Kozlowski, linux-arm-kernel, linux-samsung-soc, linux-kernel, Bartlomiej Zolnierkiewicz, Marek Szyprowski, Andrzej Hajda Make use of helper functions in exynos_drm_plane_reset in order to set all default values. Currently alpha isn't set during reset. Signed-off-by: Christoph Manszewski <c.manszewski@samsung.com> --- drivers/gpu/drm/exynos/exynos_drm_plane.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index dba29aec59b4..755ca0e9ead2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -131,16 +131,14 @@ static void exynos_drm_plane_reset(struct drm_plane *plane) if (plane->state) { exynos_state = to_exynos_plane_state(plane->state); - if (exynos_state->base.fb) - drm_framebuffer_put(exynos_state->base.fb); + __drm_atomic_helper_plane_destroy_state(plane->state); kfree(exynos_state); plane->state = NULL; } exynos_state = kzalloc(sizeof(*exynos_state), GFP_KERNEL); if (exynos_state) { - plane->state = &exynos_state->base; - plane->state->plane = plane; + __drm_atomic_helper_plane_reset(plane, &exynos_state->base); plane->state->zpos = exynos_plane->config->zpos; } } -- 2.7.4 ^ permalink raw reply related [flat|nested] 3+ messages in thread
[parent not found: <CGME20180921122617eucas1p1c167a8ea2aeca02fb3927aa3660ff540@eucas1p1.samsung.com>]
* [PATCH 2/3] drm/exynos: mixer: Make pixel blend mode configurable [not found] ` <CGME20180921122617eucas1p1c167a8ea2aeca02fb3927aa3660ff540@eucas1p1.samsung.com> @ 2018-09-21 12:24 ` Christoph Manszewski 0 siblings, 0 replies; 3+ messages in thread From: Christoph Manszewski @ 2018-09-21 12:24 UTC (permalink / raw) To: dri-devel Cc: Christoph Manszewski, Inki Dae, Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, David Airlie, Kukjin Kim, Krzysztof Kozlowski, linux-arm-kernel, linux-samsung-soc, linux-kernel, Bartlomiej Zolnierkiewicz, Marek Szyprowski, Andrzej Hajda The mixer hardware supports both premultiplied alpha and non-premultiplied alpha. Currently premultiplied alpha is default, make this configurable. Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20180913 using modetest. Signed-off-by: Christoph Manszewski <c.manszewski@samsung.com> --- drivers/gpu/drm/exynos/exynos_drm_drv.h | 1 + drivers/gpu/drm/exynos/exynos_drm_plane.c | 7 +++++++ drivers/gpu/drm/exynos/exynos_mixer.c | 27 +++++++++++++++++++++------ 3 files changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index c737c4bd2c19..1cb26d8c66f9 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -92,6 +92,7 @@ struct exynos_drm_plane { #define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1) #define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2) #define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3) +#define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4) /* * Exynos DRM plane configuration structure. diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 755ca0e9ead2..236408906f1f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -298,6 +298,10 @@ int exynos_plane_init(struct drm_device *dev, const struct exynos_drm_plane_config *config) { int err; + unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) | + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE); + struct drm_plane *plane = &exynos_plane->base; err = drm_universal_plane_init(dev, &exynos_plane->base, 1 << dev->mode_config.num_crtc, @@ -318,5 +322,8 @@ int exynos_plane_init(struct drm_device *dev, exynos_plane_attach_zpos_property(&exynos_plane->base, config->zpos, !(config->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS)); + if (config->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND) + drm_plane_create_blend_mode_property(plane, supported_modes); + return 0; } diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index ffbf4a950f69..721b63e92b28 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -131,14 +131,16 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { .pixel_formats = mixer_formats, .num_pixel_formats = ARRAY_SIZE(mixer_formats), .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | - EXYNOS_DRM_PLANE_CAP_ZPOS, + EXYNOS_DRM_PLANE_CAP_ZPOS | + EXYNOS_DRM_PLANE_CAP_PIX_BLEND, }, { .zpos = 1, .type = DRM_PLANE_TYPE_CURSOR, .pixel_formats = mixer_formats, .num_pixel_formats = ARRAY_SIZE(mixer_formats), .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | - EXYNOS_DRM_PLANE_CAP_ZPOS, + EXYNOS_DRM_PLANE_CAP_ZPOS | + EXYNOS_DRM_PLANE_CAP_PIX_BLEND, }, { .zpos = 2, .type = DRM_PLANE_TYPE_OVERLAY, @@ -309,15 +311,22 @@ static void vp_default_filter(struct mixer_context *ctx) } static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win, - bool alpha) + unsigned int pixel_alpha) { u32 val; val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ - if (alpha) { - /* blending based on pixel alpha */ + switch (pixel_alpha) { + case DRM_MODE_BLEND_PIXEL_NONE: + break; + case DRM_MODE_BLEND_COVERAGE: + val |= MXR_GRP_CFG_PIXEL_BLEND_EN; + break; + case DRM_MODE_BLEND_PREMULTI: + default: val |= MXR_GRP_CFG_BLEND_PRE_MUL; val |= MXR_GRP_CFG_PIXEL_BLEND_EN; + break; } mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win), val, MXR_GRP_CFG_MISC_MASK); @@ -553,10 +562,16 @@ static void mixer_graph_buffer(struct mixer_context *ctx, unsigned int win = plane->index; unsigned int x_ratio = 0, y_ratio = 0; unsigned int dst_x_offset, dst_y_offset; + unsigned int pixel_alpha; dma_addr_t dma_addr; unsigned int fmt; u32 val; + if (fb->format->has_alpha) + pixel_alpha = state->base.pixel_blend_mode; + else + pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; + switch (fb->format->format) { case DRM_FORMAT_XRGB4444: case DRM_FORMAT_ARGB4444: @@ -616,7 +631,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, mixer_reg_write(ctx, MXR_GRAPHIC_BASE(win), dma_addr); mixer_cfg_layer(ctx, win, priority, true); - mixer_cfg_gfx_blend(ctx, win, fb->format->has_alpha); + mixer_cfg_gfx_blend(ctx, win, pixel_alpha); /* layer update mandatory for mixer 16.0.33.0 */ if (ctx->mxr_ver == MXR_VER_16_0_33_0 || -- 2.7.4 ^ permalink raw reply related [flat|nested] 3+ messages in thread
[parent not found: <CGME20180921122619eucas1p24ab7008bf55e7dbe3eb01e5ad85fc401@eucas1p2.samsung.com>]
* [PATCH 3/3] drm/exynos: mixer: Make plane alpha configurable [not found] ` <CGME20180921122619eucas1p24ab7008bf55e7dbe3eb01e5ad85fc401@eucas1p2.samsung.com> @ 2018-09-21 12:24 ` Christoph Manszewski 0 siblings, 0 replies; 3+ messages in thread From: Christoph Manszewski @ 2018-09-21 12:24 UTC (permalink / raw) To: dri-devel Cc: Christoph Manszewski, Inki Dae, Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, David Airlie, Kukjin Kim, Krzysztof Kozlowski, linux-arm-kernel, linux-samsung-soc, linux-kernel, Bartlomiej Zolnierkiewicz, Marek Szyprowski, Andrzej Hajda The mixer hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20180913 using modetest. Signed-off-by: Christoph Manszewski <c.manszewski@samsung.com> --- drivers/gpu/drm/exynos/exynos_drm_drv.h | 1 + drivers/gpu/drm/exynos/exynos_drm_plane.c | 3 +++ drivers/gpu/drm/exynos/exynos_mixer.c | 37 ++++++++++++++++++------------- drivers/gpu/drm/exynos/regs-mixer.h | 5 ++++- 4 files changed, 30 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 1cb26d8c66f9..ec1d5bcac61a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -93,6 +93,7 @@ struct exynos_drm_plane { #define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2) #define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3) #define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4) +#define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5) /* * Exynos DRM plane configuration structure. diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 236408906f1f..df0508e0e49e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -325,5 +325,8 @@ int exynos_plane_init(struct drm_device *dev, if (config->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND) drm_plane_create_blend_mode_property(plane, supported_modes); + if (config->capabilities & EXYNOS_DRM_PLANE_CAP_WIN_BLEND) + drm_plane_create_alpha_property(plane); + return 0; } diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 721b63e92b28..e3a4ecbc503b 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -132,7 +132,8 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { .num_pixel_formats = ARRAY_SIZE(mixer_formats), .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | EXYNOS_DRM_PLANE_CAP_ZPOS | - EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_PIX_BLEND | + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, }, { .zpos = 1, .type = DRM_PLANE_TYPE_CURSOR, @@ -140,7 +141,8 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { .num_pixel_formats = ARRAY_SIZE(mixer_formats), .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | EXYNOS_DRM_PLANE_CAP_ZPOS | - EXYNOS_DRM_PLANE_CAP_PIX_BLEND, + EXYNOS_DRM_PLANE_CAP_PIX_BLEND | + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, }, { .zpos = 2, .type = DRM_PLANE_TYPE_OVERLAY, @@ -148,7 +150,8 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { .num_pixel_formats = ARRAY_SIZE(vp_formats), .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE | EXYNOS_DRM_PLANE_CAP_ZPOS | - EXYNOS_DRM_PLANE_CAP_TILE, + EXYNOS_DRM_PLANE_CAP_TILE | + EXYNOS_DRM_PLANE_CAP_WIN_BLEND, }, }; @@ -311,8 +314,9 @@ static void vp_default_filter(struct mixer_context *ctx) } static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win, - unsigned int pixel_alpha) + unsigned int pixel_alpha, unsigned int alpha) { + u32 win_alpha = alpha >> 8; u32 val; val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ @@ -328,21 +332,24 @@ static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win, val |= MXR_GRP_CFG_PIXEL_BLEND_EN; break; } + + if (alpha != DRM_BLEND_ALPHA_OPAQUE) { + val |= MXR_GRP_CFG_WIN_BLEND_EN; + val |= win_alpha; + } mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win), val, MXR_GRP_CFG_MISC_MASK); } -static void mixer_cfg_vp_blend(struct mixer_context *ctx) +static void mixer_cfg_vp_blend(struct mixer_context *ctx, unsigned int alpha) { - u32 val; + u32 win_alpha = alpha >> 8; + u32 val = 0; - /* - * No blending at the moment since the NV12/NV21 pixelformats don't - * have an alpha channel. However the mixer supports a global alpha - * value for a layer. Once this functionality is exposed, we can - * support blending of the video layer through this. - */ - val = 0; + if (alpha != DRM_BLEND_ALPHA_OPAQUE) { + val |= MXR_VID_CFG_BLEND_EN; + val |= win_alpha; + } mixer_reg_write(ctx, MXR_VIDEO_CFG, val); } @@ -538,7 +545,7 @@ static void vp_video_buffer(struct mixer_context *ctx, vp_reg_write(ctx, VP_BOT_C_PTR, chroma_addr[1]); mixer_cfg_layer(ctx, plane->index, priority, true); - mixer_cfg_vp_blend(ctx); + mixer_cfg_vp_blend(ctx, state->base.alpha); spin_unlock_irqrestore(&ctx->reg_slock, flags); @@ -631,7 +638,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, mixer_reg_write(ctx, MXR_GRAPHIC_BASE(win), dma_addr); mixer_cfg_layer(ctx, win, priority, true); - mixer_cfg_gfx_blend(ctx, win, pixel_alpha); + mixer_cfg_gfx_blend(ctx, win, pixel_alpha, state->base.alpha); /* layer update mandatory for mixer 16.0.33.0 */ if (ctx->mxr_ver == MXR_VER_16_0_33_0 || diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h index 189cfa2470a8..d2b8194a07bf 100644 --- a/drivers/gpu/drm/exynos/regs-mixer.h +++ b/drivers/gpu/drm/exynos/regs-mixer.h @@ -109,12 +109,15 @@ #define MXR_CFG_SCAN_HD (1 << 0) #define MXR_CFG_SCAN_MASK 0x47 +/* bits for MXR_VIDEO_CFG */ +#define MXR_VID_CFG_BLEND_EN (1 << 16) + /* bits for MXR_GRAPHICn_CFG */ #define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21) #define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20) #define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17) #define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16) -#define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20)) +#define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20) | 0xff) #define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8) #define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0) #define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0) -- 2.7.4 ^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-09-21 12:26 UTC | newest]
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[not found] <1537532678-4276-1-git-send-email-c.manszewski@samsung.com>
[not found] ` <CGME20180921122612eucas1p2f3e0b6cf2e15553bd4d7114722c2a217@eucas1p2.samsung.com>
2018-09-21 12:24 ` [PATCH 1/3] drm/exynos: drm_plane: Correct exynos_drm_plane_reset Christoph Manszewski
[not found] ` <CGME20180921122617eucas1p1c167a8ea2aeca02fb3927aa3660ff540@eucas1p1.samsung.com>
2018-09-21 12:24 ` [PATCH 2/3] drm/exynos: mixer: Make pixel blend mode configurable Christoph Manszewski
[not found] ` <CGME20180921122619eucas1p24ab7008bf55e7dbe3eb01e5ad85fc401@eucas1p2.samsung.com>
2018-09-21 12:24 ` [PATCH 3/3] drm/exynos: mixer: Make plane alpha configurable Christoph Manszewski
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