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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id y26-v6sm44579otk.64.2018.09.26.14.35.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 26 Sep 2018 14:35:10 -0700 (PDT) Date: Wed, 26 Sep 2018 16:35:09 -0500 From: Rob Herring To: Quentin Schulz Cc: alexandre.belloni@bootlin.com, ralf@linux-mips.org, paul.burton@mips.com, jhogan@kernel.org, mark.rutland@arm.com, davem@davemloft.net, kishon@ti.com, andrew@lunn.ch, f.fainelli@gmail.com, allan.nielsen@microchip.com, linux-mips@linux-mips.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com Subject: Re: [PATCH net-next v3 07/11] dt-bindings: phy: add DT binding for Microsemi Ocelot SerDes muxing Message-ID: <20180926213509.GA7454@bogus> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 14, 2018 at 10:16:05AM +0200, Quentin Schulz wrote: > Signed-off-by: Quentin Schulz > --- > Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt | 40 +++++++- > 1 file changed, 40 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt b/Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt > new file mode 100644 > index 0000000..2a88cc3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt > @@ -0,0 +1,40 @@ > +Microsemi Ocelot SerDes muxing driver > +------------------------------------- > + > +On Microsemi Ocelot, there is a handful of registers in HSIO address > +space for setting up the SerDes to switch port muxing. > + > +A SerDes X can be "muxed" to work with switch port Y or Z for example. > +One specific SerDes can also be used as a PCIe interface. > + > +Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one. > + > +There are two kinds of SerDes: SERDES1G supports 10/100Mbps in > +half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports > +10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode. > + > +Also, SERDES6G number (aka "macro") 0 is the only interface supporting > +QSGMII. > + > +Required properties: > + > +- compatible: should be "mscc,vsc7514-serdes" > +- #phy-cells : from the generic phy bindings, must be 2. > + The first number defines the input port to use for a given > + SerDes macro. The second defines the macro to use. They are > + defined in dt-bindings/phy/phy-ocelot-serdes.h You need to define what this is a child of. > + > +Example: > + > + serdes: serdes { > + compatible = "mscc,vsc7514-serdes"; > + #phy-cells = <2>; However, if there are no other resources associated with this, then you don't even need this child node. The parent can be a phy provider and provider of other functions too. > + }; > + > + ethernet { > + port1 { > + phy-handle = <&phy_foo>; > + /* Link SERDES1G_5 to port1 */ > + phys = <&serdes 1 SERDES1G_5>; > + }; > + }; > -- > git-series 0.9.1