From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC4B7C004D5 for ; Thu, 27 Sep 2018 07:44:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7D3562156D for ; Thu, 27 Sep 2018 07:44:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7D3562156D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727169AbeI0OBY (ORCPT ); Thu, 27 Sep 2018 10:01:24 -0400 Received: from mx.socionext.com ([202.248.49.38]:38036 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726659AbeI0OBX (ORCPT ); Thu, 27 Sep 2018 10:01:23 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 27 Sep 2018 16:44:28 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 7BEB46006C; Thu, 27 Sep 2018 16:44:28 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Thu, 27 Sep 2018 16:44:28 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id B78134039A; Thu, 27 Sep 2018 16:44:27 +0900 (JST) Received: from [127.0.0.1] (unknown [10.213.132.48]) by yuzu.css.socionext.com (Postfix) with ESMTP id 796EA120BA0; Thu, 27 Sep 2018 16:44:27 +0900 (JST) Date: Thu, 27 Sep 2018 16:44:26 +0900 From: Kunihiko Hayashi To: Lorenzo Pieralisi , Gustavo Pimentel Subject: Re: [PATCH v2 2/2] PCI: controller: dwc: add UniPhier PCIe host controller support Cc: Bjorn Helgaas , Rob Herring , Mark Rutland , Masahiro Yamada , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Masami Hiramatsu , Jassi Brar In-Reply-To: <20180926213135.A4B4.4A936039@socionext.com> References: <20180926213135.A4B4.4A936039@socionext.com> Message-Id: <20180927164426.ECD6.4A936039@socionext.com> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Mailer: Becky! ver. 2.70 [ja] Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lorenzo, Gustavo, On Wed, 26 Sep 2018 21:31:36 +0900 wrote: > Hi Lorenzo, Gustavo, > > Thank you for reviewing. > > On Tue, 25 Sep 2018 18:53:01 +0100 > Gustavo Pimentel wrote: > > > On 25/09/2018 17:14, Lorenzo Pieralisi wrote: > > > [+Gustavo, please have a look at INTX/MSI management] > > > > > > On Thu, Sep 06, 2018 at 06:40:32PM +0900, Kunihiko Hayashi wrote: > > >> This introduces specific glue layer for UniPhier platform to support > > >> PCIe host controller that is based on the DesignWare PCIe core, and > > >> this driver supports Root Complex (host) mode. > > > > > > Please read this thread and apply it to next versions: > > > > > > https://urldefense.proofpoint.com/v2/url?u=https-3A__marc.info_-3Fl-3Dlinux-2Dpci-26m-3D150905742808166-26w-3D2&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=bkWxpLoW-f-E3EdiDCCa0_h0PicsViasSlvIpzZvPxs&m=H8UNDDUGQnQnqfWr4CBios689dJcjxu4qeTTRGulLmU&s=CgcXc_2LThyOpW-4bCriJNo9H1lzROEdy_cG9p-Y5hU&e= > > I also found this thread in previous linux-pci, and I think it's helpful for me. > I'll check it carefully. [snip] > > >> + ret = devm_request_irq(dev, pp->irq, uniphier_pcie_irq_handler, > > >> + IRQF_SHARED, "pcie", priv); > > > > > > This is wrong, you should set-up a chained IRQ for INTX. > > > > > > I *think* that > > > > > > ks_pcie_setup_interrupts() > > > > > > is a good example to start with but I wonder whether it is worth > > > generalizing the INTX approach to designware as a whole as it was > > > done for MSIs. > > > > > > Thoughts ? > > > > From what I understood this is for legacy IRQ, right? > > Yes. For legacy IRQ. > > > Like you (Lorenzo) said there is 2 drivers (pci-keystone-dw.c and pci-dra7xx.c) > > that uses it and can be use as a template for handling this type of interrupts. > > > > We can try to pass some kind of generic INTX function to the DesignWare host > > library to handling this, but this will require some help from keystone and > > dra7xx maintainers, since my setup doesn't have legacy IRQ HW support. > > Now I think it's difficult to make a template for INTX function, > and at first, I'll try to re-write this part with reference to pci-keystone-dw.c. I understand that there are 2 types of interrupt and the drivers. One like pci-keystone-dw.c is: - there are 4 interrupts for legacy, - invoke handlers for each interrupt, and handle the interrupt, - call irq_set_chained_handler_and_data() to make a chain of the interrupts when initializing The other like pci-dra7xx.c is: - there is 1 IRQ for legacy as a parent, - check an interrupt factor register, and handle the interrupt correspond to the factor, - call request_irq() for the parent IRQ and irq_domain_add_linear() for the factor when initializing The pcie-uniphier.c is the same type as the latter (like pci-dra7xx.c). However, in pci-dra7xx.c, MSI and legacy IRQ share the same interrupt number, so the same handler is called and the handler divides these IRQs. (found in dra7xx_pcie_msi_irq_handler()) In pcie-uniphier.c, MSI and legacy IRQ are independent. Therefore it's necessary to prepare the handler for the legacy IRQ. I think that it's difficult to apply the way of pci-keystone-dw.c, and uniphier_pcie_irq_handler() and calling devm_request_irq() are still necessary to handle legacy IRQ. Thank you, --- Best Regards, Kunihiko Hayashi