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[108.223.40.66]) by smtp.gmail.com with ESMTPSA id i184-v6sm11943487pgc.9.2018.09.29.11.19.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Sep 2018 11:19:49 -0700 (PDT) Date: Sat, 29 Sep 2018 11:19:49 -0700 From: Guenter Roeck To: Christophe Leroy Cc: Wim Van Sebroeck , Radu Rendec , Rob Herring , Mark Rutland , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [v3,3/3] dt-bindings: watchdog: add mpc8xxx-wdt support Message-ID: <20180929181949.GA4420@roeck-us.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 17, 2018 at 06:22:53AM +0000, Christophe Leroy wrote: > Add description of DT bindings for mpc8xxx-wdt driver which > handles the CPU watchdog timer on the mpc83xx, mpc86xx and mpc8xx. > > Signed-off-by: Christophe Leroy > Reviewed-by: Rob Herring Reviewed-by: Guenter Roeck > --- > .../devicetree/bindings/watchdog/mpc8xxx-wdt.txt | 25 ++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > create mode 100644 Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt > > diff --git a/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt > new file mode 100644 > index 000000000000..e176face472a > --- /dev/null > +++ b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt > @@ -0,0 +1,25 @@ > +* Freescale mpc8xxx watchdog driver (For 83xx, 86xx and 8xx) > + > +Required properties: > +- compatible: Shall contain one of the following: > + "mpc83xx_wdt" for an mpc83xx > + "fsl,mpc8610-wdt" for an mpc86xx > + "fsl,mpc823-wdt" for an mpc8xx > +- reg: base physical address and length of the area hosting the > + watchdog registers. > + On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100> > + On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100> > + On the 8xx, "General System Interface Unit" area: <0x0 0x10> > + > +Optional properties: > +- reg: additional physical address and length (4) of location of the > + Reset Status Register (called RSTRSCR on the mpc86xx) > + On the 83xx, it is located at offset 0x910 > + On the 86xx, it is located at offset 0xe0094 > + On the 8xx, it is located at offset 0x288 > + > +Example: > + WDT: watchdog@0 { > + compatible = "fsl,mpc823-wdt"; > + reg = <0x0 0x10 0x288 0x4>; > + };