From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Vignesh R <vigneshr@ti.com>
Cc: Marek Vasut <marek.vasut@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Brian Norris <computersforpeace@gmail.com>,
Yogesh Gaur <yogeshnarayan.gaur@nxp.com>,
Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>,
<linux-mtd@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] mtd: spi-nor: Add Octal mode support for mt35xu512aba
Date: Thu, 4 Oct 2018 11:45:35 +0200 [thread overview]
Message-ID: <20181004114535.3a5dba05@bbrezillon> (raw)
In-Reply-To: <20181003165603.2579-2-vigneshr@ti.com>
On Wed, 3 Oct 2018 22:26:01 +0530
Vignesh R <vigneshr@ti.com> wrote:
> Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines. It
> supports read/write over 8 IO lines simulatenously. Add support for
> Octal read mode for Micron mt35xu512aba.
> Unfortunately, this flash is only complaint to SFDP JESD216B and does not
> seem to support newer JESD216C standard that provides auto detection of
> Octal mode capabilities and opcodes. Therefore, this capability is
> manually added using new SPI_NOR_OCTAL_READ flag.
>
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 11 ++++++++++-
> include/linux/mtd/spi-nor.h | 2 ++
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index aff5e6ff0b2c..4926e805a8cb 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -90,6 +90,7 @@ struct flash_info {
> #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
> #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
> #define USE_CLSR BIT(14) /* use CLSR command */
> +#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
Hm, we'll need to clarify what OCTAL means. I see at least 3 different
modes using 8 IO lines (1-1-8, 1-8-8 and 8-8-8) and all of them could
be qualified as "octal" modes.
So how about renaming this macro SPI_NOR_1_1_8_READ.
Also, I fear we'll soon run out of bits in ->flags if we keep adding
one flag per mode which is why I proposed a solution to let flash
chips tweak the flash parameters as they wish [1][2]. I'm not saying we
should do it now, but we should definitely plan for something like that.
[1]https://github.com/bbrezillon/linux/commit/9c672e4c85a91f1b0803c9c6e4b8f3aae5d79ffb
[2]https://github.com/bbrezillon/linux/commit/3a5515c8821314c06a3d84f9861aefe476bb711e
next prev parent reply other threads:[~2018-10-04 9:46 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-03 16:56 [PATCH 0/3] spi-nor: Add Octal SPI support Vignesh R
2018-10-03 16:56 ` [PATCH 1/3] mtd: spi-nor: Add Octal mode support for mt35xu512aba Vignesh R
2018-10-04 6:51 ` Yogesh Narayan Gaur
2018-10-04 7:39 ` Boris Brezillon
2018-10-04 8:47 ` Yogesh Narayan Gaur
2018-10-04 9:10 ` Boris Brezillon
2018-10-04 10:38 ` Vignesh R
2018-10-04 9:45 ` Boris Brezillon [this message]
2018-10-04 11:12 ` Vignesh R
2018-10-04 11:27 ` Boris Brezillon
2018-10-03 16:56 ` [PATCH 2/3] dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC Vignesh R
2018-10-15 19:11 ` Rob Herring
2018-10-03 16:56 ` [PATCH 3/3] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller Vignesh R
2018-12-10 8:45 ` Boris Brezillon
2018-12-10 11:19 ` Vignesh R
2018-12-10 11:28 ` Boris Brezillon
2018-10-03 19:20 ` [PATCH 0/3] spi-nor: Add Octal SPI support Boris Brezillon
2018-10-04 10:35 ` Vignesh R
2018-10-04 11:17 ` Boris Brezillon
2018-10-08 15:36 ` Vignesh R
2018-10-12 8:52 ` Boris Brezillon
2018-12-09 8:47 ` Vignesh R
2018-12-10 8:45 ` Boris Brezillon
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