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* [PATCH v4 00/10] Allwinner H6 USB support
@ 2018-10-04 12:28 Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 01/10] dt-bindings: phy: add binding for Allwinner H6 USB2 PHY Icenowy Zheng
                   ` (10 more replies)
  0 siblings, 11 replies; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

This patchset introduces support for the USB ports (both USB2 and USB3)
on the Allwinner H6 SoC.

The first 6 PATCHes are the USB2 part, and the latter 4 PATCHes are the
USB3 part.

PATCH 1, 2, 3, 7, 8 should go through the PHY tree, and the remaining
patches should go through the armsoc tree via sunxi tree.

Icenowy Zheng (10):
  dt-bindings: phy: add binding for Allwinner H6 USB2 PHY
  phy: sun4i-usb: add support for missing USB PHY index
  phy: sun4i-usb: add support for H6 USB2 PHY
  arm64: allwinner: dts: h6: add USB2-related device nodes
  arm64: allwinner: dts: h6: add USB Vbus regulator
  arm64: allwinner: dts: h6: enable USB2 on Pine H64
  dt-bindings: phy: add binding for Allwinner USB3 PHY
  phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
  arm64: allwinner: dts: h6: add USB3 device nodes
  arm64: allwinner: dts: h6: enable USB3 port on Pine H64

 .../devicetree/bindings/phy/sun4i-usb-phy.txt |   8 +-
 .../bindings/phy/sun50i-usb3-phy.txt          |  23 ++
 .../boot/dts/allwinner/sun50i-h6-pine-h64.dts |  46 ++++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 113 +++++++++
 drivers/phy/allwinner/Kconfig                 |  12 +
 drivers/phy/allwinner/Makefile                |   1 +
 drivers/phy/allwinner/phy-sun4i-usb.c         |  26 +-
 drivers/phy/allwinner/phy-sun50i-usb3.c       | 239 ++++++++++++++++++
 8 files changed, 463 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
 create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c

-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 01/10] dt-bindings: phy: add binding for Allwinner H6 USB2 PHY
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-10-05 20:53   ` Rob Herring
  2018-10-04 12:28 ` [PATCH v4 02/10] phy: sun4i-usb: add support for missing USB PHY index Icenowy Zheng
                   ` (9 subsequent siblings)
  10 siblings, 1 reply; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

The USB2.0 PHY on Allwinner H6 is similar to the ones on the ones on
older SoCs, but with holes in PHY number (USB1 and USB2 are missing, in
which USB1 is a USB3 PHY).

Add binding for the PHY.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
New patch in v4.

 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 07ca4ec4a745..f2e120af17f0 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -14,13 +14,14 @@ Required properties:
   * allwinner,sun8i-r40-usb-phy
   * allwinner,sun8i-v3s-usb-phy
   * allwinner,sun50i-a64-usb-phy
+  * allwinner,sun50i-h6-usb-phy
 - reg : a list of offset + length pairs
 - reg-names :
   * "phy_ctrl"
-  * "pmu0" for H3, V3s and A64
+  * "pmu0" for H3, V3s, A64 or H6
   * "pmu1"
   * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
-  * "pmu3" for sun8i-h3
+  * "pmu3" for sun8i-h3 or sun50i-h6
 - #phy-cells : from the generic phy bindings, must be 1
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names :
@@ -29,12 +30,13 @@ Required properties:
   * "usb0_phy", "usb1_phy" for sun8i
   * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
   * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
+  * "usb0_phy" and "usb3_phy" for sun50i-h6
 - resets : a list of phandle + reset specifier pairs
 - reset-names :
   * "usb0_reset"
   * "usb1_reset"
   * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
-  * "usb3_reset" for sun8i-h3
+  * "usb3_reset" for sun8i-h3 and sun50i-h6
 
 Optional properties:
 - usb0_id_det-gpios : gpio phandle for reading the otg id pin value
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 02/10] phy: sun4i-usb: add support for missing USB PHY index
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 01/10] dt-bindings: phy: add binding for Allwinner H6 USB2 PHY Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 03/10] phy: sun4i-usb: add support for H6 USB2 PHY Icenowy Zheng
                   ` (8 subsequent siblings)
  10 siblings, 0 replies; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

The new Allwinner H6 SoC's USB2 PHY has two holes -- USB1 (which is a
3.0 port with dedicated PHY) and USB2 (which doesn't exist at all).

Add support for this kind of missing USB PHY index.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
No changes in v4.

Changes in v3:
- Added Chen-Yu's Review tag.

 drivers/phy/allwinner/phy-sun4i-usb.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index d4dcd39b8d76..881078ff73f6 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -126,6 +126,7 @@ struct sun4i_usb_phy_cfg {
 	bool dedicated_clocks;
 	bool enable_pmu_unk1;
 	bool phy0_dual_route;
+	int missing_phys;
 };
 
 struct sun4i_usb_phy_data {
@@ -646,6 +647,9 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
 	if (args->args[0] >= data->cfg->num_phys)
 		return ERR_PTR(-ENODEV);
 
+	if (data->cfg->missing_phys & BIT(args->args[0]))
+		return ERR_PTR(-ENODEV);
+
 	return data->phys[args->args[0]].phy;
 }
 
@@ -741,6 +745,9 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
 		struct sun4i_usb_phy *phy = data->phys + i;
 		char name[16];
 
+		if (data->cfg->missing_phys & BIT(i))
+			continue;
+
 		snprintf(name, sizeof(name), "usb%d_vbus", i);
 		phy->vbus = devm_regulator_get_optional(dev, name);
 		if (IS_ERR(phy->vbus)) {
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 03/10] phy: sun4i-usb: add support for H6 USB2 PHY
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 01/10] dt-bindings: phy: add binding for Allwinner H6 USB2 PHY Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 02/10] phy: sun4i-usb: add support for missing USB PHY index Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-11-02  8:41   ` Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 04/10] arm64: allwinner: dts: h6: add USB2-related device nodes Icenowy Zheng
                   ` (7 subsequent siblings)
  10 siblings, 1 reply; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner SoCs,
with some USB0 quirk like A83T and PHY index 1/2 missing.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
No changes in v4.

Changes in v3:
- Added Chen-Yu's Review tag.

 drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 881078ff73f6..ae16854a770a 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -115,6 +115,7 @@ enum sun4i_usb_phy_type {
 	sun8i_r40_phy,
 	sun8i_v3s_phy,
 	sun50i_a64_phy,
+	sun50i_h6_phy,
 };
 
 struct sun4i_usb_phy_cfg {
@@ -295,7 +296,8 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 		return ret;
 	}
 
-	if (data->cfg->type == sun8i_a83t_phy) {
+	if (data->cfg->type == sun8i_a83t_phy ||
+	    data->cfg->type == sun50i_h6_phy) {
 		if (phy->index == 0) {
 			val = readl(data->base + data->cfg->phyctl_offset);
 			val |= PHY_CTL_VBUSVLDEXT;
@@ -344,7 +346,8 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 
 	if (phy->index == 0) {
-		if (data->cfg->type == sun8i_a83t_phy) {
+		if (data->cfg->type == sun8i_a83t_phy ||
+		    data->cfg->type == sun50i_h6_phy) {
 			void __iomem *phyctl = data->base +
 				data->cfg->phyctl_offset;
 
@@ -959,6 +962,17 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.phy0_dual_route = true,
 };
 
+static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
+	.num_phys = 4,
+	.type = sun50i_h6_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.enable_pmu_unk1 = true,
+	.phy0_dual_route = true,
+	.missing_phys = BIT(1) | BIT(2),
+};
+
 static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
@@ -972,6 +986,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy",
 	  .data = &sun50i_a64_cfg},
+	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 04/10] arm64: allwinner: dts: h6: add USB2-related device nodes
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
                   ` (2 preceding siblings ...)
  2018-10-04 12:28 ` [PATCH v4 03/10] phy: sun4i-usb: add support for H6 USB2 PHY Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-11-14 10:21   ` [linux-sunxi] " Chen-Yu Tsai
  2018-10-04 12:28 ` [PATCH v4 05/10] arm64: allwinner: dts: h6: add USB Vbus regulator Icenowy Zheng
                   ` (6 subsequent siblings)
  10 siblings, 1 reply; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

Allwinner H6 has two USB2 ports, one OTG and one host-only.

Add device tree nodes related to them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
No changes in v4.

Changes in v3:
- Removed the wrongly introduced usb3phy node.
- Added Chen-Yu's Review tag.

 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 81 ++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 040828d2e2c0..3d60af6cb3ae 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -258,6 +258,87 @@
 			status = "disabled";
 		};
 
+		usb2otg: usb@5100000 {
+			compatible = "allwinner,sun8i-a33-musb";
+			reg = <0x05100000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usb2phy 0>;
+			phy-names = "usb";
+			extcon = <&usb2phy 0>;
+			status = "disabled";
+		};
+
+		usb2phy: phy@5100400 {
+			compatible = "allwinner,sun50i-h6-usb-phy";
+			reg = <0x05100400 0x14>,
+			      <0x05101800 0x4>,
+			      <0x05311800 0x4>;
+			reg-names = "phy_ctrl",
+				    "pmu0",
+				    "pmu3";
+			clocks = <&ccu CLK_USB_PHY0>,
+				 <&ccu CLK_USB_PHY3>;
+			clock-names = "usb0_phy",
+				      "usb3_phy";
+			resets = <&ccu RST_USB_PHY0>,
+				 <&ccu RST_USB_PHY3>;
+			reset-names = "usb0_reset",
+				      "usb3_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
+		ehci0: usb@5101000 {
+			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
+			reg = <0x05101000 0x100>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_BUS_EHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>,
+				 <&ccu RST_BUS_EHCI0>;
+			status = "disabled";
+		};
+
+		ohci0: usb@5101400 {
+			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
+			reg = <0x05101400 0x100>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
+		ehci3: usb@5311000 {
+			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
+			reg = <0x05311000 0x100>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI3>,
+				 <&ccu CLK_BUS_EHCI3>,
+				 <&ccu CLK_USB_OHCI3>;
+			resets = <&ccu RST_BUS_OHCI3>,
+				 <&ccu RST_BUS_EHCI3>;
+			phys = <&usb2phy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci3: usb@5311400 {
+			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
+			reg = <0x05311400 0x100>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI3>,
+				 <&ccu CLK_USB_OHCI3>;
+			resets = <&ccu RST_BUS_OHCI3>;
+			phys = <&usb2phy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
 		r_ccu: clock@7010000 {
 			compatible = "allwinner,sun50i-h6-r-ccu";
 			reg = <0x07010000 0x400>;
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 05/10] arm64: allwinner: dts: h6: add USB Vbus regulator
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
                   ` (3 preceding siblings ...)
  2018-10-04 12:28 ` [PATCH v4 04/10] arm64: allwinner: dts: h6: add USB2-related device nodes Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 06/10] arm64: allwinner: dts: h6: enable USB2 on Pine H64 Icenowy Zheng
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

The 5V output of the USB ports on Pine H64 is controlled via a GPIO.

Add the USB Vbus regulator device tree node.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
No changes in v4.

Changes in v3:
- Added Chen-Yu's Review tag.

 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 48daec7f78ba..b181088d7500 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -39,6 +39,16 @@
 			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
 		};
 	};
+
+	reg_usb_vbus: vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		startup-delay-us = <100000>;
+		gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 };
 
 &mmc0 {
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 06/10] arm64: allwinner: dts: h6: enable USB2 on Pine H64
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
                   ` (4 preceding siblings ...)
  2018-10-04 12:28 ` [PATCH v4 05/10] arm64: allwinner: dts: h6: add USB Vbus regulator Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY Icenowy Zheng
                   ` (4 subsequent siblings)
  10 siblings, 0 replies; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

Pine H64 board has both the USB2 OTG pins and the USB2 host pins on H6
SoC wired out to USB Type-A ports.

Enable them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
No changes in v4.

Changes in v3:
- Added Chen-Yu's Review tag.

 .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index b181088d7500..2fde0ff3dd6b 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -51,6 +51,14 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
+&ehci3 {
+	status = "okay";
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
@@ -71,6 +79,14 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
+&ohci3 {
+	status = "okay";
+};
+
 &r_i2c {
 	status = "okay";
 
@@ -195,3 +211,14 @@
 	pinctrl-0 = <&uart0_ph_pins>;
 	status = "okay";
 };
+
+&usb2otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2phy {
+	usb0_vbus-supply = <&reg_usb_vbus>;
+	usb3_vbus-supply = <&reg_usb_vbus>;
+	status = "okay";
+};
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
                   ` (5 preceding siblings ...)
  2018-10-04 12:28 ` [PATCH v4 06/10] arm64: allwinner: dts: h6: enable USB2 on Pine H64 Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-10-05 20:58   ` Rob Herring
  2018-10-04 12:28 ` [PATCH v4 08/10] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC Icenowy Zheng
                   ` (3 subsequent siblings)
  10 siblings, 1 reply; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
external USB3 pins of the SoC.

Add a device tree binding for the PHY.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
Changes in v4:
- Changed Vbus regulator property to vbus-supply.

Changes in v3:
- Added Chen-Yu's Review tag.

No changes in v2, v1.

 .../bindings/phy/sun50i-usb3-phy.txt          | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
new file mode 100644
index 000000000000..9f49c6b8c7e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
@@ -0,0 +1,23 @@
+Allwinner sun50i USB3 PHY
+-----------------------
+
+Required properties:
+- compatible : should be one of
+  * allwinner,sun60i-h6-usb3-phy
+- reg : a list of offset + length pairs
+- #phy-cells : from the generic phy bindings, must be 0
+- clocks : phandle + clock specifier for the phy clock
+- resets : phandle + reset specifier for the phy reset
+
+Optional Properties:
+- vbus-supply : a phandle to a regulator that provides power to VBUS.
+
+Example:
+	usb3phy: phy@5210000 {
+		compatible = "allwinner,sun50i-h6-usb3-phy";
+		reg = <0x5210000 0x10000>;
+		clocks = <&ccu CLK_USB_PHY1>;
+		resets = <&ccu RST_USB_PHY1>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 08/10] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
                   ` (6 preceding siblings ...)
  2018-10-04 12:28 ` [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-11-14  4:57   ` Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 09/10] arm64: allwinner: dts: h6: add USB3 device nodes Icenowy Zheng
                   ` (2 subsequent siblings)
  10 siblings, 1 reply; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
controlled).

Add a driver for it.

The register operations in this driver is mainly extracted from the BSP
USB3 driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
Changes in v4:
- Added support for vbus-supply property.

Changes in v3:
- Dropped USB_SUPPORT dependency.
- Added Chen-Yu's Review tag.

No changes in v2, v1.

 drivers/phy/allwinner/Kconfig           |  12 ++
 drivers/phy/allwinner/Makefile          |   1 +
 drivers/phy/allwinner/phy-sun50i-usb3.c | 239 ++++++++++++++++++++++++
 3 files changed, 252 insertions(+)
 create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c

diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
index cdc1e745ba47..064096e6a4e5 100644
--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -29,3 +29,15 @@ config PHY_SUN9I_USB
 	  sun9i SoCs.
 
 	  This driver controls each individual USB 2 host PHY.
+
+config PHY_SUN50I_USB3
+	tristate "Allwinner sun50i SoC USB3 PHY driver"
+	depends on ARCH_SUNXI && HAS_IOMEM && OF
+	depends on RESET_CONTROLLER
+	select USB_COMMON
+	select GENERIC_PHY
+	help
+	  Enable this to support the USB3.0-capable transceiver that is
+	  part of some Allwinner sun50i SoCs.
+
+	  This driver controls each individual USB 2+3 host PHY combo.
diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
index 8605529c01a1..a8d01e9073c2 100644
--- a/drivers/phy/allwinner/Makefile
+++ b/drivers/phy/allwinner/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
+obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c
new file mode 100644
index 000000000000..70c299c01c3e
--- /dev/null
+++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Allwinner sun50i(H6) USB 3.0 phy driver
+ *
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on phy-sun9i-usb.c, which is:
+ *
+ * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on code from Allwinner BSP, which is:
+ *
+ * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/usb/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+
+/* Interface Status and Control Registers */
+#define SUNXI_ISCR			0x00
+#define SUNXI_PIPE_CLOCK_CONTROL	0x14
+#define SUNXI_PHY_TUNE_LOW		0x18
+#define SUNXI_PHY_TUNE_HIGH		0x1c
+#define SUNXI_PHY_EXTERNAL_CONTROL	0x20
+
+/* USB2.0 Interface Status and Control Register */
+#define SUNXI_ISCR_FORCE_VBUS		(3 << 12)
+
+/* PIPE Clock Control Register */
+#define SUNXI_PCC_PIPE_CLK_OPEN		(1 << 6)
+
+/* PHY External Control Register */
+#define SUNXI_PEC_EXTERN_VBUS		(3 << 1)
+#define SUNXI_PEC_SSC_EN		(1 << 24)
+#define SUNXI_PEC_REF_SSP_EN		(1 << 26)
+
+/* PHY Tune High Register */
+#define SUNXI_TX_DEEMPH_3P5DB(n)	((n) << 19)
+#define SUNXI_TX_DEEMPH_3P5DB_MASK	GENMASK(24, 19)
+#define SUNXI_TX_DEEMPH_6DB(n)		((n) << 13)
+#define SUNXI_TX_DEEMPH_6GB_MASK	GENMASK(18, 13)
+#define SUNXI_TX_SWING_FULL(n)		((n) << 6)
+#define SUNXI_TX_SWING_FULL_MASK	GENMASK(12, 6)
+#define SUNXI_LOS_BIAS(n)		((n) << 3)
+#define SUNXI_LOS_BIAS_MASK		GENMASK(5, 3)
+#define SUNXI_TXVBOOSTLVL(n)		((n) << 0)
+#define SUNXI_TXVBOOSTLVL_MASK		GENMASK(0, 2)
+
+struct sun50i_usb3_phy {
+	struct phy *phy;
+	void __iomem *regs;
+	struct reset_control *reset;
+	struct clk *clk;
+	bool regulator_on;
+	struct regulator *vbus;
+};
+
+static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
+{
+	u32 val;
+
+	val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
+	val |= SUNXI_PEC_EXTERN_VBUS;
+	val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
+	writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
+
+	val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
+	val |= SUNXI_PCC_PIPE_CLK_OPEN;
+	writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
+
+	val = readl(phy->regs + SUNXI_ISCR);
+	val |= SUNXI_ISCR_FORCE_VBUS;
+	writel(val, phy->regs + SUNXI_ISCR);
+
+	/*
+	 * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
+	 * registers are directly taken from the BSP USB3 driver from
+	 * Allwiner.
+	 */
+	writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
+
+	val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
+	val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
+		 SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
+		 SUNXI_TX_DEEMPH_3P5DB_MASK);
+	val |= SUNXI_TXVBOOSTLVL(0x7);
+	val |= SUNXI_LOS_BIAS(0x7);
+	val |= SUNXI_TX_SWING_FULL(0x55);
+	val |= SUNXI_TX_DEEMPH_6DB(0x20);
+	val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
+	writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
+}
+
+static int sun50i_usb3_phy_init(struct phy *_phy)
+{
+	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
+	int ret;
+
+	ret = clk_prepare_enable(phy->clk);
+	if (ret)
+		goto err_clk;
+
+	ret = reset_control_deassert(phy->reset);
+	if (ret)
+		goto err_reset;
+
+	sun50i_usb3_phy_open(phy);
+	return 0;
+
+err_reset:
+	clk_disable_unprepare(phy->clk);
+
+err_clk:
+	return ret;
+}
+
+static int sun50i_usb3_phy_exit(struct phy *_phy)
+{
+	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
+
+	reset_control_assert(phy->reset);
+	clk_disable_unprepare(phy->clk);
+
+	return 0;
+}
+
+static int sun50i_usb3_phy_power_on(struct phy *_phy)
+{
+	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
+	int ret;
+
+	if (!phy->vbus || phy->regulator_on)
+		return 0;
+
+	ret = regulator_enable(phy->vbus);
+	if (ret)
+		return ret;
+
+	phy->regulator_on = true;
+
+	return 0;
+}
+
+static int sun50i_usb3_phy_power_off(struct phy *_phy)
+{
+	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
+
+	if (!phy->vbus || !phy->regulator_on)
+		return 0;
+
+	regulator_disable(phy->vbus);
+	phy->regulator_on = false;
+
+	return 0;
+}
+
+static const struct phy_ops sun50i_usb3_phy_ops = {
+	.init		= sun50i_usb3_phy_init,
+	.exit		= sun50i_usb3_phy_exit,
+	.power_on	= sun50i_usb3_phy_power_on,
+	.power_off	= sun50i_usb3_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int sun50i_usb3_phy_probe(struct platform_device *pdev)
+{
+	struct sun50i_usb3_phy *phy;
+	struct device *dev = &pdev->dev;
+	struct phy_provider *phy_provider;
+	struct resource *res;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	phy->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(phy->clk)) {
+		dev_err(dev, "failed to get phy clock\n");
+		return PTR_ERR(phy->clk);
+	}
+
+	phy->reset = devm_reset_control_get(dev, NULL);
+	if (IS_ERR(phy->reset)) {
+		dev_err(dev, "failed to get reset control\n");
+		return PTR_ERR(phy->reset);
+	}
+
+	phy->vbus = devm_regulator_get_optional(dev, "vbus");
+	if (IS_ERR(phy->vbus)) {
+		if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
+			dev_err(dev, "Couldn't get vbus regulator... Deferring probe\n");
+			return -EPROBE_DEFER;
+		}
+
+		phy->vbus = NULL;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	phy->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(phy->regs))
+		return PTR_ERR(phy->regs);
+
+	phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops);
+	if (IS_ERR(phy->phy)) {
+		dev_err(dev, "failed to create PHY\n");
+		return PTR_ERR(phy->phy);
+	}
+
+	phy_set_drvdata(phy->phy, phy);
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id sun50i_usb3_phy_of_match[] = {
+	{ .compatible = "allwinner,sun50i-h6-usb3-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match);
+
+static struct platform_driver sun50i_usb3_phy_driver = {
+	.probe	= sun50i_usb3_phy_probe,
+	.driver = {
+		.of_match_table	= sun50i_usb3_phy_of_match,
+		.name  = "sun50i-usb3-phy",
+	}
+};
+module_platform_driver(sun50i_usb3_phy_driver);
+
+MODULE_DESCRIPTION("Allwinner sun50i USB 3.0 phy driver");
+MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
+MODULE_LICENSE("GPL");
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 09/10] arm64: allwinner: dts: h6: add USB3 device nodes
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
                   ` (7 preceding siblings ...)
  2018-10-04 12:28 ` [PATCH v4 08/10] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-10-04 12:28 ` [PATCH v4 10/10] arm64: allwinner: dts: h6: enable USB3 port on Pine H64 Icenowy Zheng
  2018-10-05 10:44 ` [linux-sunxi] [PATCH v4 00/10] Allwinner H6 USB support Chen-Yu Tsai
  10 siblings, 0 replies; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.

Add device tree nodes for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
No changes in v4.

Changes in v3:
- Changed the dwc3 clock according to the user manual.
- Added Chen-Yu's Review tag.

 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 32 ++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 3d60af6cb3ae..0a8b4845c0df 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -313,6 +313,38 @@
 			status = "disabled";
 		};
 
+		dwc3: dwc3@5200000 {
+			compatible = "snps,dwc3";
+			reg = <0x05200000 0x10000>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_XHCI>,
+				 <&ccu CLK_BUS_XHCI>,
+				 <&osc32k>;
+			clock-names = "ref", "bus_early", "suspend";
+			resets = <&ccu RST_BUS_XHCI>;
+			/*
+			 * The datasheet of the chip doesn't declare the
+			 * peripheral function, and there's no boards known
+			 * to have a USB Type-B port routed to the port.
+			 * In addition, no one has tested the peripheral
+			 * function yet.
+			 * So set the dr_mode to "host" in the DTSI file.
+			 */
+			dr_mode = "host";
+			phys = <&usb3phy>;
+			phy-names = "usb3-phy";
+			status = "disabled";
+		};
+
+		usb3phy: phy@5210000 {
+			compatible = "allwinner,sun50i-h6-usb3-phy";
+			reg = <0x5210000 0x10000>;
+			clocks = <&ccu CLK_USB_PHY1>;
+			resets = <&ccu RST_USB_PHY1>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		ehci3: usb@5311000 {
 			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 			reg = <0x05311000 0x100>;
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v4 10/10] arm64: allwinner: dts: h6: enable USB3 port on Pine H64
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
                   ` (8 preceding siblings ...)
  2018-10-04 12:28 ` [PATCH v4 09/10] arm64: allwinner: dts: h6: add USB3 device nodes Icenowy Zheng
@ 2018-10-04 12:28 ` Icenowy Zheng
  2018-10-05 10:44 ` [linux-sunxi] [PATCH v4 00/10] Allwinner H6 USB support Chen-Yu Tsai
  10 siblings, 0 replies; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-04 12:28 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

Pine H64 board have a USB3 port, which is connected to the USB3 pins of
the H6 SoC, and the 5V power supply is controlled via GPIO (shared with
the power USB ports).

Enable this port.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
No changes in v4.

Changes in v3:
- Added Chen-Yu's Review tag.

 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 2fde0ff3dd6b..dde1f692d252 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -51,6 +51,10 @@
 	};
 };
 
+&dwc3 {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -222,3 +226,8 @@
 	usb3_vbus-supply = <&reg_usb_vbus>;
 	status = "okay";
 };
+
+&usb3phy {
+	vbus-supply = <&reg_usb_vbus>;
+	status = "okay";
+};
-- 
2.18.0


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [linux-sunxi] [PATCH v4 00/10] Allwinner H6 USB support
  2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
                   ` (9 preceding siblings ...)
  2018-10-04 12:28 ` [PATCH v4 10/10] arm64: allwinner: dts: h6: enable USB3 port on Pine H64 Icenowy Zheng
@ 2018-10-05 10:44 ` Chen-Yu Tsai
  10 siblings, 0 replies; 27+ messages in thread
From: Chen-Yu Tsai @ 2018-10-05 10:44 UTC (permalink / raw)
  To: Icenowy Zheng
  Cc: Rob Herring, Maxime Ripard, Kishon Vijay Abraham I, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi

On Thu, Oct 4, 2018 at 8:29 PM Icenowy Zheng <icenowy@aosc.io> wrote:
>
> This patchset introduces support for the USB ports (both USB2 and USB3)
> on the Allwinner H6 SoC.
>
> The first 6 PATCHes are the USB2 part, and the latter 4 PATCHes are the
> USB3 part.
>
> PATCH 1, 2, 3, 7, 8 should go through the PHY tree, and the remaining
> patches should go through the armsoc tree via sunxi tree.
>
> Icenowy Zheng (10):
>   dt-bindings: phy: add binding for Allwinner H6 USB2 PHY
>   phy: sun4i-usb: add support for missing USB PHY index
>   phy: sun4i-usb: add support for H6 USB2 PHY
>   arm64: allwinner: dts: h6: add USB2-related device nodes
>   arm64: allwinner: dts: h6: add USB Vbus regulator
>   arm64: allwinner: dts: h6: enable USB2 on Pine H64
>   dt-bindings: phy: add binding for Allwinner USB3 PHY
>   phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
>   arm64: allwinner: dts: h6: add USB3 device nodes
>   arm64: allwinner: dts: h6: enable USB3 port on Pine H64

Tested-by: Chen-Yu Tsai <wens@csie.org>

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 01/10] dt-bindings: phy: add binding for Allwinner H6 USB2 PHY
  2018-10-04 12:28 ` [PATCH v4 01/10] dt-bindings: phy: add binding for Allwinner H6 USB2 PHY Icenowy Zheng
@ 2018-10-05 20:53   ` Rob Herring
  0 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2018-10-05 20:53 UTC (permalink / raw)
  To: Icenowy Zheng
  Cc: Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng

On Thu,  4 Oct 2018 20:28:46 +0800, Icenowy Zheng wrote:
> The USB2.0 PHY on Allwinner H6 is similar to the ones on the ones on
> older SoCs, but with holes in PHY number (USB1 and USB2 are missing, in
> which USB1 is a USB3 PHY).
> 
> Add binding for the PHY.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> New patch in v4.
> 
>  Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY
  2018-10-04 12:28 ` [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY Icenowy Zheng
@ 2018-10-05 20:58   ` Rob Herring
  2018-10-14  2:41     ` Icenowy Zheng
  0 siblings, 1 reply; 27+ messages in thread
From: Rob Herring @ 2018-10-05 20:58 UTC (permalink / raw)
  To: Icenowy Zheng
  Cc: Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi

On Thu, Oct 04, 2018 at 08:28:52PM +0800, Icenowy Zheng wrote:
> The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
> external USB3 pins of the SoC.
> 
> Add a device tree binding for the PHY.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> ---
> Changes in v4:
> - Changed Vbus regulator property to vbus-supply.
> 
> Changes in v3:
> - Added Chen-Yu's Review tag.
> 
> No changes in v2, v1.
> 
>  .../bindings/phy/sun50i-usb3-phy.txt          | 23 +++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> new file mode 100644
> index 000000000000..9f49c6b8c7e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> @@ -0,0 +1,23 @@
> +Allwinner sun50i USB3 PHY
> +-----------------------
> +
> +Required properties:
> +- compatible : should be one of
> +  * allwinner,sun60i-h6-usb3-phy
> +- reg : a list of offset + length pairs
> +- #phy-cells : from the generic phy bindings, must be 0
> +- clocks : phandle + clock specifier for the phy clock
> +- resets : phandle + reset specifier for the phy reset
> +
> +Optional Properties:
> +- vbus-supply : a phandle to a regulator that provides power to VBUS.

This belongs in a connector node as it is part of the connector unless 
the phy physically needs Vbus for power.

But others have done this, so all the phys can just be wrong...

> +
> +Example:
> +	usb3phy: phy@5210000 {

usb-phy@

> +		compatible = "allwinner,sun50i-h6-usb3-phy";
> +		reg = <0x5210000 0x10000>;
> +		clocks = <&ccu CLK_USB_PHY1>;
> +		resets = <&ccu RST_USB_PHY1>;
> +		#phy-cells = <0>;
> +		status = "disabled";

Don't show status in examples.

> +	};
> -- 
> 2.18.0
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY
  2018-10-05 20:58   ` Rob Herring
@ 2018-10-14  2:41     ` Icenowy Zheng
  2018-10-18 13:58       ` Rob Herring
  0 siblings, 1 reply; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-14  2:41 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree, Maxime Ripard, linux-sunxi, linux-kernel,
	Kishon Vijay Abraham I, Chen-Yu Tsai, linux-arm-kernel

在 2018-10-05五的 15:58 -0500,Rob Herring写道:
> On Thu, Oct 04, 2018 at 08:28:52PM +0800, Icenowy Zheng wrote:
> > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
> > external USB3 pins of the SoC.
> > 
> > Add a device tree binding for the PHY.
> > 
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > ---
> > Changes in v4:
> > - Changed Vbus regulator property to vbus-supply.
> > 
> > Changes in v3:
> > - Added Chen-Yu's Review tag.
> > 
> > No changes in v2, v1.
> > 
> >  .../bindings/phy/sun50i-usb3-phy.txt          | 23
> > +++++++++++++++++++
> >  1 file changed, 23 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/sun50i-
> > usb3-phy.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/sun50i-usb3-
> > phy.txt b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> > new file mode 100644
> > index 000000000000..9f49c6b8c7e7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> > @@ -0,0 +1,23 @@
> > +Allwinner sun50i USB3 PHY
> > +-----------------------
> > +
> > +Required properties:
> > +- compatible : should be one of
> > +  * allwinner,sun60i-h6-usb3-phy
> > +- reg : a list of offset + length pairs
> > +- #phy-cells : from the generic phy bindings, must be 0
> > +- clocks : phandle + clock specifier for the phy clock
> > +- resets : phandle + reset specifier for the phy reset
> > +
> > +Optional Properties:
> > +- vbus-supply : a phandle to a regulator that provides power to
> > VBUS.
> 
> This belongs in a connector node as it is part of the connector
> unless 
> the phy physically needs Vbus for power.
> 
> But others have done this, so all the phys can just be wrong...

How should we reference the connector?

Via OF graph or simply a property in PHY node?

> 
> > +
> > +Example:
> > +	usb3phy: phy@5210000 {
> 
> usb-phy@
> 
> > +		compatible = "allwinner,sun50i-h6-usb3-phy";
> > +		reg = <0x5210000 0x10000>;
> > +		clocks = <&ccu CLK_USB_PHY1>;
> > +		resets = <&ccu RST_USB_PHY1>;
> > +		#phy-cells = <0>;
> > +		status = "disabled";
> 
> Don't show status in examples.
> 
> > +	};
> > -- 
> > 2.18.0
> > 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY
  2018-10-14  2:41     ` Icenowy Zheng
@ 2018-10-18 13:58       ` Rob Herring
  2018-10-19  5:54         ` [linux-sunxi] " Icenowy Zheng
  2018-11-14  5:15         ` Icenowy Zheng
  0 siblings, 2 replies; 27+ messages in thread
From: Rob Herring @ 2018-10-18 13:58 UTC (permalink / raw)
  To: Icenowy Zheng
  Cc: devicetree, Maxime Ripard, linux-sunxi, linux-kernel,
	Kishon Vijay Abraham I, Chen-Yu Tsai,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On Sat, Oct 13, 2018 at 9:42 PM Icenowy Zheng <icenowy@aosc.io> wrote:
>
> 在 2018-10-05五的 15:58 -0500,Rob Herring写道:
> > On Thu, Oct 04, 2018 at 08:28:52PM +0800, Icenowy Zheng wrote:
> > > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
> > > external USB3 pins of the SoC.
> > >
> > > Add a device tree binding for the PHY.
> > >
> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > > ---
> > > Changes in v4:
> > > - Changed Vbus regulator property to vbus-supply.
> > >
> > > Changes in v3:
> > > - Added Chen-Yu's Review tag.
> > >
> > > No changes in v2, v1.
> > >
> > >  .../bindings/phy/sun50i-usb3-phy.txt          | 23
> > > +++++++++++++++++++
> > >  1 file changed, 23 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/phy/sun50i-
> > > usb3-phy.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/sun50i-usb3-
> > > phy.txt b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> > > new file mode 100644
> > > index 000000000000..9f49c6b8c7e7
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> > > @@ -0,0 +1,23 @@
> > > +Allwinner sun50i USB3 PHY
> > > +-----------------------
> > > +
> > > +Required properties:
> > > +- compatible : should be one of
> > > +  * allwinner,sun60i-h6-usb3-phy
> > > +- reg : a list of offset + length pairs
> > > +- #phy-cells : from the generic phy bindings, must be 0
> > > +- clocks : phandle + clock specifier for the phy clock
> > > +- resets : phandle + reset specifier for the phy reset
> > > +
> > > +Optional Properties:
> > > +- vbus-supply : a phandle to a regulator that provides power to
> > > VBUS.
> >
> > This belongs in a connector node as it is part of the connector
> > unless
> > the phy physically needs Vbus for power.
> >
> > But others have done this, so all the phys can just be wrong...
>
> How should we reference the connector?
>
> Via OF graph or simply a property in PHY node?

The connector is either a child of the controller or an OF graph from
the controller to the connector. The phy driver needs the controller
node and then it can walk the tree or graph to get the connector node.

Rob

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [linux-sunxi] Re: [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY
  2018-10-18 13:58       ` Rob Herring
@ 2018-10-19  5:54         ` Icenowy Zheng
  2018-11-14  5:15         ` Icenowy Zheng
  1 sibling, 0 replies; 27+ messages in thread
From: Icenowy Zheng @ 2018-10-19  5:54 UTC (permalink / raw)
  To: robh, Rob Herring
  Cc: devicetree, Maxime Ripard, linux-sunxi, linux-kernel,
	Kishon Vijay Abraham I, Chen-Yu Tsai,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE



于 2018年10月18日 GMT+08:00 下午9:58:25, Rob Herring <robh@kernel.org> 写到:
>On Sat, Oct 13, 2018 at 9:42 PM Icenowy Zheng <icenowy@aosc.io> wrote:
>>
>> 在 2018-10-05五的 15:58 -0500,Rob Herring写道:
>> > On Thu, Oct 04, 2018 at 08:28:52PM +0800, Icenowy Zheng wrote:
>> > > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
>> > > external USB3 pins of the SoC.
>> > >
>> > > Add a device tree binding for the PHY.
>> > >
>> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> > > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
>> > > ---
>> > > Changes in v4:
>> > > - Changed Vbus regulator property to vbus-supply.
>> > >
>> > > Changes in v3:
>> > > - Added Chen-Yu's Review tag.
>> > >
>> > > No changes in v2, v1.
>> > >
>> > >  .../bindings/phy/sun50i-usb3-phy.txt          | 23
>> > > +++++++++++++++++++
>> > >  1 file changed, 23 insertions(+)
>> > >  create mode 100644 Documentation/devicetree/bindings/phy/sun50i-
>> > > usb3-phy.txt
>> > >
>> > > diff --git a/Documentation/devicetree/bindings/phy/sun50i-usb3-
>> > > phy.txt
>b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
>> > > new file mode 100644
>> > > index 000000000000..9f49c6b8c7e7
>> > > --- /dev/null
>> > > +++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
>> > > @@ -0,0 +1,23 @@
>> > > +Allwinner sun50i USB3 PHY
>> > > +-----------------------
>> > > +
>> > > +Required properties:
>> > > +- compatible : should be one of
>> > > +  * allwinner,sun60i-h6-usb3-phy
>> > > +- reg : a list of offset + length pairs
>> > > +- #phy-cells : from the generic phy bindings, must be 0
>> > > +- clocks : phandle + clock specifier for the phy clock
>> > > +- resets : phandle + reset specifier for the phy reset
>> > > +
>> > > +Optional Properties:
>> > > +- vbus-supply : a phandle to a regulator that provides power to
>> > > VBUS.
>> >
>> > This belongs in a connector node as it is part of the connector
>> > unless
>> > the phy physically needs Vbus for power.
>> >
>> > But others have done this, so all the phys can just be wrong...
>>
>> How should we reference the connector?
>>
>> Via OF graph or simply a property in PHY node?
>
>The connector is either a child of the controller or an OF graph from
>the controller to the connector. The phy driver needs the controller
>node and then it can walk the tree or graph to get the connector node.

Why is it a child of the controller?

I think on hardware the connector is connected to the PHY via USB, and PHY is
connected to the controller via ULPI/UTMI and PIPE, so the connector node
should link to PHY in some way, not to controller.

For Allwinner USB3 PHY I prefer to use child node now, as it's a simple
single-port PHY, and there seems to be no reserved space for multi-port.

>
>Rob

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 03/10] phy: sun4i-usb: add support for H6 USB2 PHY
  2018-10-04 12:28 ` [PATCH v4 03/10] phy: sun4i-usb: add support for H6 USB2 PHY Icenowy Zheng
@ 2018-11-02  8:41   ` Icenowy Zheng
  2018-11-02  8:43     ` Kishon Vijay Abraham I
  0 siblings, 1 reply; 27+ messages in thread
From: Icenowy Zheng @ 2018-11-02  8:41 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-sunxi, linux-kernel, linux-arm-kernel

在 2018-10-04四的 20:28 +0800,Icenowy Zheng写道:
> The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner
> SoCs,
> with some USB0 quirk like A83T and PHY index 1/2 missing.
> 
> Add support for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Excuse me.

Kishon, could you check PATCH 1~3 and queue them?

Even if USB3 support is pending, USB2 support will still be useful, and
they're independent.

> ---
> No changes in v4.
> 
> Changes in v3:
> - Added Chen-Yu's Review tag.
> 
>  drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> b/drivers/phy/allwinner/phy-sun4i-usb.c
> index 881078ff73f6..ae16854a770a 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -115,6 +115,7 @@ enum sun4i_usb_phy_type {
>  	sun8i_r40_phy,
>  	sun8i_v3s_phy,
>  	sun50i_a64_phy,
> +	sun50i_h6_phy,
>  };
>  
>  struct sun4i_usb_phy_cfg {
> @@ -295,7 +296,8 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>  		return ret;
>  	}
>  
> -	if (data->cfg->type == sun8i_a83t_phy) {
> +	if (data->cfg->type == sun8i_a83t_phy ||
> +	    data->cfg->type == sun50i_h6_phy) {
>  		if (phy->index == 0) {
>  			val = readl(data->base + data->cfg-
> >phyctl_offset);
>  			val |= PHY_CTL_VBUSVLDEXT;
> @@ -344,7 +346,8 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
>  	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
>  
>  	if (phy->index == 0) {
> -		if (data->cfg->type == sun8i_a83t_phy) {
> +		if (data->cfg->type == sun8i_a83t_phy ||
> +		    data->cfg->type == sun50i_h6_phy) {
>  			void __iomem *phyctl = data->base +
>  				data->cfg->phyctl_offset;
>  
> @@ -959,6 +962,17 @@ static const struct sun4i_usb_phy_cfg
> sun50i_a64_cfg = {
>  	.phy0_dual_route = true,
>  };
>  
> +static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
> +	.num_phys = 4,
> +	.type = sun50i_h6_phy,
> +	.disc_thresh = 3,
> +	.phyctl_offset = REG_PHYCTL_A33,
> +	.dedicated_clocks = true,
> +	.enable_pmu_unk1 = true,
> +	.phy0_dual_route = true,
> +	.missing_phys = BIT(1) | BIT(2),
> +};
> +
>  static const struct of_device_id sun4i_usb_phy_of_match[] = {
>  	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data =
> &sun4i_a10_cfg },
>  	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data =
> &sun5i_a13_cfg },
> @@ -972,6 +986,7 @@ static const struct of_device_id
> sun4i_usb_phy_of_match[] = {
>  	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data =
> &sun8i_v3s_cfg },
>  	{ .compatible = "allwinner,sun50i-a64-usb-phy",
>  	  .data = &sun50i_a64_cfg},
> +	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data =
> &sun50i_h6_cfg },
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 03/10] phy: sun4i-usb: add support for H6 USB2 PHY
  2018-11-02  8:41   ` Icenowy Zheng
@ 2018-11-02  8:43     ` Kishon Vijay Abraham I
  2018-11-09 14:04       ` Icenowy Zheng
  0 siblings, 1 reply; 27+ messages in thread
From: Kishon Vijay Abraham I @ 2018-11-02  8:43 UTC (permalink / raw)
  To: Icenowy Zheng, Rob Herring, Maxime Ripard, Chen-Yu Tsai
  Cc: devicetree, linux-sunxi, linux-kernel, linux-arm-kernel



On 02/11/18 2:11 PM, Icenowy Zheng wrote:
> 在 2018-10-04四的 20:28 +0800,Icenowy Zheng写道:
>> The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner
>> SoCs,
>> with some USB0 quirk like A83T and PHY index 1/2 missing.
>>
>> Add support for it.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> 
> Excuse me.
> 
> Kishon, could you check PATCH 1~3 and queue them?
> 
> Even if USB3 support is pending, USB2 support will still be useful, and
> they're independent.

I'll queue once -rc1 is tagged.

Thanks
Kishon

> 
>> ---
>> No changes in v4.
>>
>> Changes in v3:
>> - Added Chen-Yu's Review tag.
>>
>>  drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++--
>>  1 file changed, 17 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
>> b/drivers/phy/allwinner/phy-sun4i-usb.c
>> index 881078ff73f6..ae16854a770a 100644
>> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
>> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
>> @@ -115,6 +115,7 @@ enum sun4i_usb_phy_type {
>>  	sun8i_r40_phy,
>>  	sun8i_v3s_phy,
>>  	sun50i_a64_phy,
>> +	sun50i_h6_phy,
>>  };
>>  
>>  struct sun4i_usb_phy_cfg {
>> @@ -295,7 +296,8 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>>  		return ret;
>>  	}
>>  
>> -	if (data->cfg->type == sun8i_a83t_phy) {
>> +	if (data->cfg->type == sun8i_a83t_phy ||
>> +	    data->cfg->type == sun50i_h6_phy) {
>>  		if (phy->index == 0) {
>>  			val = readl(data->base + data->cfg-
>>> phyctl_offset);
>>  			val |= PHY_CTL_VBUSVLDEXT;
>> @@ -344,7 +346,8 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
>>  	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
>>  
>>  	if (phy->index == 0) {
>> -		if (data->cfg->type == sun8i_a83t_phy) {
>> +		if (data->cfg->type == sun8i_a83t_phy ||
>> +		    data->cfg->type == sun50i_h6_phy) {
>>  			void __iomem *phyctl = data->base +
>>  				data->cfg->phyctl_offset;
>>  
>> @@ -959,6 +962,17 @@ static const struct sun4i_usb_phy_cfg
>> sun50i_a64_cfg = {
>>  	.phy0_dual_route = true,
>>  };
>>  
>> +static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
>> +	.num_phys = 4,
>> +	.type = sun50i_h6_phy,
>> +	.disc_thresh = 3,
>> +	.phyctl_offset = REG_PHYCTL_A33,
>> +	.dedicated_clocks = true,
>> +	.enable_pmu_unk1 = true,
>> +	.phy0_dual_route = true,
>> +	.missing_phys = BIT(1) | BIT(2),
>> +};
>> +
>>  static const struct of_device_id sun4i_usb_phy_of_match[] = {
>>  	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data =
>> &sun4i_a10_cfg },
>>  	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data =
>> &sun5i_a13_cfg },
>> @@ -972,6 +986,7 @@ static const struct of_device_id
>> sun4i_usb_phy_of_match[] = {
>>  	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data =
>> &sun8i_v3s_cfg },
>>  	{ .compatible = "allwinner,sun50i-a64-usb-phy",
>>  	  .data = &sun50i_a64_cfg},
>> +	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data =
>> &sun50i_h6_cfg },
>>  	{ },
>>  };
>>  MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 03/10] phy: sun4i-usb: add support for H6 USB2 PHY
  2018-11-02  8:43     ` Kishon Vijay Abraham I
@ 2018-11-09 14:04       ` Icenowy Zheng
  0 siblings, 0 replies; 27+ messages in thread
From: Icenowy Zheng @ 2018-11-09 14:04 UTC (permalink / raw)
  To: Kishon Vijay Abraham I, Rob Herring, Maxime Ripard, Chen-Yu Tsai
  Cc: devicetree, linux-sunxi, linux-kernel, linux-arm-kernel

在 2018-11-02五的 14:13 +0530,Kishon Vijay Abraham I写道:
> 
> On 02/11/18 2:11 PM, Icenowy Zheng wrote:
> > 在 2018-10-04四的 20:28 +0800,Icenowy Zheng写道:
> > > The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner
> > > SoCs,
> > > with some USB0 quirk like A83T and PHY index 1/2 missing.
> > > 
> > > Add support for it.
> > > 
> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > 
> > Excuse me.
> > 
> > Kishon, could you check PATCH 1~3 and queue them?
> > 
> > Even if USB3 support is pending, USB2 support will still be useful,
> > and
> > they're independent.
> 
> I'll queue once -rc1 is tagged.

Ping.

4.20-rc1 is out now.

> 
> Thanks
> Kishon
> 
> > > ---
> > > No changes in v4.
> > > 
> > > Changes in v3:
> > > - Added Chen-Yu's Review tag.
> > > 
> > >  drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++--
> > >  1 file changed, 17 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > b/drivers/phy/allwinner/phy-sun4i-usb.c
> > > index 881078ff73f6..ae16854a770a 100644
> > > --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> > > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> > > @@ -115,6 +115,7 @@ enum sun4i_usb_phy_type {
> > >  	sun8i_r40_phy,
> > >  	sun8i_v3s_phy,
> > >  	sun50i_a64_phy,
> > > +	sun50i_h6_phy,
> > >  };
> > >  
> > >  struct sun4i_usb_phy_cfg {
> > > @@ -295,7 +296,8 @@ static int sun4i_usb_phy_init(struct phy
> > > *_phy)
> > >  		return ret;
> > >  	}
> > >  
> > > -	if (data->cfg->type == sun8i_a83t_phy) {
> > > +	if (data->cfg->type == sun8i_a83t_phy ||
> > > +	    data->cfg->type == sun50i_h6_phy) {
> > >  		if (phy->index == 0) {
> > >  			val = readl(data->base + data->cfg-
> > > > phyctl_offset);
> > >  			val |= PHY_CTL_VBUSVLDEXT;
> > > @@ -344,7 +346,8 @@ static int sun4i_usb_phy_exit(struct phy
> > > *_phy)
> > >  	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
> > >  
> > >  	if (phy->index == 0) {
> > > -		if (data->cfg->type == sun8i_a83t_phy) {
> > > +		if (data->cfg->type == sun8i_a83t_phy ||
> > > +		    data->cfg->type == sun50i_h6_phy) {
> > >  			void __iomem *phyctl = data->base +
> > >  				data->cfg->phyctl_offset;
> > >  
> > > @@ -959,6 +962,17 @@ static const struct sun4i_usb_phy_cfg
> > > sun50i_a64_cfg = {
> > >  	.phy0_dual_route = true,
> > >  };
> > >  
> > > +static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
> > > +	.num_phys = 4,
> > > +	.type = sun50i_h6_phy,
> > > +	.disc_thresh = 3,
> > > +	.phyctl_offset = REG_PHYCTL_A33,
> > > +	.dedicated_clocks = true,
> > > +	.enable_pmu_unk1 = true,
> > > +	.phy0_dual_route = true,
> > > +	.missing_phys = BIT(1) | BIT(2),
> > > +};
> > > +
> > >  static const struct of_device_id sun4i_usb_phy_of_match[] = {
> > >  	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data =
> > > &sun4i_a10_cfg },
> > >  	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data =
> > > &sun5i_a13_cfg },
> > > @@ -972,6 +986,7 @@ static const struct of_device_id
> > > sun4i_usb_phy_of_match[] = {
> > >  	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data =
> > > &sun8i_v3s_cfg },
> > >  	{ .compatible = "allwinner,sun50i-a64-usb-phy",
> > >  	  .data = &sun50i_a64_cfg},
> > > +	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data =
> > > &sun50i_h6_cfg },
> > >  	{ },
> > >  };
> > >  MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 08/10] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
  2018-10-04 12:28 ` [PATCH v4 08/10] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC Icenowy Zheng
@ 2018-11-14  4:57   ` Icenowy Zheng
  2018-11-20  5:11     ` Kishon Vijay Abraham I
  0 siblings, 1 reply; 27+ messages in thread
From: Icenowy Zheng @ 2018-11-14  4:57 UTC (permalink / raw)
  To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
  Cc: devicetree, linux-sunxi, linux-kernel, linux-arm-kernel

在 2018-10-04四的 20:28 +0800,Icenowy Zheng写道:
> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> controlled).
> 
> Add a driver for it.
> 
> The register operations in this driver is mainly extracted from the
> BSP
> USB3 driver.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Kishon, I see this patch is picked to linux-next, however this patch is
not in the stage that can be picked, because for the Vbus of USB3 PHY
Rob Herring still have some problems.

Could you remove PATCH 7 and 8 in this patchset now?

Thanks!

> ---
> Changes in v4:
> - Added support for vbus-supply property.
> 
> Changes in v3:
> - Dropped USB_SUPPORT dependency.
> - Added Chen-Yu's Review tag.
> 
> No changes in v2, v1.
> 
>  drivers/phy/allwinner/Kconfig           |  12 ++
>  drivers/phy/allwinner/Makefile          |   1 +
>  drivers/phy/allwinner/phy-sun50i-usb3.c | 239
> ++++++++++++++++++++++++
>  3 files changed, 252 insertions(+)
>  create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c
> 
> diff --git a/drivers/phy/allwinner/Kconfig
> b/drivers/phy/allwinner/Kconfig
> index cdc1e745ba47..064096e6a4e5 100644
> --- a/drivers/phy/allwinner/Kconfig
> +++ b/drivers/phy/allwinner/Kconfig
> @@ -29,3 +29,15 @@ config PHY_SUN9I_USB
>  	  sun9i SoCs.
>  
>  	  This driver controls each individual USB 2 host PHY.
> +
> +config PHY_SUN50I_USB3
> +	tristate "Allwinner sun50i SoC USB3 PHY driver"
> +	depends on ARCH_SUNXI && HAS_IOMEM && OF
> +	depends on RESET_CONTROLLER
> +	select USB_COMMON
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the USB3.0-capable transceiver that is
> +	  part of some Allwinner sun50i SoCs.
> +
> +	  This driver controls each individual USB 2+3 host PHY combo.
> diff --git a/drivers/phy/allwinner/Makefile
> b/drivers/phy/allwinner/Makefile
> index 8605529c01a1..a8d01e9073c2 100644
> --- a/drivers/phy/allwinner/Makefile
> +++ b/drivers/phy/allwinner/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
>  obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
> +obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
> diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c
> b/drivers/phy/allwinner/phy-sun50i-usb3.c
> new file mode 100644
> index 000000000000..70c299c01c3e
> --- /dev/null
> +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
> @@ -0,0 +1,239 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Allwinner sun50i(H6) USB 3.0 phy driver
> + *
> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> + *
> + * Based on phy-sun9i-usb.c, which is:
> + *
> + * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
> + *
> + * Based on code from Allwinner BSP, which is:
> + *
> + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/usb/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +
> +/* Interface Status and Control Registers */
> +#define SUNXI_ISCR			0x00
> +#define SUNXI_PIPE_CLOCK_CONTROL	0x14
> +#define SUNXI_PHY_TUNE_LOW		0x18
> +#define SUNXI_PHY_TUNE_HIGH		0x1c
> +#define SUNXI_PHY_EXTERNAL_CONTROL	0x20
> +
> +/* USB2.0 Interface Status and Control Register */
> +#define SUNXI_ISCR_FORCE_VBUS		(3 << 12)
> +
> +/* PIPE Clock Control Register */
> +#define SUNXI_PCC_PIPE_CLK_OPEN		(1 << 6)
> +
> +/* PHY External Control Register */
> +#define SUNXI_PEC_EXTERN_VBUS		(3 << 1)
> +#define SUNXI_PEC_SSC_EN		(1 << 24)
> +#define SUNXI_PEC_REF_SSP_EN		(1 << 26)
> +
> +/* PHY Tune High Register */
> +#define SUNXI_TX_DEEMPH_3P5DB(n)	((n) << 19)
> +#define SUNXI_TX_DEEMPH_3P5DB_MASK	GENMASK(24, 19)
> +#define SUNXI_TX_DEEMPH_6DB(n)		((n) << 13)
> +#define SUNXI_TX_DEEMPH_6GB_MASK	GENMASK(18, 13)
> +#define SUNXI_TX_SWING_FULL(n)		((n) << 6)
> +#define SUNXI_TX_SWING_FULL_MASK	GENMASK(12, 6)
> +#define SUNXI_LOS_BIAS(n)		((n) << 3)
> +#define SUNXI_LOS_BIAS_MASK		GENMASK(5, 3)
> +#define SUNXI_TXVBOOSTLVL(n)		((n) << 0)
> +#define SUNXI_TXVBOOSTLVL_MASK		GENMASK(0, 2)
> +
> +struct sun50i_usb3_phy {
> +	struct phy *phy;
> +	void __iomem *regs;
> +	struct reset_control *reset;
> +	struct clk *clk;
> +	bool regulator_on;
> +	struct regulator *vbus;
> +};
> +
> +static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
> +{
> +	u32 val;
> +
> +	val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
> +	val |= SUNXI_PEC_EXTERN_VBUS;
> +	val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
> +	writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
> +
> +	val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
> +	val |= SUNXI_PCC_PIPE_CLK_OPEN;
> +	writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
> +
> +	val = readl(phy->regs + SUNXI_ISCR);
> +	val |= SUNXI_ISCR_FORCE_VBUS;
> +	writel(val, phy->regs + SUNXI_ISCR);
> +
> +	/*
> +	 * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
> +	 * registers are directly taken from the BSP USB3 driver from
> +	 * Allwiner.
> +	 */
> +	writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
> +
> +	val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
> +	val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
> +		 SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
> +		 SUNXI_TX_DEEMPH_3P5DB_MASK);
> +	val |= SUNXI_TXVBOOSTLVL(0x7);
> +	val |= SUNXI_LOS_BIAS(0x7);
> +	val |= SUNXI_TX_SWING_FULL(0x55);
> +	val |= SUNXI_TX_DEEMPH_6DB(0x20);
> +	val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
> +	writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
> +}
> +
> +static int sun50i_usb3_phy_init(struct phy *_phy)
> +{
> +	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
> +	int ret;
> +
> +	ret = clk_prepare_enable(phy->clk);
> +	if (ret)
> +		goto err_clk;
> +
> +	ret = reset_control_deassert(phy->reset);
> +	if (ret)
> +		goto err_reset;
> +
> +	sun50i_usb3_phy_open(phy);
> +	return 0;
> +
> +err_reset:
> +	clk_disable_unprepare(phy->clk);
> +
> +err_clk:
> +	return ret;
> +}
> +
> +static int sun50i_usb3_phy_exit(struct phy *_phy)
> +{
> +	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
> +
> +	reset_control_assert(phy->reset);
> +	clk_disable_unprepare(phy->clk);
> +
> +	return 0;
> +}
> +
> +static int sun50i_usb3_phy_power_on(struct phy *_phy)
> +{
> +	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
> +	int ret;
> +
> +	if (!phy->vbus || phy->regulator_on)
> +		return 0;
> +
> +	ret = regulator_enable(phy->vbus);
> +	if (ret)
> +		return ret;
> +
> +	phy->regulator_on = true;
> +
> +	return 0;
> +}
> +
> +static int sun50i_usb3_phy_power_off(struct phy *_phy)
> +{
> +	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
> +
> +	if (!phy->vbus || !phy->regulator_on)
> +		return 0;
> +
> +	regulator_disable(phy->vbus);
> +	phy->regulator_on = false;
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops sun50i_usb3_phy_ops = {
> +	.init		= sun50i_usb3_phy_init,
> +	.exit		= sun50i_usb3_phy_exit,
> +	.power_on	= sun50i_usb3_phy_power_on,
> +	.power_off	= sun50i_usb3_phy_power_off,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static int sun50i_usb3_phy_probe(struct platform_device *pdev)
> +{
> +	struct sun50i_usb3_phy *phy;
> +	struct device *dev = &pdev->dev;
> +	struct phy_provider *phy_provider;
> +	struct resource *res;
> +
> +	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> +	if (!phy)
> +		return -ENOMEM;
> +
> +	phy->clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(phy->clk)) {
> +		dev_err(dev, "failed to get phy clock\n");
> +		return PTR_ERR(phy->clk);
> +	}
> +
> +	phy->reset = devm_reset_control_get(dev, NULL);
> +	if (IS_ERR(phy->reset)) {
> +		dev_err(dev, "failed to get reset control\n");
> +		return PTR_ERR(phy->reset);
> +	}
> +
> +	phy->vbus = devm_regulator_get_optional(dev, "vbus");
> +	if (IS_ERR(phy->vbus)) {
> +		if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
> +			dev_err(dev, "Couldn't get vbus regulator...
> Deferring probe\n");
> +			return -EPROBE_DEFER;
> +		}
> +
> +		phy->vbus = NULL;
> +	}
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	phy->regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(phy->regs))
> +		return PTR_ERR(phy->regs);
> +
> +	phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops);
> +	if (IS_ERR(phy->phy)) {
> +		dev_err(dev, "failed to create PHY\n");
> +		return PTR_ERR(phy->phy);
> +	}
> +
> +	phy_set_drvdata(phy->phy, phy);
> +	phy_provider = devm_of_phy_provider_register(dev,
> of_phy_simple_xlate);
> +
> +	return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id sun50i_usb3_phy_of_match[] = {
> +	{ .compatible = "allwinner,sun50i-h6-usb3-phy" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match);
> +
> +static struct platform_driver sun50i_usb3_phy_driver = {
> +	.probe	= sun50i_usb3_phy_probe,
> +	.driver = {
> +		.of_match_table	= sun50i_usb3_phy_of_match,
> +		.name  = "sun50i-usb3-phy",
> +	}
> +};
> +module_platform_driver(sun50i_usb3_phy_driver);
> +
> +MODULE_DESCRIPTION("Allwinner sun50i USB 3.0 phy driver");
> +MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
> +MODULE_LICENSE("GPL");


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY
  2018-10-18 13:58       ` Rob Herring
  2018-10-19  5:54         ` [linux-sunxi] " Icenowy Zheng
@ 2018-11-14  5:15         ` Icenowy Zheng
  1 sibling, 0 replies; 27+ messages in thread
From: Icenowy Zheng @ 2018-11-14  5:15 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree, Maxime Ripard, Chen-Yu Tsai, linux-kernel,
	linux-sunxi, Kishon Vijay Abraham I,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

在 2018-10-18四的 08:58 -0500,Rob Herring写道:
> On Sat, Oct 13, 2018 at 9:42 PM Icenowy Zheng <icenowy@aosc.io>
> wrote:
> > 
> > 在 2018-10-05五的 15:58 -0500,Rob Herring写道:
> > > On Thu, Oct 04, 2018 at 08:28:52PM +0800, Icenowy Zheng wrote:
> > > > The new Allwinner H6 SoC contains a USB3 PHY that is wired to
> > > > the
> > > > external USB3 pins of the SoC.
> > > > 
> > > > Add a device tree binding for the PHY.
> > > > 
> > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > > > ---
> > > > Changes in v4:
> > > > - Changed Vbus regulator property to vbus-supply.
> > > > 
> > > > Changes in v3:
> > > > - Added Chen-Yu's Review tag.
> > > > 
> > > > No changes in v2, v1.
> > > > 
> > > >  .../bindings/phy/sun50i-usb3-phy.txt          | 23
> > > > +++++++++++++++++++
> > > >  1 file changed, 23 insertions(+)
> > > >  create mode 100644
> > > > Documentation/devicetree/bindings/phy/sun50i-
> > > > usb3-phy.txt
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/phy/sun50i-usb3-
> > > > phy.txt b/Documentation/devicetree/bindings/phy/sun50i-usb3-
> > > > phy.txt
> > > > new file mode 100644
> > > > index 000000000000..9f49c6b8c7e7
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> > > > @@ -0,0 +1,23 @@
> > > > +Allwinner sun50i USB3 PHY
> > > > +-----------------------
> > > > +
> > > > +Required properties:
> > > > +- compatible : should be one of
> > > > +  * allwinner,sun60i-h6-usb3-phy
> > > > +- reg : a list of offset + length pairs
> > > > +- #phy-cells : from the generic phy bindings, must be 0
> > > > +- clocks : phandle + clock specifier for the phy clock
> > > > +- resets : phandle + reset specifier for the phy reset
> > > > +
> > > > +Optional Properties:
> > > > +- vbus-supply : a phandle to a regulator that provides power
> > > > to
> > > > VBUS.
> > > 
> > > This belongs in a connector node as it is part of the connector
> > > unless
> > > the phy physically needs Vbus for power.
> > > 
> > > But others have done this, so all the phys can just be wrong...
> > 
> > How should we reference the connector?
> > 
> > Via OF graph or simply a property in PHY node?
> 
> The connector is either a child of the controller or an OF graph from
> the controller to the connector. The phy driver needs the controller
> node and then it can walk the tree or graph to get the connector
> node.

By reading the binding, it says the connector should be a child of the
"interface controller", not the USB controller. In this case I think
the interface controller is the PHY rather than the USB controller.

In addition, the connector is a passive component, and power management
should be done by the "interface controller", either directly by the
PHY or make a dummy interface controller driver that only controls the
Vbus.

> 
> Rob
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [linux-sunxi] [PATCH v4 04/10] arm64: allwinner: dts: h6: add USB2-related device nodes
  2018-10-04 12:28 ` [PATCH v4 04/10] arm64: allwinner: dts: h6: add USB2-related device nodes Icenowy Zheng
@ 2018-11-14 10:21   ` Chen-Yu Tsai
  2018-11-14 10:30     ` Icenowy Zheng
  0 siblings, 1 reply; 27+ messages in thread
From: Chen-Yu Tsai @ 2018-11-14 10:21 UTC (permalink / raw)
  To: Icenowy Zheng
  Cc: Rob Herring, Maxime Ripard, Kishon Vijay Abraham I, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi

Hi,

On Thu, Oct 4, 2018 at 8:30 PM Icenowy Zheng <icenowy@aosc.io> wrote:
>
> Allwinner H6 has two USB2 ports, one OTG and one host-only.
>
> Add device tree nodes related to them.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> ---
> No changes in v4.
>
> Changes in v3:
> - Removed the wrongly introduced usb3phy node.
> - Added Chen-Yu's Review tag.
>
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 81 ++++++++++++++++++++
>  1 file changed, 81 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 040828d2e2c0..3d60af6cb3ae 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -258,6 +258,87 @@
>                         status = "disabled";
>                 };
>
> +               usb2otg: usb@5100000 {
> +                       compatible = "allwinner,sun8i-a33-musb";

I added an SoC-specific compatible: "allwinner,sun50i-h6-musb".

I'm also curious as to whether the MUSB controller was tested or not,
since Allwinner now has EHCI/OHCI host pairs for host mode, and the Pine H64
only does host mode.

> +                       reg = <0x05100000 0x0400>;
> +                       clocks = <&ccu CLK_BUS_OTG>;
> +                       resets = <&ccu RST_BUS_OTG>;
> +                       interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "mc";
> +                       phys = <&usb2phy 0>;
> +                       phy-names = "usb";
> +                       extcon = <&usb2phy 0>;
> +                       status = "disabled";
> +               };
> +
> +               usb2phy: phy@5100400 {
> +                       compatible = "allwinner,sun50i-h6-usb-phy";
> +                       reg = <0x05100400 0x14>,
> +                             <0x05101800 0x4>,
> +                             <0x05311800 0x4>;
> +                       reg-names = "phy_ctrl",
> +                                   "pmu0",
> +                                   "pmu3";
> +                       clocks = <&ccu CLK_USB_PHY0>,
> +                                <&ccu CLK_USB_PHY3>;
> +                       clock-names = "usb0_phy",
> +                                     "usb3_phy";
> +                       resets = <&ccu RST_USB_PHY0>,
> +                                <&ccu RST_USB_PHY3>;
> +                       reset-names = "usb0_reset",
> +                                     "usb3_reset";
> +                       status = "disabled";
> +                       #phy-cells = <1>;
> +               };
> +
> +               ehci0: usb@5101000 {
> +                       compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
> +                       reg = <0x05101000 0x100>;
> +                       interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI0>,
> +                                <&ccu CLK_BUS_EHCI0>,
> +                                <&ccu CLK_USB_OHCI0>;
> +                       resets = <&ccu RST_BUS_OHCI0>,
> +                                <&ccu RST_BUS_EHCI0>;
> +                       status = "disabled";
> +               };
> +
> +               ohci0: usb@5101400 {
> +                       compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
> +                       reg = <0x05101400 0x100>;
> +                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI0>,
> +                                <&ccu CLK_USB_OHCI0>;
> +                       resets = <&ccu RST_BUS_OHCI0>;
> +                       status = "disabled";
> +               };
> +
> +               ehci3: usb@5311000 {
> +                       compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
> +                       reg = <0x05311000 0x100>;
> +                       interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI3>,
> +                                <&ccu CLK_BUS_EHCI3>,
> +                                <&ccu CLK_USB_OHCI3>;
> +                       resets = <&ccu RST_BUS_OHCI3>,
> +                                <&ccu RST_BUS_EHCI3>;
> +                       phys = <&usb2phy 3>;
> +                       phy-names = "usb";
> +                       status = "disabled";
> +               };
> +
> +               ohci3: usb@5311400 {
> +                       compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
> +                       reg = <0x05311400 0x100>;
> +                       interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI3>,
> +                                <&ccu CLK_USB_OHCI3>;
> +                       resets = <&ccu RST_BUS_OHCI3>;
> +                       phys = <&usb2phy 3>;
> +                       phy-names = "usb";
> +                       status = "disabled";
> +               };
> +

This didn't apply cleanly due to the new HDMI nodes. I fixed it up locally.

ChenYu

>                 r_ccu: clock@7010000 {
>                         compatible = "allwinner,sun50i-h6-r-ccu";
>                         reg = <0x07010000 0x400>;
> --
> 2.18.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [linux-sunxi] [PATCH v4 04/10] arm64: allwinner: dts: h6: add USB2-related device nodes
  2018-11-14 10:21   ` [linux-sunxi] " Chen-Yu Tsai
@ 2018-11-14 10:30     ` Icenowy Zheng
  2018-11-15  2:16       ` Chen-Yu Tsai
  0 siblings, 1 reply; 27+ messages in thread
From: Icenowy Zheng @ 2018-11-14 10:30 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Rob Herring, Maxime Ripard, Kishon Vijay Abraham I, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi



于 2018年11月14日 GMT+08:00 下午6:21:33, Chen-Yu Tsai <wens@csie.org> 写到:
>Hi,
>
>On Thu, Oct 4, 2018 at 8:30 PM Icenowy Zheng <icenowy@aosc.io> wrote:
>>
>> Allwinner H6 has two USB2 ports, one OTG and one host-only.
>>
>> Add device tree nodes related to them.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>> No changes in v4.
>>
>> Changes in v3:
>> - Removed the wrongly introduced usb3phy node.
>> - Added Chen-Yu's Review tag.
>>
>>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 81
>++++++++++++++++++++
>>  1 file changed, 81 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> index 040828d2e2c0..3d60af6cb3ae 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> @@ -258,6 +258,87 @@
>>                         status = "disabled";
>>                 };
>>
>> +               usb2otg: usb@5100000 {
>> +                       compatible = "allwinner,sun8i-a33-musb";
>
>I added an SoC-specific compatible: "allwinner,sun50i-h6-musb".
>
>I'm also curious as to whether the MUSB controller was tested or not,
>since Allwinner now has EHCI/OHCI host pairs for host mode, and the
>Pine H64
>only does host mode.

USB plug-in detection relays on MUSB if it's enabled.

>
>> +                       reg = <0x05100000 0x0400>;
>> +                       clocks = <&ccu CLK_BUS_OTG>;
>> +                       resets = <&ccu RST_BUS_OTG>;
>> +                       interrupts = <GIC_SPI 23
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       interrupt-names = "mc";
>> +                       phys = <&usb2phy 0>;
>> +                       phy-names = "usb";
>> +                       extcon = <&usb2phy 0>;
>> +                       status = "disabled";
>> +               };
>> +
>> +               usb2phy: phy@5100400 {
>> +                       compatible = "allwinner,sun50i-h6-usb-phy";
>> +                       reg = <0x05100400 0x14>,
>> +                             <0x05101800 0x4>,
>> +                             <0x05311800 0x4>;
>> +                       reg-names = "phy_ctrl",
>> +                                   "pmu0",
>> +                                   "pmu3";
>> +                       clocks = <&ccu CLK_USB_PHY0>,
>> +                                <&ccu CLK_USB_PHY3>;
>> +                       clock-names = "usb0_phy",
>> +                                     "usb3_phy";
>> +                       resets = <&ccu RST_USB_PHY0>,
>> +                                <&ccu RST_USB_PHY3>;
>> +                       reset-names = "usb0_reset",
>> +                                     "usb3_reset";
>> +                       status = "disabled";
>> +                       #phy-cells = <1>;
>> +               };
>> +
>> +               ehci0: usb@5101000 {
>> +                       compatible = "allwinner,sun50i-h6-ehci",
>"generic-ehci";
>> +                       reg = <0x05101000 0x100>;
>> +                       interrupts = <GIC_SPI 24
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&ccu CLK_BUS_OHCI0>,
>> +                                <&ccu CLK_BUS_EHCI0>,
>> +                                <&ccu CLK_USB_OHCI0>;
>> +                       resets = <&ccu RST_BUS_OHCI0>,
>> +                                <&ccu RST_BUS_EHCI0>;
>> +                       status = "disabled";
>> +               };
>> +
>> +               ohci0: usb@5101400 {
>> +                       compatible = "allwinner,sun50i-h6-ohci",
>"generic-ohci";
>> +                       reg = <0x05101400 0x100>;
>> +                       interrupts = <GIC_SPI 25
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&ccu CLK_BUS_OHCI0>,
>> +                                <&ccu CLK_USB_OHCI0>;
>> +                       resets = <&ccu RST_BUS_OHCI0>;
>> +                       status = "disabled";
>> +               };
>> +
>> +               ehci3: usb@5311000 {
>> +                       compatible = "allwinner,sun50i-h6-ehci",
>"generic-ehci";
>> +                       reg = <0x05311000 0x100>;
>> +                       interrupts = <GIC_SPI 28
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&ccu CLK_BUS_OHCI3>,
>> +                                <&ccu CLK_BUS_EHCI3>,
>> +                                <&ccu CLK_USB_OHCI3>;
>> +                       resets = <&ccu RST_BUS_OHCI3>,
>> +                                <&ccu RST_BUS_EHCI3>;
>> +                       phys = <&usb2phy 3>;
>> +                       phy-names = "usb";
>> +                       status = "disabled";
>> +               };
>> +
>> +               ohci3: usb@5311400 {
>> +                       compatible = "allwinner,sun50i-h6-ohci",
>"generic-ohci";
>> +                       reg = <0x05311400 0x100>;
>> +                       interrupts = <GIC_SPI 29
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&ccu CLK_BUS_OHCI3>,
>> +                                <&ccu CLK_USB_OHCI3>;
>> +                       resets = <&ccu RST_BUS_OHCI3>;
>> +                       phys = <&usb2phy 3>;
>> +                       phy-names = "usb";
>> +                       status = "disabled";
>> +               };
>> +
>
>This didn't apply cleanly due to the new HDMI nodes. I fixed it up
>locally.
>
>ChenYu
>
>>                 r_ccu: clock@7010000 {
>>                         compatible = "allwinner,sun50i-h6-r-ccu";
>>                         reg = <0x07010000 0x400>;
>> --
>> 2.18.0
>>
>> --
>> You received this message because you are subscribed to the Google
>Groups "linux-sunxi" group.
>> To unsubscribe from this group and stop receiving emails from it,
>send an email to linux-sunxi+unsubscribe@googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [linux-sunxi] [PATCH v4 04/10] arm64: allwinner: dts: h6: add USB2-related device nodes
  2018-11-14 10:30     ` Icenowy Zheng
@ 2018-11-15  2:16       ` Chen-Yu Tsai
  2018-11-15  6:28         ` Chen-Yu Tsai
  0 siblings, 1 reply; 27+ messages in thread
From: Chen-Yu Tsai @ 2018-11-15  2:16 UTC (permalink / raw)
  To: Icenowy Zheng
  Cc: Rob Herring, Maxime Ripard, Kishon Vijay Abraham I, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi

On Wed, Nov 14, 2018 at 6:31 PM Icenowy Zheng <icenowy@aosc.io> wrote:
> 于 2018年11月14日 GMT+08:00 下午6:21:33, Chen-Yu Tsai <wens@csie.org> 写到:
> >Hi,
> >
> >On Thu, Oct 4, 2018 at 8:30 PM Icenowy Zheng <icenowy@aosc.io> wrote:
> >>
> >> Allwinner H6 has two USB2 ports, one OTG and one host-only.
> >>
> >> Add device tree nodes related to them.
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >> No changes in v4.
> >>
> >> Changes in v3:
> >> - Removed the wrongly introduced usb3phy node.
> >> - Added Chen-Yu's Review tag.
> >>
> >>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 81
> >++++++++++++++++++++
> >>  1 file changed, 81 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> >b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> >> index 040828d2e2c0..3d60af6cb3ae 100644
> >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> >> @@ -258,6 +258,87 @@
> >>                         status = "disabled";
> >>                 };
> >>
> >> +               usb2otg: usb@5100000 {
> >> +                       compatible = "allwinner,sun8i-a33-musb";
> >
> >I added an SoC-specific compatible: "allwinner,sun50i-h6-musb".
> >
> >I'm also curious as to whether the MUSB controller was tested or not,
> >since Allwinner now has EHCI/OHCI host pairs for host mode, and the
> >Pine H64
> >only does host mode.
>
> USB plug-in detection relays on MUSB if it's enabled.

That's not what I meant. Have you actually used the MUSB core in either
device or host mode to know that it is compatible with the A33? And
that it works correctly?

IIRC ID detection is done by the PHY driver, using the GPIO lines.
In host mode, since it's already directly routed to the host pair,
it's the host pair that does plug-in detection. The MUSB core is
completely unused. It should be quite clear if you look at the times
each interrupt line fired.

ChenYu

> >
> >> +                       reg = <0x05100000 0x0400>;
> >> +                       clocks = <&ccu CLK_BUS_OTG>;
> >> +                       resets = <&ccu RST_BUS_OTG>;
> >> +                       interrupts = <GIC_SPI 23
> >IRQ_TYPE_LEVEL_HIGH>;
> >> +                       interrupt-names = "mc";
> >> +                       phys = <&usb2phy 0>;
> >> +                       phy-names = "usb";
> >> +                       extcon = <&usb2phy 0>;
> >> +                       status = "disabled";
> >> +               };
> >> +
> >> +               usb2phy: phy@5100400 {
> >> +                       compatible = "allwinner,sun50i-h6-usb-phy";
> >> +                       reg = <0x05100400 0x14>,
> >> +                             <0x05101800 0x4>,
> >> +                             <0x05311800 0x4>;
> >> +                       reg-names = "phy_ctrl",
> >> +                                   "pmu0",
> >> +                                   "pmu3";
> >> +                       clocks = <&ccu CLK_USB_PHY0>,
> >> +                                <&ccu CLK_USB_PHY3>;
> >> +                       clock-names = "usb0_phy",
> >> +                                     "usb3_phy";
> >> +                       resets = <&ccu RST_USB_PHY0>,
> >> +                                <&ccu RST_USB_PHY3>;
> >> +                       reset-names = "usb0_reset",
> >> +                                     "usb3_reset";
> >> +                       status = "disabled";
> >> +                       #phy-cells = <1>;
> >> +               };
> >> +
> >> +               ehci0: usb@5101000 {
> >> +                       compatible = "allwinner,sun50i-h6-ehci",
> >"generic-ehci";
> >> +                       reg = <0x05101000 0x100>;
> >> +                       interrupts = <GIC_SPI 24
> >IRQ_TYPE_LEVEL_HIGH>;
> >> +                       clocks = <&ccu CLK_BUS_OHCI0>,
> >> +                                <&ccu CLK_BUS_EHCI0>,
> >> +                                <&ccu CLK_USB_OHCI0>;
> >> +                       resets = <&ccu RST_BUS_OHCI0>,
> >> +                                <&ccu RST_BUS_EHCI0>;
> >> +                       status = "disabled";
> >> +               };
> >> +
> >> +               ohci0: usb@5101400 {
> >> +                       compatible = "allwinner,sun50i-h6-ohci",
> >"generic-ohci";
> >> +                       reg = <0x05101400 0x100>;
> >> +                       interrupts = <GIC_SPI 25
> >IRQ_TYPE_LEVEL_HIGH>;
> >> +                       clocks = <&ccu CLK_BUS_OHCI0>,
> >> +                                <&ccu CLK_USB_OHCI0>;
> >> +                       resets = <&ccu RST_BUS_OHCI0>;
> >> +                       status = "disabled";
> >> +               };
> >> +
> >> +               ehci3: usb@5311000 {
> >> +                       compatible = "allwinner,sun50i-h6-ehci",
> >"generic-ehci";
> >> +                       reg = <0x05311000 0x100>;
> >> +                       interrupts = <GIC_SPI 28
> >IRQ_TYPE_LEVEL_HIGH>;
> >> +                       clocks = <&ccu CLK_BUS_OHCI3>,
> >> +                                <&ccu CLK_BUS_EHCI3>,
> >> +                                <&ccu CLK_USB_OHCI3>;
> >> +                       resets = <&ccu RST_BUS_OHCI3>,
> >> +                                <&ccu RST_BUS_EHCI3>;
> >> +                       phys = <&usb2phy 3>;
> >> +                       phy-names = "usb";
> >> +                       status = "disabled";
> >> +               };
> >> +
> >> +               ohci3: usb@5311400 {
> >> +                       compatible = "allwinner,sun50i-h6-ohci",
> >"generic-ohci";
> >> +                       reg = <0x05311400 0x100>;
> >> +                       interrupts = <GIC_SPI 29
> >IRQ_TYPE_LEVEL_HIGH>;
> >> +                       clocks = <&ccu CLK_BUS_OHCI3>,
> >> +                                <&ccu CLK_USB_OHCI3>;
> >> +                       resets = <&ccu RST_BUS_OHCI3>;
> >> +                       phys = <&usb2phy 3>;
> >> +                       phy-names = "usb";
> >> +                       status = "disabled";
> >> +               };
> >> +
> >
> >This didn't apply cleanly due to the new HDMI nodes. I fixed it up
> >locally.
> >
> >ChenYu
> >
> >>                 r_ccu: clock@7010000 {
> >>                         compatible = "allwinner,sun50i-h6-r-ccu";
> >>                         reg = <0x07010000 0x400>;
> >> --
> >> 2.18.0
> >>
> >> --
> >> You received this message because you are subscribed to the Google
> >Groups "linux-sunxi" group.
> >> To unsubscribe from this group and stop receiving emails from it,
> >send an email to linux-sunxi+unsubscribe@googlegroups.com.
> >> For more options, visit https://groups.google.com/d/optout.
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [linux-sunxi] [PATCH v4 04/10] arm64: allwinner: dts: h6: add USB2-related device nodes
  2018-11-15  2:16       ` Chen-Yu Tsai
@ 2018-11-15  6:28         ` Chen-Yu Tsai
  0 siblings, 0 replies; 27+ messages in thread
From: Chen-Yu Tsai @ 2018-11-15  6:28 UTC (permalink / raw)
  To: Icenowy Zheng
  Cc: Rob Herring, Maxime Ripard, Kishon Vijay Abraham I, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi

On Thu, Nov 15, 2018 at 10:16 AM Chen-Yu Tsai <wens@csie.org> wrote:
>
> On Wed, Nov 14, 2018 at 6:31 PM Icenowy Zheng <icenowy@aosc.io> wrote:
> > 于 2018年11月14日 GMT+08:00 下午6:21:33, Chen-Yu Tsai <wens@csie.org> 写到:
> > >Hi,
> > >
> > >On Thu, Oct 4, 2018 at 8:30 PM Icenowy Zheng <icenowy@aosc.io> wrote:
> > >>
> > >> Allwinner H6 has two USB2 ports, one OTG and one host-only.
> > >>
> > >> Add device tree nodes related to them.
> > >>
> > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > >> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > >> ---
> > >> No changes in v4.
> > >>
> > >> Changes in v3:
> > >> - Removed the wrongly introduced usb3phy node.
> > >> - Added Chen-Yu's Review tag.
> > >>
> > >>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 81
> > >++++++++++++++++++++
> > >>  1 file changed, 81 insertions(+)
> > >>
> > >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > >b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > >> index 040828d2e2c0..3d60af6cb3ae 100644
> > >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > >> @@ -258,6 +258,87 @@
> > >>                         status = "disabled";
> > >>                 };
> > >>
> > >> +               usb2otg: usb@5100000 {
> > >> +                       compatible = "allwinner,sun8i-a33-musb";
> > >
> > >I added an SoC-specific compatible: "allwinner,sun50i-h6-musb".
> > >
> > >I'm also curious as to whether the MUSB controller was tested or not,
> > >since Allwinner now has EHCI/OHCI host pairs for host mode, and the
> > >Pine H64
> > >only does host mode.
> >
> > USB plug-in detection relays on MUSB if it's enabled.
>
> That's not what I meant. Have you actually used the MUSB core in either
> device or host mode to know that it is compatible with the A33? And
> that it works correctly?
>
> IIRC ID detection is done by the PHY driver, using the GPIO lines.
> In host mode, since it's already directly routed to the host pair,
> it's the host pair that does plug-in detection. The MUSB core is
> completely unused. It should be quite clear if you look at the times
> each interrupt line fired.

I forced the routing to use MUSB and it looks like it works OK.
And the BSP figures for the number of endpoints looks correct.
I'll push the patches out. Thanks.

ChenYu

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v4 08/10] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
  2018-11-14  4:57   ` Icenowy Zheng
@ 2018-11-20  5:11     ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 27+ messages in thread
From: Kishon Vijay Abraham I @ 2018-11-20  5:11 UTC (permalink / raw)
  To: Icenowy Zheng, Rob Herring, Maxime Ripard, Chen-Yu Tsai
  Cc: devicetree, linux-sunxi, linux-kernel, linux-arm-kernel

Hi,

On 14/11/18 10:27 AM, Icenowy Zheng wrote:
> 在 2018-10-04四的 20:28 +0800,Icenowy Zheng写道:
>> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
>> controlled).
>>
>> Add a driver for it.
>>
>> The register operations in this driver is mainly extracted from the
>> BSP
>> USB3 driver.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> 
> Kishon, I see this patch is picked to linux-next, however this patch is
> not in the stage that can be picked, because for the Vbus of USB3 PHY
> Rob Herring still have some problems.
> 
> Could you remove PATCH 7 and 8 in this patchset now?

I've updated my tree now.

Thanks
Kishon
> 
> Thanks!
> 
>> ---
>> Changes in v4:
>> - Added support for vbus-supply property.
>>
>> Changes in v3:
>> - Dropped USB_SUPPORT dependency.
>> - Added Chen-Yu's Review tag.
>>
>> No changes in v2, v1.
>>
>>   drivers/phy/allwinner/Kconfig           |  12 ++
>>   drivers/phy/allwinner/Makefile          |   1 +
>>   drivers/phy/allwinner/phy-sun50i-usb3.c | 239
>> ++++++++++++++++++++++++
>>   3 files changed, 252 insertions(+)
>>   create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c
>>
>> diff --git a/drivers/phy/allwinner/Kconfig
>> b/drivers/phy/allwinner/Kconfig
>> index cdc1e745ba47..064096e6a4e5 100644
>> --- a/drivers/phy/allwinner/Kconfig
>> +++ b/drivers/phy/allwinner/Kconfig
>> @@ -29,3 +29,15 @@ config PHY_SUN9I_USB
>>   	  sun9i SoCs.
>>   
>>   	  This driver controls each individual USB 2 host PHY.
>> +
>> +config PHY_SUN50I_USB3
>> +	tristate "Allwinner sun50i SoC USB3 PHY driver"
>> +	depends on ARCH_SUNXI && HAS_IOMEM && OF
>> +	depends on RESET_CONTROLLER
>> +	select USB_COMMON
>> +	select GENERIC_PHY
>> +	help
>> +	  Enable this to support the USB3.0-capable transceiver that is
>> +	  part of some Allwinner sun50i SoCs.
>> +
>> +	  This driver controls each individual USB 2+3 host PHY combo.
>> diff --git a/drivers/phy/allwinner/Makefile
>> b/drivers/phy/allwinner/Makefile
>> index 8605529c01a1..a8d01e9073c2 100644
>> --- a/drivers/phy/allwinner/Makefile
>> +++ b/drivers/phy/allwinner/Makefile
>> @@ -1,2 +1,3 @@
>>   obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
>>   obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
>> +obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
>> diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c
>> b/drivers/phy/allwinner/phy-sun50i-usb3.c
>> new file mode 100644
>> index 000000000000..70c299c01c3e
>> --- /dev/null
>> +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
>> @@ -0,0 +1,239 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Allwinner sun50i(H6) USB 3.0 phy driver
>> + *
>> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
>> + *
>> + * Based on phy-sun9i-usb.c, which is:
>> + *
>> + * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
>> + *
>> + * Based on code from Allwinner BSP, which is:
>> + *
>> + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/usb/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regulator/consumer.h>
>> +#include <linux/reset.h>
>> +
>> +/* Interface Status and Control Registers */
>> +#define SUNXI_ISCR			0x00
>> +#define SUNXI_PIPE_CLOCK_CONTROL	0x14
>> +#define SUNXI_PHY_TUNE_LOW		0x18
>> +#define SUNXI_PHY_TUNE_HIGH		0x1c
>> +#define SUNXI_PHY_EXTERNAL_CONTROL	0x20
>> +
>> +/* USB2.0 Interface Status and Control Register */
>> +#define SUNXI_ISCR_FORCE_VBUS		(3 << 12)
>> +
>> +/* PIPE Clock Control Register */
>> +#define SUNXI_PCC_PIPE_CLK_OPEN		(1 << 6)
>> +
>> +/* PHY External Control Register */
>> +#define SUNXI_PEC_EXTERN_VBUS		(3 << 1)
>> +#define SUNXI_PEC_SSC_EN		(1 << 24)
>> +#define SUNXI_PEC_REF_SSP_EN		(1 << 26)
>> +
>> +/* PHY Tune High Register */
>> +#define SUNXI_TX_DEEMPH_3P5DB(n)	((n) << 19)
>> +#define SUNXI_TX_DEEMPH_3P5DB_MASK	GENMASK(24, 19)
>> +#define SUNXI_TX_DEEMPH_6DB(n)		((n) << 13)
>> +#define SUNXI_TX_DEEMPH_6GB_MASK	GENMASK(18, 13)
>> +#define SUNXI_TX_SWING_FULL(n)		((n) << 6)
>> +#define SUNXI_TX_SWING_FULL_MASK	GENMASK(12, 6)
>> +#define SUNXI_LOS_BIAS(n)		((n) << 3)
>> +#define SUNXI_LOS_BIAS_MASK		GENMASK(5, 3)
>> +#define SUNXI_TXVBOOSTLVL(n)		((n) << 0)
>> +#define SUNXI_TXVBOOSTLVL_MASK		GENMASK(0, 2)
>> +
>> +struct sun50i_usb3_phy {
>> +	struct phy *phy;
>> +	void __iomem *regs;
>> +	struct reset_control *reset;
>> +	struct clk *clk;
>> +	bool regulator_on;
>> +	struct regulator *vbus;
>> +};
>> +
>> +static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
>> +{
>> +	u32 val;
>> +
>> +	val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
>> +	val |= SUNXI_PEC_EXTERN_VBUS;
>> +	val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
>> +	writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
>> +
>> +	val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
>> +	val |= SUNXI_PCC_PIPE_CLK_OPEN;
>> +	writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
>> +
>> +	val = readl(phy->regs + SUNXI_ISCR);
>> +	val |= SUNXI_ISCR_FORCE_VBUS;
>> +	writel(val, phy->regs + SUNXI_ISCR);
>> +
>> +	/*
>> +	 * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
>> +	 * registers are directly taken from the BSP USB3 driver from
>> +	 * Allwiner.
>> +	 */
>> +	writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
>> +
>> +	val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
>> +	val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
>> +		 SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
>> +		 SUNXI_TX_DEEMPH_3P5DB_MASK);
>> +	val |= SUNXI_TXVBOOSTLVL(0x7);
>> +	val |= SUNXI_LOS_BIAS(0x7);
>> +	val |= SUNXI_TX_SWING_FULL(0x55);
>> +	val |= SUNXI_TX_DEEMPH_6DB(0x20);
>> +	val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
>> +	writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
>> +}
>> +
>> +static int sun50i_usb3_phy_init(struct phy *_phy)
>> +{
>> +	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
>> +	int ret;
>> +
>> +	ret = clk_prepare_enable(phy->clk);
>> +	if (ret)
>> +		goto err_clk;
>> +
>> +	ret = reset_control_deassert(phy->reset);
>> +	if (ret)
>> +		goto err_reset;
>> +
>> +	sun50i_usb3_phy_open(phy);
>> +	return 0;
>> +
>> +err_reset:
>> +	clk_disable_unprepare(phy->clk);
>> +
>> +err_clk:
>> +	return ret;
>> +}
>> +
>> +static int sun50i_usb3_phy_exit(struct phy *_phy)
>> +{
>> +	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
>> +
>> +	reset_control_assert(phy->reset);
>> +	clk_disable_unprepare(phy->clk);
>> +
>> +	return 0;
>> +}
>> +
>> +static int sun50i_usb3_phy_power_on(struct phy *_phy)
>> +{
>> +	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
>> +	int ret;
>> +
>> +	if (!phy->vbus || phy->regulator_on)
>> +		return 0;
>> +
>> +	ret = regulator_enable(phy->vbus);
>> +	if (ret)
>> +		return ret;
>> +
>> +	phy->regulator_on = true;
>> +
>> +	return 0;
>> +}
>> +
>> +static int sun50i_usb3_phy_power_off(struct phy *_phy)
>> +{
>> +	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
>> +
>> +	if (!phy->vbus || !phy->regulator_on)
>> +		return 0;
>> +
>> +	regulator_disable(phy->vbus);
>> +	phy->regulator_on = false;
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct phy_ops sun50i_usb3_phy_ops = {
>> +	.init		= sun50i_usb3_phy_init,
>> +	.exit		= sun50i_usb3_phy_exit,
>> +	.power_on	= sun50i_usb3_phy_power_on,
>> +	.power_off	= sun50i_usb3_phy_power_off,
>> +	.owner		= THIS_MODULE,
>> +};
>> +
>> +static int sun50i_usb3_phy_probe(struct platform_device *pdev)
>> +{
>> +	struct sun50i_usb3_phy *phy;
>> +	struct device *dev = &pdev->dev;
>> +	struct phy_provider *phy_provider;
>> +	struct resource *res;
>> +
>> +	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
>> +	if (!phy)
>> +		return -ENOMEM;
>> +
>> +	phy->clk = devm_clk_get(dev, NULL);
>> +	if (IS_ERR(phy->clk)) {
>> +		dev_err(dev, "failed to get phy clock\n");
>> +		return PTR_ERR(phy->clk);
>> +	}
>> +
>> +	phy->reset = devm_reset_control_get(dev, NULL);
>> +	if (IS_ERR(phy->reset)) {
>> +		dev_err(dev, "failed to get reset control\n");
>> +		return PTR_ERR(phy->reset);
>> +	}
>> +
>> +	phy->vbus = devm_regulator_get_optional(dev, "vbus");
>> +	if (IS_ERR(phy->vbus)) {
>> +		if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
>> +			dev_err(dev, "Couldn't get vbus regulator...
>> Deferring probe\n");
>> +			return -EPROBE_DEFER;
>> +		}
>> +
>> +		phy->vbus = NULL;
>> +	}
>> +
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	phy->regs = devm_ioremap_resource(dev, res);
>> +	if (IS_ERR(phy->regs))
>> +		return PTR_ERR(phy->regs);
>> +
>> +	phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops);
>> +	if (IS_ERR(phy->phy)) {
>> +		dev_err(dev, "failed to create PHY\n");
>> +		return PTR_ERR(phy->phy);
>> +	}
>> +
>> +	phy_set_drvdata(phy->phy, phy);
>> +	phy_provider = devm_of_phy_provider_register(dev,
>> of_phy_simple_xlate);
>> +
>> +	return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static const struct of_device_id sun50i_usb3_phy_of_match[] = {
>> +	{ .compatible = "allwinner,sun50i-h6-usb3-phy" },
>> +	{ },
>> +};
>> +MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match);
>> +
>> +static struct platform_driver sun50i_usb3_phy_driver = {
>> +	.probe	= sun50i_usb3_phy_probe,
>> +	.driver = {
>> +		.of_match_table	= sun50i_usb3_phy_of_match,
>> +		.name  = "sun50i-usb3-phy",
>> +	}
>> +};
>> +module_platform_driver(sun50i_usb3_phy_driver);
>> +
>> +MODULE_DESCRIPTION("Allwinner sun50i USB 3.0 phy driver");
>> +MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
>> +MODULE_LICENSE("GPL");
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

end of thread, other threads:[~2018-11-20  5:12 UTC | newest]

Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-04 12:28 [PATCH v4 00/10] Allwinner H6 USB support Icenowy Zheng
2018-10-04 12:28 ` [PATCH v4 01/10] dt-bindings: phy: add binding for Allwinner H6 USB2 PHY Icenowy Zheng
2018-10-05 20:53   ` Rob Herring
2018-10-04 12:28 ` [PATCH v4 02/10] phy: sun4i-usb: add support for missing USB PHY index Icenowy Zheng
2018-10-04 12:28 ` [PATCH v4 03/10] phy: sun4i-usb: add support for H6 USB2 PHY Icenowy Zheng
2018-11-02  8:41   ` Icenowy Zheng
2018-11-02  8:43     ` Kishon Vijay Abraham I
2018-11-09 14:04       ` Icenowy Zheng
2018-10-04 12:28 ` [PATCH v4 04/10] arm64: allwinner: dts: h6: add USB2-related device nodes Icenowy Zheng
2018-11-14 10:21   ` [linux-sunxi] " Chen-Yu Tsai
2018-11-14 10:30     ` Icenowy Zheng
2018-11-15  2:16       ` Chen-Yu Tsai
2018-11-15  6:28         ` Chen-Yu Tsai
2018-10-04 12:28 ` [PATCH v4 05/10] arm64: allwinner: dts: h6: add USB Vbus regulator Icenowy Zheng
2018-10-04 12:28 ` [PATCH v4 06/10] arm64: allwinner: dts: h6: enable USB2 on Pine H64 Icenowy Zheng
2018-10-04 12:28 ` [PATCH v4 07/10] dt-bindings: phy: add binding for Allwinner USB3 PHY Icenowy Zheng
2018-10-05 20:58   ` Rob Herring
2018-10-14  2:41     ` Icenowy Zheng
2018-10-18 13:58       ` Rob Herring
2018-10-19  5:54         ` [linux-sunxi] " Icenowy Zheng
2018-11-14  5:15         ` Icenowy Zheng
2018-10-04 12:28 ` [PATCH v4 08/10] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC Icenowy Zheng
2018-11-14  4:57   ` Icenowy Zheng
2018-11-20  5:11     ` Kishon Vijay Abraham I
2018-10-04 12:28 ` [PATCH v4 09/10] arm64: allwinner: dts: h6: add USB3 device nodes Icenowy Zheng
2018-10-04 12:28 ` [PATCH v4 10/10] arm64: allwinner: dts: h6: enable USB3 port on Pine H64 Icenowy Zheng
2018-10-05 10:44 ` [linux-sunxi] [PATCH v4 00/10] Allwinner H6 USB support Chen-Yu Tsai

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