From: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
To: platform-driver-x86@vger.kernel.org
Cc: dvhart@infradead.org, andy@infradead.org,
linux-kernel@vger.kernel.org, rajneesh.bhardwaj@intel.com,
Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
Subject: [PATCH v2 2/4] platform/x86: intel_pmc_core: Fix LTR IGNORE Max offset
Date: Sat, 6 Oct 2018 12:21:11 +0530 [thread overview]
Message-ID: <20181006065113.669-2-rajneesh.bhardwaj@linux.intel.com> (raw)
In-Reply-To: <20181006065113.669-1-rajneesh.bhardwaj@linux.intel.com>
Cannonlake PCH allows us to ignore LTR from more IPs than Sunrisepoint
PCH so make the LTR ignore platform specific.
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
---
drivers/platform/x86/intel_pmc_core.c | 4 +++-
drivers/platform/x86/intel_pmc_core.h | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 217a822a8da1..c616cfedf2be 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -148,6 +148,7 @@ static const struct pmc_reg_map spt_reg_map = {
.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
+ .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
};
/* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */
@@ -319,6 +320,7 @@ static const struct pmc_reg_map cnp_reg_map = {
.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+ .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
};
static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
@@ -565,7 +567,7 @@ static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
goto out_unlock;
}
- if (val > NUM_IP_IGN_ALLOWED) {
+ if (val > map->ltr_ignore_max) {
err = -EINVAL;
goto out_unlock;
}
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index 7a00436e337d..7f8181057ec8 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -44,7 +44,7 @@
#define SPT_PMC_READ_DISABLE_BIT 0x16
#define SPT_PMC_MSG_FULL_STS_BIT 0x18
#define NUM_RETRIES 100
-#define NUM_IP_IGN_ALLOWED 17
+#define SPT_NUM_IP_IGN_ALLOWED 17
#define SPT_PMC_LTR_CUR_PLT 0x350
#define SPT_PMC_LTR_CUR_ASLT 0x354
@@ -154,6 +154,7 @@ enum ppfear_regs {
#define CNP_PPFEAR_NUM_ENTRIES 8
#define CNP_PMC_READ_DISABLE_BIT 22
#define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31)
+#define CNP_NUM_IP_IGN_ALLOWED 19
#define CNP_PMC_LTR_CUR_PLT 0x1B50
#define CNP_PMC_LTR_CUR_ASLT 0x1B54
#define CNP_PMC_LTR_SPA 0x1B60
@@ -216,6 +217,7 @@ struct pmc_reg_map {
const u32 pm_cfg_offset;
const int pm_read_disable_bit;
const u32 slps0_dbg_offset;
+ const u32 ltr_ignore_max;
};
/**
--
2.17.1
next prev parent reply other threads:[~2018-10-06 6:54 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-06 6:51 [PATCH v2 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info Rajneesh Bhardwaj
2018-10-06 6:51 ` Rajneesh Bhardwaj [this message]
2018-10-19 12:13 ` [PATCH v2 2/4] platform/x86: intel_pmc_core: Fix LTR IGNORE Max offset Andy Shevchenko
2018-10-06 6:51 ` [PATCH v2 3/4] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR Rajneesh Bhardwaj
2018-10-19 12:34 ` Andy Shevchenko
2018-10-30 7:40 ` Bhardwaj, Rajneesh
2018-10-30 9:39 ` Andy Shevchenko
2018-10-06 6:51 ` [PATCH v2 4/4] platform/x86: intel_telemetry: report debugfs failure Rajneesh Bhardwaj
2018-10-19 12:39 ` Andy Shevchenko
2018-10-30 7:41 ` Bhardwaj, Rajneesh
2018-10-30 13:12 ` Andy Shevchenko
2018-10-19 12:12 ` [PATCH v2 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info Andy Shevchenko
2018-10-30 7:25 ` Bhardwaj, Rajneesh
2018-10-30 9:30 ` Andy Shevchenko
2018-10-30 18:03 ` Srinivas Pandruvada
2018-10-30 18:33 ` Andy Shevchenko
2018-10-30 18:50 ` Srinivas Pandruvada
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