* [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support
@ 2018-10-07 9:38 Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 01/29] dt-bindings: bus: add H6 DE3 bus binding Jernej Skrabec
` (29 more replies)
0 siblings, 30 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
This series adds support for Display Engine 3.0 and HDMI 2.0a, which
can be found on H6 SoC.
Display Engine 3.0 in comparison to 2.0 mostly adds features needed for
displaying and processing 10-bit and AFBC formats, which are not yet
supported by this series.
This series is based on linux-next at next-20180828, which has working
R40 display pipeline support. I'll rebase series on later linux-next, if
needed, once R40 display pipeline support is reintroduced.
I suggest all patches go through allwinner tree, except DRM patches,
which should go through drm-misc tree.
Last detail, PineH64 model A schematic has DDC_EN signal, which enables
DDC voltage level shifter. TL Lim, PINE64 founder, said that this
signal is not actually present on PineH64 model A board. It is, however
present on PineH64 model B engineering samples, but it will be removed
in production version. Because of that, I didn't include any code for
it.
Please take a look.
Best regards,
Jernej
Changes from v1:
- Collected tags
- Reworked some commit messages and titles
- Remove two patches which were already merged
- Added new patches (10, 11, 12, 21)
- Lowered max. supported HDMI pixel clock to 594 MHz
- Reordered compatibles and quirks by family name
- Fixed kbuild test robot warnings
- renamed CLK_NUMBER to CLK_NUMBER_WITHOUT_ROT and introduced
CLK_NUMBER_WITH_ROT
- removed "inline" from functions in c file
- used regmap_bulk_write() for writing DE3 CSC table
- DE3 specific macros have "DE3_" prefix now
- reworked DE2/3 mixer registers initialization
- removed writing to edge detection registers because
functionality is not used
Icenowy Zheng (5):
dt-bindings: bus: add H6 DE3 bus binding
dt-bindings: display: sunxi: add DT binding for Allwinner H6 DW HDMI
drm: sun4i: add quirks for TCON TOP
dt-bindings: display: sun4i-drm: document H6 TCON TOP
drm: sun4i: add support for H6 TCON TOP
Jernej Skrabec (24):
clk: sunxi-ng: Adjust MP clock parent rate when allowed
clk: sunxi-ng: Use u64 for calculation of NM rate
clk: sunxi-ng: h6: Set video PLLs limits
dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
clk: sunxi-ng: Add support for H6 DE3 clocks
dt-bindings: display: sun4i-drm: Add H6 display engine compatibles
drm/sun4i: Add compatible for H6 display engine
drm/sun4i: Rework DE2 register defines
drm/sun4i: Rename DE2 registers related macros
drm/sun4i: Fix DE2 mixer size
drm/sun4i: Disable unused DE2 sub-engines
drm/sun4i: Add basic support for DE3
drm/sun4i: Add support for H6 DE3 mixer 0
drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a
drm/sun4i: Not all DW HDMI controllers has scrambled addresses
drm/sun4i: dw-hdmi: Make mode_valid function configurable
drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock
drm/sun4i: Add support for H6 DW HDMI controller
drm/sun4i: dw-hdmi-phy: Reorder quirks by family
drm/sun4i: Add support for Synopsys HDMI PHY
drm/sun4i: Add support for H6 HDMI PHY
drm/sun4i: Initialize registers in tcon-top driver
arm64: dts: allwinner: h6: Add HDMI pipeline
arm64: dts: allwinner: h6: Enable HDMI output on Pine H64 board
.../bindings/bus/sun50i-de2-bus.txt | 9 +-
.../devicetree/bindings/clock/sun8i-de2.txt | 5 +-
.../bindings/display/sunxi/sun4i-drm.txt | 30 ++-
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 25 +++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 201 +++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 4 +
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 71 +++++-
drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 4 +-
drivers/clk/sunxi-ng/ccu_mp.c | 64 +++++-
drivers/clk/sunxi-ng/ccu_nm.c | 18 +-
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
drivers/gpu/drm/sun4i/sun8i_csc.c | 89 +++++++-
drivers/gpu/drm/sun4i/sun8i_csc.h | 6 +-
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 46 +++-
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 14 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 201 +++++++++++++++--
drivers/gpu/drm/sun4i/sun8i_mixer.c | 147 ++++++++-----
drivers/gpu/drm/sun4i/sun8i_mixer.h | 205 +++++++++++-------
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 58 ++++-
drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 81 ++++---
drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 49 +++--
drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 67 +++---
drivers/gpu/drm/sun4i/sun8i_ui_scaler.h | 50 ++---
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 91 +++++---
drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 35 +--
drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 101 +++++----
drivers/gpu/drm/sun4i/sun8i_vi_scaler.h | 90 +++++---
include/dt-bindings/clock/sun8i-de2.h | 3 +
include/dt-bindings/reset/sun8i-de2.h | 1 +
30 files changed, 1333 insertions(+), 434 deletions(-)
--
2.19.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v2 01/29] dt-bindings: bus: add H6 DE3 bus binding
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-08 8:31 ` Maxime Ripard
2018-10-07 9:38 ` [PATCH v2 02/29] clk: sunxi-ng: Adjust MP clock parent rate when allowed Jernej Skrabec
` (28 subsequent siblings)
29 siblings, 1 reply; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The Allwinner H6 DE3 bus is similar to the A64 DE2 one.
Add its compatible string with the A64 string as fallback to the
binding.
Some description of the binding is modified to make it more generic.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
index 87dfb33fb3be..ac1445b95f41 100644
--- a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
+++ b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
@@ -1,11 +1,14 @@
-Device tree bindings for Allwinner A64 DE2 bus
+Device tree bindings for Allwinner DE2/3 bus
The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C)
-to be claimed for enabling the access.
+to be claimed for enabling the access. The DE3 on Allwinner H6 is at the same
+situation, and the binding also applies.
Required properties:
- - compatible: Should contain "allwinner,sun50i-a64-de2"
+ - compatible: Should be one of:
+ - "allwinner,sun50i-a64-de2"
+ - "allwinner,sun50i-a6-de3", "allwinner,sun50i-a64-de2"
- reg: A resource specifier for the register space
- #address-cells: Must be set to 1
- #size-cells: Must be set to 1
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 02/29] clk: sunxi-ng: Adjust MP clock parent rate when allowed
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 01/29] dt-bindings: bus: add H6 DE3 bus binding Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 03/29] clk: sunxi-ng: Use u64 for calculation of NM rate Jernej Skrabec
` (27 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Currently MP clocks don't consider adjusting parent rate even if they
are allowed to do so. Such behaviour considerably lowers amount of
possible rates, which is very inconvenient when such clock is used for
pixel clock, for example.
In order to improve the situation, adjusting parent rate is considered
when allowed.
This code is inspired by clk_divider_bestdiv() function, which does
basically the same thing for different clock type.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu_mp.c | 64 +++++++++++++++++++++++++++++++++--
1 file changed, 62 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
index 5d0af4051737..0357349eb767 100644
--- a/drivers/clk/sunxi-ng/ccu_mp.c
+++ b/drivers/clk/sunxi-ng/ccu_mp.c
@@ -40,6 +40,61 @@ static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
*p = best_p;
}
+static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
+ unsigned long *parent,
+ unsigned long rate,
+ unsigned int max_m,
+ unsigned int max_p)
+{
+ unsigned long parent_rate_saved;
+ unsigned long parent_rate, now;
+ unsigned long best_rate = 0;
+ unsigned int _m, _p, div;
+ unsigned long maxdiv;
+
+ parent_rate_saved = *parent;
+
+ /*
+ * The maximum divider we can use without overflowing
+ * unsigned long in rate * m * p below
+ */
+ maxdiv = max_m * max_p;
+ maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+ for (_p = 1; _p <= max_p; _p <<= 1) {
+ for (_m = 1; _m <= max_m; _m++) {
+ div = _m * _p;
+
+ if (div > maxdiv)
+ break;
+
+ if (rate * div == parent_rate_saved) {
+ /*
+ * It's the most ideal case if the requested
+ * rate can be divided from parent clock without
+ * needing to change parent rate, so return the
+ * divider immediately.
+ */
+ *parent = parent_rate_saved;
+ return rate;
+ }
+
+ parent_rate = clk_hw_round_rate(hw, rate * div);
+ now = parent_rate / div;
+
+ if (now <= rate && now > best_rate) {
+ best_rate = now;
+ *parent = parent_rate;
+
+ if (now == rate)
+ return rate;
+ }
+ }
+ }
+
+ return best_rate;
+}
+
static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
struct clk_hw *hw,
unsigned long *parent_rate,
@@ -56,8 +111,13 @@ static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
- ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
- rate = *parent_rate / p / m;
+ if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+ ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
+ rate = *parent_rate / p / m;
+ } else {
+ rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
+ max_m, max_p);
+ }
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= cmp->fixed_post_div;
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 03/29] clk: sunxi-ng: Use u64 for calculation of NM rate
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 01/29] dt-bindings: bus: add H6 DE3 bus binding Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 02/29] clk: sunxi-ng: Adjust MP clock parent rate when allowed Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 04/29] clk: sunxi-ng: h6: Set video PLLs limits Jernej Skrabec
` (26 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, stable
Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent
rate is 24MHz, intermediate result when calculating final rate easily
overflows 32 bit variable.
Because of that, introduce function for calculating clock rate which
uses 64 bit variable for intermediate result.
Fixes: 6174a1e24b0d ("clk: sunxi-ng: Add N-M-factor clock support")
Fixes: ee28648cb2b4 ("clk: sunxi-ng: Remove the use of rational computations")
CC: <stable@vger.kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu_nm.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index 6fe3c14f7b2d..424d8635b053 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -19,6 +19,17 @@ struct _ccu_nm {
unsigned long m, min_m, max_m;
};
+static unsigned long ccu_nm_calc_rate(unsigned long parent,
+ unsigned long n, unsigned long m)
+{
+ u64 rate = parent;
+
+ rate *= n;
+ do_div(rate, m);
+
+ return rate;
+}
+
static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nm *nm)
{
@@ -28,7 +39,8 @@ static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
for (_n = nm->min_n; _n <= nm->max_n; _n++) {
for (_m = nm->min_m; _m <= nm->max_m; _m++) {
- unsigned long tmp_rate = parent * _n / _m;
+ unsigned long tmp_rate = ccu_nm_calc_rate(parent,
+ _n, _m);
if (tmp_rate > rate)
continue;
@@ -100,7 +112,7 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
if (ccu_sdm_helper_is_enabled(&nm->common, &nm->sdm))
rate = ccu_sdm_helper_read_rate(&nm->common, &nm->sdm, m, n);
else
- rate = parent_rate * n / m;
+ rate = ccu_nm_calc_rate(parent_rate, n, m);
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
@@ -149,7 +161,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
ccu_nm_find_best(*parent_rate, rate, &_nm);
- rate = *parent_rate * _nm.n / _nm.m;
+ rate = ccu_nm_calc_rate(*parent_rate, _nm.n, _nm.m);
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 04/29] clk: sunxi-ng: h6: Set video PLLs limits
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (2 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 03/29] clk: sunxi-ng: Use u64 for calculation of NM rate Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-12 8:13 ` [linux-sunxi] " Jagan Teki
2018-10-07 9:38 ` [PATCH v2 05/29] dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description Jernej Skrabec
` (25 subsequent siblings)
29 siblings, 1 reply; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Video PLL factors can be set in a way that final PLL rate is outside
stable range. H6 user manual specifically says that N factor should not
be below 12. While it doesn't says anything about maximum stable rate, it
is clear that PLL doesn't work at 6.096 GHz (254 * 24 MHz).
Set minimum allowed PLL video rate to 288 MHz (12 * 24 MHz) and maximum
to 2.4 GHz, which is maximum in BSP driver.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index 2193e1495086..19ff09f610e4 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -120,6 +120,8 @@ static struct ccu_nm pll_video0_clk = {
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
+ .min_rate = 288000000,
+ .max_rate = 2400000000UL,
.common = {
.reg = 0x040,
.features = CCU_FEATURE_FIXED_POSTDIV,
@@ -136,6 +138,8 @@ static struct ccu_nm pll_video1_clk = {
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
+ .min_rate = 288000000,
+ .max_rate = 2400000000UL,
.common = {
.reg = 0x048,
.features = CCU_FEATURE_FIXED_POSTDIV,
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 05/29] dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (3 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 04/29] clk: sunxi-ng: h6: Set video PLLs limits Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 06/29] clk: sunxi-ng: Add support for H6 DE3 clocks Jernej Skrabec
` (24 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
This commit adds necessary description and dt includes for H6 DE3 clock.
It is very similar to others, but memory region has some additional
registers not found in DE2.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
include/dt-bindings/clock/sun8i-de2.h | 3 +++
include/dt-bindings/reset/sun8i-de2.h | 1 +
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index e94582e8b8a9..41a52c2acffd 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -1,5 +1,5 @@
-Allwinner Display Engine 2.0 Clock Control Binding
---------------------------------------------------
+Allwinner Display Engine 2.0/3.0 Clock Control Binding
+------------------------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
@@ -8,6 +8,7 @@ Required properties :
- "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
+ - "allwinner,sun50i-h6-de3-clk"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h
index 3bed63b524aa..7768f73b051e 100644
--- a/include/dt-bindings/clock/sun8i-de2.h
+++ b/include/dt-bindings/clock/sun8i-de2.h
@@ -15,4 +15,7 @@
#define CLK_MIXER1 7
#define CLK_WB 8
+#define CLK_BUS_ROT 9
+#define CLK_ROT 10
+
#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
diff --git a/include/dt-bindings/reset/sun8i-de2.h b/include/dt-bindings/reset/sun8i-de2.h
index 9526017432f0..1c36a6ac86d6 100644
--- a/include/dt-bindings/reset/sun8i-de2.h
+++ b/include/dt-bindings/reset/sun8i-de2.h
@@ -10,5 +10,6 @@
#define RST_MIXER0 0
#define RST_MIXER1 1
#define RST_WB 2
+#define RST_ROT 3
#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 06/29] clk: sunxi-ng: Add support for H6 DE3 clocks
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (4 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 05/29] dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 07/29] dt-bindings: display: sun4i-drm: Add H6 display engine compatibles Jernej Skrabec
` (23 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
Support for mixer0, mixer1, writeback and rotation units is added.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 71 ++++++++++++++++++++++++++--
drivers/clk/sunxi-ng/ccu-sun8i-de2.h | 4 +-
2 files changed, 71 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index bae5ee67a797..1c9ae0a319c1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -31,6 +31,8 @@ static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", "bus-de",
0x04, BIT(1), 0);
static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de",
0x04, BIT(2), 0);
+static SUNXI_CCU_GATE(bus_rot_clk, "bus-rot", "bus-de",
+ 0x04, BIT(3), 0);
static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div",
0x00, BIT(0), CLK_SET_RATE_PARENT);
@@ -38,6 +40,8 @@ static SUNXI_CCU_GATE(mixer1_clk, "mixer1", "mixer1-div",
0x00, BIT(1), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div",
0x00, BIT(2), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE(rot_clk, "rot", "rot-div",
+ 0x00, BIT(3), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
CLK_SET_RATE_PARENT);
@@ -45,6 +49,8 @@ static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(rot_div_clk, "rot-div", "de", 0x0c, 0x0c, 4,
+ CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4,
CLK_SET_RATE_PARENT);
@@ -53,6 +59,24 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
+static struct ccu_common *sun50i_h6_de3_clks[] = {
+ &mixer0_clk.common,
+ &mixer1_clk.common,
+ &wb_clk.common,
+
+ &bus_mixer0_clk.common,
+ &bus_mixer1_clk.common,
+ &bus_wb_clk.common,
+
+ &mixer0_div_clk.common,
+ &mixer1_div_clk.common,
+ &wb_div_clk.common,
+
+ &bus_rot_clk.common,
+ &rot_clk.common,
+ &rot_div_clk.common,
+};
+
static struct ccu_common *sun8i_a83t_de2_clks[] = {
&mixer0_clk.common,
&mixer1_clk.common,
@@ -106,7 +130,7 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
},
- .num = CLK_NUMBER,
+ .num = CLK_NUMBER_WITHOUT_ROT,
};
static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
@@ -123,7 +147,7 @@ static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
[CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
[CLK_WB_DIV] = &wb_div_clk.common.hw,
},
- .num = CLK_NUMBER,
+ .num = CLK_NUMBER_WITHOUT_ROT,
};
static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
@@ -137,7 +161,27 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
[CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
[CLK_WB_DIV] = &wb_div_clk.common.hw,
},
- .num = CLK_NUMBER,
+ .num = CLK_NUMBER_WITHOUT_ROT,
+};
+
+static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
+ .hws = {
+ [CLK_MIXER0] = &mixer0_clk.common.hw,
+ [CLK_MIXER1] = &mixer1_clk.common.hw,
+ [CLK_WB] = &wb_clk.common.hw,
+ [CLK_ROT] = &rot_clk.common.hw,
+
+ [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
+ [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
+ [CLK_BUS_WB] = &bus_wb_clk.common.hw,
+ [CLK_BUS_ROT] = &bus_rot_clk.common.hw,
+
+ [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
+ [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
+ [CLK_WB_DIV] = &wb_div_clk.common.hw,
+ [CLK_ROT_DIV] = &rot_div_clk.common.hw,
+ },
+ .num = CLK_NUMBER_WITH_ROT,
};
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
@@ -156,6 +200,13 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_WB] = { 0x08, BIT(2) },
};
+static struct ccu_reset_map sun50i_h6_de3_resets[] = {
+ [RST_MIXER0] = { 0x08, BIT(0) },
+ [RST_MIXER1] = { 0x08, BIT(1) },
+ [RST_WB] = { 0x08, BIT(2) },
+ [RST_ROT] = { 0x08, BIT(3) },
+};
+
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
.ccu_clks = sun8i_a83t_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
@@ -186,6 +237,16 @@ static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
};
+static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
+ .ccu_clks = sun50i_h6_de3_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
+
+ .hw_clks = &sun50i_h6_de3_hw_clks,
+
+ .resets = sun50i_h6_de3_resets,
+ .num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),
+};
+
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
.ccu_clks = sun8i_v3s_de2_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
@@ -296,6 +357,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.compatible = "allwinner,sun50i-h5-de2-clk",
.data = &sun50i_a64_de2_clk_desc,
},
+ {
+ .compatible = "allwinner,sun50i-h6-de3-clk",
+ .data = &sun50i_h6_de3_clk_desc,
+ },
{ }
};
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h
index 530c006e0ae9..fc9c6b4c89a8 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.h
@@ -22,7 +22,9 @@
#define CLK_MIXER0_DIV 3
#define CLK_MIXER1_DIV 4
#define CLK_WB_DIV 5
+#define CLK_ROT_DIV 11
-#define CLK_NUMBER (CLK_WB + 1)
+#define CLK_NUMBER_WITH_ROT (CLK_ROT_DIV + 1)
+#define CLK_NUMBER_WITHOUT_ROT (CLK_WB + 1)
#endif /* _CCU_SUN8I_DE2_H_ */
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 07/29] dt-bindings: display: sun4i-drm: Add H6 display engine compatibles
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (5 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 06/29] clk: sunxi-ng: Add support for H6 DE3 clocks Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 08/29] drm/sun4i: Add compatible for H6 display engine Jernej Skrabec
` (22 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
This commit adds compatibles used in H6 display pipeline, namely for
display engine, mixer and TV TCON.
H6 display engine is somewhat similar to R40, just less TCONs and
mixer support more features.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 7854fff4fc16..62c83b351344 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -158,6 +158,7 @@ Required properties:
* allwinner,sun9i-a80-tcon-tv
* "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd"
* "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv"
+ * allwinner,sun50i-h6-tcon-tv, allwinner,sun8i-r40-tcon-tv
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON.
@@ -381,6 +382,7 @@ Required properties:
* allwinner,sun8i-v3s-de2-mixer
* allwinner,sun50i-a64-de2-mixer-0
* allwinner,sun50i-a64-de2-mixer-1
+ * allwinner,sun50i-h6-de3-mixer-0
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
@@ -415,9 +417,10 @@ Required properties:
* allwinner,sun8i-v3s-display-engine
* allwinner,sun9i-a80-display-engine
* allwinner,sun50i-a64-display-engine
+ * allwinner,sun50i-h6-display-engine
- allwinner,pipelines: list of phandle to the display engine
- frontends (DE 1.0) or mixers (DE 2.0) available.
+ frontends (DE 1.0) or mixers (DE 2.0/3.0) available.
Example:
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 08/29] drm/sun4i: Add compatible for H6 display engine
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (6 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 07/29] dt-bindings: display: sun4i-drm: Add H6 display engine compatibles Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 09/29] drm/sun4i: Rework DE2 register defines Jernej Skrabec
` (21 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
H6 is first Allwinner SoC which supports 10 bit colors, HDR and AFBC.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 1e41c3f5fd6d..1ca7b70cbbfa 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -406,6 +406,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ .compatible = "allwinner,sun9i-a80-display-engine" },
{ .compatible = "allwinner,sun50i-a64-display-engine" },
+ { .compatible = "allwinner,sun50i-h6-display-engine" },
{ }
};
MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 09/29] drm/sun4i: Rework DE2 register defines
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (7 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 08/29] drm/sun4i: Add compatible for H6 display engine Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 10/29] drm/sun4i: Rename DE2 registers related macros Jernej Skrabec
` (20 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
Most, if not all, registers found in DE2 still exists in DE3. However,
units are on different base addresses.
To prepare for addition of DE3 support, registers macros are reworked so
they take base address as parameter.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
[rebased]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 14 ++++---
drivers/gpu/drm/sun4i/sun8i_mixer.h | 44 +++++++++++++-------
drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 47 ++++++++++++++--------
drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 37 +++++++++--------
drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 41 +++++++++++--------
drivers/gpu/drm/sun4i/sun8i_ui_scaler.h | 27 +++++--------
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 47 ++++++++++++++--------
drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 23 ++++++-----
drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 53 +++++++++++++++----------
drivers/gpu/drm/sun4i/sun8i_vi_scaler.h | 45 ++++++++++-----------
10 files changed, 219 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 8b3d02b146b7..6129c350f7bd 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -368,6 +368,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
struct sun8i_mixer *mixer;
struct resource *res;
void __iomem *regs;
+ unsigned int base;
int plane_cnt;
int i, ret;
@@ -456,6 +457,8 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
list_add_tail(&mixer->engine.list, &drv->engine_list);
+ base = sun8i_blender_base(mixer);
+
/* Reset the registers */
for (i = 0x0; i < 0x20000; i += 4)
regmap_write(mixer->engine.regs, i, 0);
@@ -465,24 +468,25 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
SUN8I_MIXER_GLOBAL_CTL_RT_EN);
/* Set background color to black */
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR,
+ regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
SUN8I_MIXER_BLEND_COLOR_BLACK);
/*
* Set fill color of bottom plane to black. Generally not needed
* except when VI plane is at bottom (zpos = 0) and enabled.
*/
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL,
+ regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(0),
+ regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
SUN8I_MIXER_BLEND_COLOR_BLACK);
plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
for (i = 0; i < plane_cnt; i++)
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(i),
+ regmap_write(mixer->engine.regs,
+ SUN8I_MIXER_BLEND_MODE(base, i),
SUN8I_MIXER_BLEND_MODE_DEF);
- regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL,
+ regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
return 0;
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 406c42e752d7..025550a1f539 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -29,20 +29,24 @@
#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
-#define SUN8I_MIXER_BLEND_PIPE_CTL 0x1000
-#define SUN8I_MIXER_BLEND_ATTR_FCOLOR(x) (0x1004 + 0x10 * (x) + 0x0)
-#define SUN8I_MIXER_BLEND_ATTR_INSIZE(x) (0x1004 + 0x10 * (x) + 0x4)
-#define SUN8I_MIXER_BLEND_ATTR_COORD(x) (0x1004 + 0x10 * (x) + 0x8)
-#define SUN8I_MIXER_BLEND_ROUTE 0x1080
-#define SUN8I_MIXER_BLEND_PREMULTIPLY 0x1084
-#define SUN8I_MIXER_BLEND_BKCOLOR 0x1088
-#define SUN8I_MIXER_BLEND_OUTSIZE 0x108c
-#define SUN8I_MIXER_BLEND_MODE(x) (0x1090 + 0x04 * (x))
-#define SUN8I_MIXER_BLEND_CK_CTL 0x10b0
-#define SUN8I_MIXER_BLEND_CK_CFG 0x10b4
-#define SUN8I_MIXER_BLEND_CK_MAX(x) (0x10c0 + 0x04 * (x))
-#define SUN8I_MIXER_BLEND_CK_MIN(x) (0x10e0 + 0x04 * (x))
-#define SUN8I_MIXER_BLEND_OUTCTL 0x10fc
+#define DE2_BLD_BASE 0x1000
+#define DE2_CH_BASE 0x2000
+#define DE2_CH_SIZE 0x1000
+
+#define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0)
+#define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x))
+#define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x))
+#define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x))
+#define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80)
+#define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84)
+#define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88)
+#define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c)
+#define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x))
+#define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0)
+#define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4)
+#define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x))
+#define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x))
+#define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc)
#define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
#define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
@@ -153,5 +157,17 @@ engine_to_sun8i_mixer(struct sunxi_engine *engine)
return container_of(engine, struct sun8i_mixer, engine);
}
+static inline u32
+sun8i_blender_base(struct sun8i_mixer *mixer)
+{
+ return DE2_BLD_BASE;
+}
+
+static inline u32
+sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
+{
+ return DE2_CH_BASE + channel * DE2_CH_SIZE;
+}
+
const struct de2_fmt_info *sun8i_mixer_format_info(u32 format);
#endif /* _SUN8I_MIXER_H_ */
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
index 28c15c6ef1ef..e3fc8fa920fb 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
@@ -30,7 +30,10 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
int overlay, bool enable, unsigned int zpos,
unsigned int old_zpos)
{
- u32 val;
+ u32 val, bld_base, ch_base;
+
+ bld_base = sun8i_blender_base(mixer);
+ ch_base = sun8i_channel_base(mixer, channel);
DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
enable ? "En" : "Dis", channel, overlay);
@@ -41,17 +44,17 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
val = 0;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR(channel, overlay),
+ SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
if (!enable || zpos != old_zpos) {
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_PIPE_CTL,
+ SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
0);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ROUTE,
+ SUN8I_MIXER_BLEND_ROUTE(bld_base),
SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
0);
}
@@ -60,12 +63,13 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_PIPE_CTL, val, val);
+ SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+ val, val);
val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ROUTE,
+ SUN8I_MIXER_BLEND_ROUTE(bld_base),
SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
val);
}
@@ -77,12 +81,16 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
{
struct drm_plane_state *state = plane->state;
u32 src_w, src_h, dst_w, dst_h;
+ u32 bld_base, ch_base;
u32 outsize, insize;
u32 hphase, vphase;
DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n",
channel, overlay);
+ bld_base = sun8i_blender_base(mixer);
+ ch_base = sun8i_channel_base(mixer, channel);
+
src_w = drm_rect_width(&state->src) >> 16;
src_h = drm_rect_height(&state->src) >> 16;
dst_w = drm_rect_width(&state->dst);
@@ -103,8 +111,8 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
regmap_write(mixer->engine.regs,
SUN8I_MIXER_GLOBAL_SIZE,
outsize);
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_OUTSIZE,
- outsize);
+ regmap_write(mixer->engine.regs,
+ SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize);
if (state->crtc)
interlaced = state->crtc->state->adjusted_mode.flags
@@ -116,7 +124,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
val = 0;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_OUTCTL,
+ SUN8I_MIXER_BLEND_OUTCTL(bld_base),
SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
val);
@@ -129,10 +137,10 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
state->src.x1 >> 16, state->src.y1 >> 16);
DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_SIZE(channel, overlay),
+ SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, overlay),
insize);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_OVL_SIZE(channel),
+ SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base),
insize);
if (insize != outsize || hphase || vphase) {
@@ -156,10 +164,10 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
state->dst.x1, state->dst.y1);
DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ATTR_COORD(zpos),
+ SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ATTR_INSIZE(zpos),
+ SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
outsize);
return 0;
@@ -170,7 +178,9 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
{
struct drm_plane_state *state = plane->state;
const struct de2_fmt_info *fmt_info;
- u32 val;
+ u32 val, ch_base;
+
+ ch_base = sun8i_channel_base(mixer, channel);
fmt_info = sun8i_mixer_format_info(state->fb->format->format);
if (!fmt_info || !fmt_info->rgb) {
@@ -180,7 +190,7 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR(channel, overlay),
+ SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
return 0;
@@ -193,8 +203,11 @@ static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
struct drm_framebuffer *fb = state->fb;
struct drm_gem_cma_object *gem;
dma_addr_t paddr;
+ u32 ch_base;
int bpp;
+ ch_base = sun8i_channel_base(mixer, channel);
+
/* Get the physical address of the buffer in memory */
gem = drm_fb_cma_get_gem_obj(fb, 0);
@@ -211,13 +224,13 @@ static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
/* Set the line width */
DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_PITCH(channel, overlay),
+ SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay),
fb->pitches[0]);
DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(channel, overlay),
+ SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay),
lower_32_bits(paddr));
return 0;
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
index 123b15ea9918..f4389cf0ba20 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
@@ -18,23 +18,26 @@
#include <drm/drm_plane.h>
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x0)
-#define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x4)
-#define SUN8I_MIXER_CHAN_UI_LAYER_COORD(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x8)
-#define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0xc)
-#define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x10)
-#define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x14)
-#define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x20 * (layer) + 0x18)
-#define SUN8I_MIXER_CHAN_UI_TOP_HADDR(ch) (0x2000 + 0x1000 * (ch) + 0x80)
-#define SUN8I_MIXER_CHAN_UI_BOT_HADDR(ch) (0x2000 + 0x1000 * (ch) + 0x84)
-#define SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch) (0x2000 + 0x1000 * (ch) + 0x88)
+#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \
+ ((base) + 0x20 * (layer) + 0x0)
+#define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \
+ ((base) + 0x20 * (layer) + 0x4)
+#define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \
+ ((base) + 0x20 * (layer) + 0x8)
+#define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \
+ ((base) + 0x20 * (layer) + 0xc)
+#define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \
+ ((base) + 0x20 * (layer) + 0x10)
+#define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \
+ ((base) + 0x20 * (layer) + 0x14)
+#define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \
+ ((base) + 0x20 * (layer) + 0x18)
+#define SUN8I_MIXER_CHAN_UI_TOP_HADDR(base) \
+ ((base) + 0x80)
+#define SUN8I_MIXER_CHAN_UI_BOT_HADDR(base) \
+ ((base) + 0x84)
+#define SUN8I_MIXER_CHAN_UI_OVL_SIZE(base) \
+ ((base) + 0x88)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN BIT(0)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK GENMASK(2, 1)
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
index 6bb2aa164c8e..698401ecb53d 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
@@ -10,6 +10,7 @@
*/
#include "sun8i_ui_scaler.h"
+#include "sun8i_vi_scaler.h"
static const u32 lan2coefftab16[240] = {
0x00004000, 0x00033ffe, 0x00063efc, 0x000a3bfb,
@@ -88,6 +89,14 @@ static const u32 lan2coefftab16[240] = {
0x0b1c1603, 0x0d1c1502, 0x0e1d1401, 0x0f1d1301,
};
+static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel)
+{
+ int vi_num = mixer->cfg->vi_num;
+
+ return DE2_VI_SCALER_UNIT_BASE + DE2_VI_SCALER_UNIT_SIZE * vi_num +
+ DE2_UI_SCALER_UNIT_SIZE * (channel - vi_num);
+}
+
static int sun8i_ui_scaler_coef_index(unsigned int step)
{
unsigned int scale, int_part, float_part;
@@ -114,33 +123,35 @@ static int sun8i_ui_scaler_coef_index(unsigned int step)
void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
{
- int vi_cnt = mixer->cfg->vi_num;
- u32 val;
+ u32 val, base;
- if (WARN_ON(layer < vi_cnt))
+ if (WARN_ON(layer < mixer->cfg->vi_num))
return;
+ base = sun8i_ui_scaler_base(mixer, layer);
+
if (enable)
val = SUN8I_SCALER_GSU_CTRL_EN |
SUN8I_SCALER_GSU_CTRL_COEFF_RDY;
else
val = 0;
- regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_CTRL(vi_cnt, layer - vi_cnt), val);
+ regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val);
}
void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer,
u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
u32 hscale, u32 vscale, u32 hphase, u32 vphase)
{
- int vi_cnt = mixer->cfg->vi_num;
u32 insize, outsize;
int i, offset;
+ u32 base;
- if (WARN_ON(layer < vi_cnt))
+ if (WARN_ON(layer < mixer->cfg->vi_num))
return;
+ base = sun8i_ui_scaler_base(mixer, layer);
+
hphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16;
vphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16;
hscale <<= SUN8I_UI_SCALER_SCALE_FRAC - 16;
@@ -149,24 +160,22 @@ void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer,
insize = SUN8I_UI_SCALER_SIZE(src_w, src_h);
outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h);
- layer -= vi_cnt;
-
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_OUTSIZE(vi_cnt, layer), outsize);
+ SUN8I_SCALER_GSU_OUTSIZE(base), outsize);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_INSIZE(vi_cnt, layer), insize);
+ SUN8I_SCALER_GSU_INSIZE(base), insize);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_HSTEP(vi_cnt, layer), hscale);
+ SUN8I_SCALER_GSU_HSTEP(base), hscale);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_VSTEP(vi_cnt, layer), vscale);
+ SUN8I_SCALER_GSU_VSTEP(base), vscale);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_HPHASE(vi_cnt, layer), hphase);
+ SUN8I_SCALER_GSU_HPHASE(base), hphase);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_VPHASE(vi_cnt, layer), vphase);
+ SUN8I_SCALER_GSU_VPHASE(base), vphase);
offset = sun8i_ui_scaler_coef_index(hscale) *
SUN8I_UI_SCALER_COEFF_COUNT;
for (i = 0; i < SUN8I_UI_SCALER_COEFF_COUNT; i++)
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_HCOEFF(vi_cnt, layer, i),
+ SUN8I_SCALER_GSU_HCOEFF(base, i),
lan2coefftab16[offset + i]);
}
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
index 86295be8be78..6b4bc1ff3e2c 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
@@ -11,6 +11,8 @@
#include "sun8i_mixer.h"
+#define DE2_UI_SCALER_UNIT_SIZE 0x10000
+
/* this two macros assumes 16 fractional bits which is standard in DRM */
#define SUN8I_UI_SCALER_SCALE_MIN 1
#define SUN8I_UI_SCALER_SCALE_MAX ((1UL << 20) - 1)
@@ -20,23 +22,14 @@
#define SUN8I_UI_SCALER_COEFF_COUNT 16
#define SUN8I_UI_SCALER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
-#define SUN8I_SCALER_GSU_CTRL(vi_cnt, ui_idx) \
- (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x0)
-#define SUN8I_SCALER_GSU_OUTSIZE(vi_cnt, ui_idx) \
- (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x40)
-#define SUN8I_SCALER_GSU_INSIZE(vi_cnt, ui_idx) \
- (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x80)
-#define SUN8I_SCALER_GSU_HSTEP(vi_cnt, ui_idx) \
- (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x88)
-#define SUN8I_SCALER_GSU_VSTEP(vi_cnt, ui_idx) \
- (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x8c)
-#define SUN8I_SCALER_GSU_HPHASE(vi_cnt, ui_idx) \
- (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x90)
-#define SUN8I_SCALER_GSU_VPHASE(vi_cnt, ui_idx) \
- (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x98)
-#define SUN8I_SCALER_GSU_HCOEFF(vi_cnt, ui_idx, index) \
- (0x20000 + 0x20000 * (vi_cnt) + 0x10000 * (ui_idx) + 0x200 + \
- 0x4 * (index))
+#define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0)
+#define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40)
+#define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80)
+#define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88)
+#define SUN8I_SCALER_GSU_VSTEP(base) ((base) + 0x8c)
+#define SUN8I_SCALER_GSU_HPHASE(base) ((base) + 0x90)
+#define SUN8I_SCALER_GSU_VPHASE(base) ((base) + 0x98)
+#define SUN8I_SCALER_GSU_HCOEFF(base, index) ((base) + 0x200 + 0x4 * (index))
#define SUN8I_SCALER_GSU_CTRL_EN BIT(0)
#define SUN8I_SCALER_GSU_CTRL_COEFF_RDY BIT(4)
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index f4fe97813f94..79811eae3735 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -24,7 +24,10 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
int overlay, bool enable, unsigned int zpos,
unsigned int old_zpos)
{
- u32 val;
+ u32 val, bld_base, ch_base;
+
+ bld_base = sun8i_blender_base(mixer);
+ ch_base = sun8i_channel_base(mixer, channel);
DRM_DEBUG_DRIVER("%sabling VI channel %d overlay %d\n",
enable ? "En" : "Dis", channel, overlay);
@@ -35,17 +38,17 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
val = 0;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_ATTR(channel, overlay),
+ SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
if (!enable || zpos != old_zpos) {
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_PIPE_CTL,
+ SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
0);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ROUTE,
+ SUN8I_MIXER_BLEND_ROUTE(bld_base),
SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
0);
}
@@ -54,12 +57,13 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_PIPE_CTL, val, val);
+ SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+ val, val);
val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ROUTE,
+ SUN8I_MIXER_BLEND_ROUTE(bld_base),
SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
val);
}
@@ -72,6 +76,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
struct drm_plane_state *state = plane->state;
const struct drm_format_info *format = state->fb->format;
u32 src_w, src_h, dst_w, dst_h;
+ u32 bld_base, ch_base;
u32 outsize, insize;
u32 hphase, vphase;
bool subsampled;
@@ -79,6 +84,9 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
channel, overlay);
+ bld_base = sun8i_blender_base(mixer);
+ ch_base = sun8i_channel_base(mixer, channel);
+
src_w = drm_rect_width(&state->src) >> 16;
src_h = drm_rect_height(&state->src) >> 16;
dst_w = drm_rect_width(&state->dst);
@@ -115,10 +123,10 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
(state->src.y1 >> 16) & ~(format->vsub - 1));
DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_SIZE(channel, overlay),
+ SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base, overlay),
insize);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_OVL_SIZE(channel),
+ SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base),
insize);
/*
@@ -149,10 +157,10 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
state->dst.x1, state->dst.y1);
DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ATTR_COORD(zpos),
+ SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ATTR_INSIZE(zpos),
+ SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
outsize);
return 0;
@@ -163,7 +171,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
{
struct drm_plane_state *state = plane->state;
const struct de2_fmt_info *fmt_info;
- u32 val;
+ u32 val, ch_base;
+
+ ch_base = sun8i_channel_base(mixer, channel);
fmt_info = sun8i_mixer_format_info(state->fb->format->format);
if (!fmt_info) {
@@ -173,7 +183,7 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_ATTR(channel, overlay),
+ SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
if (fmt_info->csc != SUN8I_CSC_MODE_OFF) {
@@ -189,7 +199,7 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
val = 0;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_ATTR(channel, overlay),
+ SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
return 0;
@@ -204,8 +214,11 @@ static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
struct drm_gem_cma_object *gem;
u32 dx, dy, src_x, src_y;
dma_addr_t paddr;
+ u32 ch_base;
int i;
+ ch_base = sun8i_channel_base(mixer, channel);
+
/* Adjust x and y to be dividable by subsampling factor */
src_x = (state->src.x1 >> 16) & ~(format->hsub - 1);
src_y = (state->src.y1 >> 16) & ~(format->vsub - 1);
@@ -235,17 +248,17 @@ static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
i + 1, fb->pitches[i]);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_PITCH(channel,
+ SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base,
overlay, i),
- fb->pitches[i]);
+ fb->pitches[i]);
DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
i + 1, &paddr);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(channel,
+ SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base,
overlay, i),
- lower_32_bits(paddr));
+ lower_32_bits(paddr));
}
return 0;
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
index 6996627a0a76..46f0237c17bb 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
@@ -12,17 +12,18 @@
#include <drm/drm_plane.h>
-#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0x0)
-#define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0x4)
-#define SUN8I_MIXER_CHAN_VI_LAYER_COORD(ch, layer) \
- (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0x8)
-#define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch, layer, plane) \
- (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0xc + 4 * (plane))
-#define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch, layer, plane) \
- (0x2000 + 0x1000 * (ch) + 0x30 * (layer) + 0x18 + 4 * (plane))
-#define SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch) (0x2000 + 0x1000 * (ch) + 0xe8)
+#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \
+ ((base) + 0x30 * (layer) + 0x0)
+#define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \
+ ((base) + 0x30 * (layer) + 0x4)
+#define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \
+ ((base) + 0x30 * (layer) + 0x8)
+#define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \
+ ((base) + 0x30 * (layer) + 0xc + 4 * (plane))
+#define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \
+ ((base) + 0x30 * (layer) + 0x18 + 4 * (plane))
+#define SUN8I_MIXER_CHAN_VI_OVL_SIZE(base) \
+ ((base) + 0xe8)
#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN BIT(0)
/* RGB mode should be set for RGB formats and cleared for YCbCr */
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
index d3f1acb234b7..9f6834c143d7 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
@@ -833,6 +833,11 @@ static const u32 bicubic4coefftab32[480] = {
0x1012110d, 0x1012110d, 0x1013110c, 0x1013110c,
};
+static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
+{
+ return DE2_VI_SCALER_UNIT_BASE + DE2_VI_SCALER_UNIT_SIZE * channel;
+}
+
static int sun8i_vi_scaler_coef_index(unsigned int step)
{
unsigned int scale, int_part, float_part;
@@ -857,7 +862,7 @@ static int sun8i_vi_scaler_coef_index(unsigned int step)
}
}
-static void sun8i_vi_scaler_set_coeff(struct regmap *map, int layer,
+static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base,
u32 hstep, u32 vstep,
const struct drm_format_info *format)
{
@@ -877,29 +882,31 @@ static void sun8i_vi_scaler_set_coeff(struct regmap *map, int layer,
offset = sun8i_vi_scaler_coef_index(hstep) *
SUN8I_VI_SCALER_COEFF_COUNT;
for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) {
- regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(layer, i),
+ regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, i),
lan3coefftab32_left[offset + i]);
- regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(layer, i),
+ regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, i),
lan3coefftab32_right[offset + i]);
- regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(layer, i),
+ regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, i),
ch_left[offset + i]);
- regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(layer, i),
+ regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, i),
ch_right[offset + i]);
}
offset = sun8i_vi_scaler_coef_index(hstep) *
SUN8I_VI_SCALER_COEFF_COUNT;
for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) {
- regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(layer, i),
+ regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, i),
lan2coefftab32[offset + i]);
- regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(layer, i),
+ regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, i),
cy[offset + i]);
}
}
void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
{
- u32 val;
+ u32 val, base;
+
+ base = sun8i_vi_scaler_base(mixer, layer);
if (enable)
val = SUN8I_SCALER_VSU_CTRL_EN |
@@ -907,7 +914,8 @@ void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
else
val = 0;
- regmap_write(mixer->engine.regs, SUN8I_SCALER_VSU_CTRL(layer), val);
+ regmap_write(mixer->engine.regs,
+ SUN8I_SCALER_VSU_CTRL(base), val);
}
void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
@@ -917,6 +925,9 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
{
u32 chphase, cvphase;
u32 insize, outsize;
+ u32 base;
+
+ base = sun8i_vi_scaler_base(mixer, layer);
hphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
vphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
@@ -941,31 +952,31 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
}
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_OUTSIZE(layer), outsize);
+ SUN8I_SCALER_VSU_OUTSIZE(base), outsize);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YINSIZE(layer), insize);
+ SUN8I_SCALER_VSU_YINSIZE(base), insize);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YHSTEP(layer), hscale);
+ SUN8I_SCALER_VSU_YHSTEP(base), hscale);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YVSTEP(layer), vscale);
+ SUN8I_SCALER_VSU_YVSTEP(base), vscale);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YHPHASE(layer), hphase);
+ SUN8I_SCALER_VSU_YHPHASE(base), hphase);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YVPHASE(layer), vphase);
+ SUN8I_SCALER_VSU_YVPHASE(base), vphase);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CINSIZE(layer),
+ SUN8I_SCALER_VSU_CINSIZE(base),
SUN8I_VI_SCALER_SIZE(src_w / format->hsub,
src_h / format->vsub));
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CHSTEP(layer),
+ SUN8I_SCALER_VSU_CHSTEP(base),
hscale / format->hsub);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CVSTEP(layer),
+ SUN8I_SCALER_VSU_CVSTEP(base),
vscale / format->vsub);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CHPHASE(layer), chphase);
+ SUN8I_SCALER_VSU_CHPHASE(base), chphase);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CVPHASE(layer), cvphase);
- sun8i_vi_scaler_set_coeff(mixer->engine.regs, layer,
+ SUN8I_SCALER_VSU_CVPHASE(base), cvphase);
+ sun8i_vi_scaler_set_coeff(mixer->engine.regs, base,
hscale, vscale, format);
}
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
index a595ab643a5a..f3de87122f07 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
@@ -12,6 +12,9 @@
#include <drm/drm_fourcc.h>
#include "sun8i_mixer.h"
+#define DE2_VI_SCALER_UNIT_BASE 0x20000
+#define DE2_VI_SCALER_UNIT_SIZE 0x20000
+
/* this two macros assumes 16 fractional bits which is standard in DRM */
#define SUN8I_VI_SCALER_SCALE_MIN 1
#define SUN8I_VI_SCALER_SCALE_MAX ((1UL << 20) - 1)
@@ -21,30 +24,24 @@
#define SUN8I_VI_SCALER_COEFF_COUNT 32
#define SUN8I_VI_SCALER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
-#define SUN8I_SCALER_VSU_CTRL(ch) (0x20000 + 0x20000 * (ch) + 0x0)
-#define SUN8I_SCALER_VSU_OUTSIZE(ch) (0x20000 + 0x20000 * (ch) + 0x40)
-#define SUN8I_SCALER_VSU_YINSIZE(ch) (0x20000 + 0x20000 * (ch) + 0x80)
-#define SUN8I_SCALER_VSU_YHSTEP(ch) (0x20000 + 0x20000 * (ch) + 0x88)
-#define SUN8I_SCALER_VSU_YVSTEP(ch) (0x20000 + 0x20000 * (ch) + 0x8c)
-#define SUN8I_SCALER_VSU_YHPHASE(ch) (0x20000 + 0x20000 * (ch) + 0x90)
-#define SUN8I_SCALER_VSU_YVPHASE(ch) (0x20000 + 0x20000 * (ch) + 0x98)
-#define SUN8I_SCALER_VSU_CINSIZE(ch) (0x20000 + 0x20000 * (ch) + 0xc0)
-#define SUN8I_SCALER_VSU_CHSTEP(ch) (0x20000 + 0x20000 * (ch) + 0xc8)
-#define SUN8I_SCALER_VSU_CVSTEP(ch) (0x20000 + 0x20000 * (ch) + 0xcc)
-#define SUN8I_SCALER_VSU_CHPHASE(ch) (0x20000 + 0x20000 * (ch) + 0xd0)
-#define SUN8I_SCALER_VSU_CVPHASE(ch) (0x20000 + 0x20000 * (ch) + 0xd8)
-#define SUN8I_SCALER_VSU_YHCOEFF0(ch, i) \
- (0x20000 + 0x20000 * (ch) + 0x200 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_YHCOEFF1(ch, i) \
- (0x20000 + 0x20000 * (ch) + 0x300 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_YVCOEFF(ch, i) \
- (0x20000 + 0x20000 * (ch) + 0x400 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_CHCOEFF0(ch, i) \
- (0x20000 + 0x20000 * (ch) + 0x600 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_CHCOEFF1(ch, i) \
- (0x20000 + 0x20000 * (ch) + 0x700 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_CVCOEFF(ch, i) \
- (0x20000 + 0x20000 * (ch) + 0x800 + 0x4 * (i))
+#define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0)
+#define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40)
+#define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80)
+#define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88)
+#define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c)
+#define SUN8I_SCALER_VSU_YHPHASE(base) ((base) + 0x90)
+#define SUN8I_SCALER_VSU_YVPHASE(base) ((base) + 0x98)
+#define SUN8I_SCALER_VSU_CINSIZE(base) ((base) + 0xc0)
+#define SUN8I_SCALER_VSU_CHSTEP(base) ((base) + 0xc8)
+#define SUN8I_SCALER_VSU_CVSTEP(base) ((base) + 0xcc)
+#define SUN8I_SCALER_VSU_CHPHASE(base) ((base) + 0xd0)
+#define SUN8I_SCALER_VSU_CVPHASE(base) ((base) + 0xd8)
+#define SUN8I_SCALER_VSU_YHCOEFF0(base, i) ((base) + 0x200 + 0x4 * (i))
+#define SUN8I_SCALER_VSU_YHCOEFF1(base, i) ((base) + 0x300 + 0x4 * (i))
+#define SUN8I_SCALER_VSU_YVCOEFF(base, i) ((base) + 0x400 + 0x4 * (i))
+#define SUN8I_SCALER_VSU_CHCOEFF0(base, i) ((base) + 0x600 + 0x4 * (i))
+#define SUN8I_SCALER_VSU_CHCOEFF1(base, i) ((base) + 0x700 + 0x4 * (i))
+#define SUN8I_SCALER_VSU_CVCOEFF(base, i) ((base) + 0x800 + 0x4 * (i))
#define SUN8I_SCALER_VSU_CTRL_EN BIT(0)
#define SUN8I_SCALER_VSU_CTRL_COEFF_RDY BIT(4)
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 10/29] drm/sun4i: Rename DE2 registers related macros
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (8 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 09/29] drm/sun4i: Rework DE2 register defines Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-08 10:18 ` Maxime Ripard
2018-10-07 9:38 ` [PATCH v2 11/29] drm/sun4i: Fix DE2 mixer size Jernej Skrabec
` (19 subsequent siblings)
29 siblings, 1 reply; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
In preparation to introduce DE3 support, change prefix from "SUN8I_" to
"DE2_". Current prefix suggest that it's valid only for one family,
whereas in reality, DE2 unit is used also on sun50i family.
Additionally, it will be easier to distinguish DE3 specific macros by
using "DE3_" prefix.
No functional change in this commit.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_csc.c | 6 +-
drivers/gpu/drm/sun4i/sun8i_csc.h | 6 +-
drivers/gpu/drm/sun4i/sun8i_mixer.c | 100 ++++++++--------
drivers/gpu/drm/sun4i/sun8i_mixer.h | 146 ++++++++++++------------
drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 62 +++++-----
drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 30 ++---
drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 38 +++---
drivers/gpu/drm/sun4i/sun8i_ui_scaler.h | 38 +++---
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 62 +++++-----
drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 20 ++--
drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 67 ++++++-----
drivers/gpu/drm/sun4i/sun8i_vi_scaler.h | 58 +++++-----
12 files changed, 316 insertions(+), 317 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
index b14925b40ccf..755b60bae408 100644
--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
@@ -57,7 +57,7 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
/* For some reason, 0x200 must be added to constant parts */
if (((i + 1) & 3) == 0)
data += 0x200;
- regmap_write(map, SUN8I_CSC_COEFF(base, i), data);
+ regmap_write(map, DE2_CSC_COEFF(base, i), data);
}
}
@@ -66,11 +66,11 @@ static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable)
u32 val;
if (enable)
- val = SUN8I_CSC_CTRL_EN;
+ val = DE2_CSC_CTRL_EN;
else
val = 0;
- regmap_update_bits(map, SUN8I_CSC_CTRL(base), SUN8I_CSC_CTRL_EN, val);
+ regmap_update_bits(map, DE2_CSC_CTRL(base), DE2_CSC_CTRL_EN, val);
}
void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h
index 880e8fbb0855..08ae38761280 100644
--- a/drivers/gpu/drm/sun4i/sun8i_csc.h
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.h
@@ -18,10 +18,10 @@ struct sun8i_mixer;
#define CCSC10_OFFSET 0xA0000
#define CCSC11_OFFSET 0xF0000
-#define SUN8I_CSC_CTRL(base) (base + 0x0)
-#define SUN8I_CSC_COEFF(base, i) (base + 0x10 + 4 * i)
+#define DE2_CSC_CTRL(base) (base + 0x0)
+#define DE2_CSC_COEFF(base, i) (base + 0x10 + 4 * i)
-#define SUN8I_CSC_CTRL_EN BIT(0)
+#define DE2_CSC_CTRL_EN BIT(0)
enum sun8i_csc_mode {
SUN8I_CSC_MODE_OFF,
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 6129c350f7bd..71c0f6dc8a49 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -34,217 +34,217 @@
static const struct de2_fmt_info de2_formats[] = {
{
.drm_fmt = DRM_FORMAT_ARGB8888,
- .de2_fmt = SUN8I_MIXER_FBFMT_ARGB8888,
+ .de2_fmt = DE2_MIXER_FBFMT_ARGB8888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_ABGR8888,
- .de2_fmt = SUN8I_MIXER_FBFMT_ABGR8888,
+ .de2_fmt = DE2_MIXER_FBFMT_ABGR8888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_RGBA8888,
- .de2_fmt = SUN8I_MIXER_FBFMT_RGBA8888,
+ .de2_fmt = DE2_MIXER_FBFMT_RGBA8888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_BGRA8888,
- .de2_fmt = SUN8I_MIXER_FBFMT_BGRA8888,
+ .de2_fmt = DE2_MIXER_FBFMT_BGRA8888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_XRGB8888,
- .de2_fmt = SUN8I_MIXER_FBFMT_XRGB8888,
+ .de2_fmt = DE2_MIXER_FBFMT_XRGB8888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_XBGR8888,
- .de2_fmt = SUN8I_MIXER_FBFMT_XBGR8888,
+ .de2_fmt = DE2_MIXER_FBFMT_XBGR8888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_RGBX8888,
- .de2_fmt = SUN8I_MIXER_FBFMT_RGBX8888,
+ .de2_fmt = DE2_MIXER_FBFMT_RGBX8888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_BGRX8888,
- .de2_fmt = SUN8I_MIXER_FBFMT_BGRX8888,
+ .de2_fmt = DE2_MIXER_FBFMT_BGRX8888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_RGB888,
- .de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
+ .de2_fmt = DE2_MIXER_FBFMT_RGB888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_BGR888,
- .de2_fmt = SUN8I_MIXER_FBFMT_BGR888,
+ .de2_fmt = DE2_MIXER_FBFMT_BGR888,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_RGB565,
- .de2_fmt = SUN8I_MIXER_FBFMT_RGB565,
+ .de2_fmt = DE2_MIXER_FBFMT_RGB565,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_BGR565,
- .de2_fmt = SUN8I_MIXER_FBFMT_BGR565,
+ .de2_fmt = DE2_MIXER_FBFMT_BGR565,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_ARGB4444,
- .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
+ .de2_fmt = DE2_MIXER_FBFMT_ARGB4444,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_ABGR4444,
- .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
+ .de2_fmt = DE2_MIXER_FBFMT_ABGR4444,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_RGBA4444,
- .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
+ .de2_fmt = DE2_MIXER_FBFMT_RGBA4444,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_BGRA4444,
- .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
+ .de2_fmt = DE2_MIXER_FBFMT_BGRA4444,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_ARGB1555,
- .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
+ .de2_fmt = DE2_MIXER_FBFMT_ARGB1555,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_ABGR1555,
- .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
+ .de2_fmt = DE2_MIXER_FBFMT_ABGR1555,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_RGBA5551,
- .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
+ .de2_fmt = DE2_MIXER_FBFMT_RGBA5551,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_BGRA5551,
- .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
+ .de2_fmt = DE2_MIXER_FBFMT_BGRA5551,
.rgb = true,
.csc = SUN8I_CSC_MODE_OFF,
},
{
.drm_fmt = DRM_FORMAT_UYVY,
- .de2_fmt = SUN8I_MIXER_FBFMT_UYVY,
+ .de2_fmt = DE2_MIXER_FBFMT_UYVY,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_VYUY,
- .de2_fmt = SUN8I_MIXER_FBFMT_VYUY,
+ .de2_fmt = DE2_MIXER_FBFMT_VYUY,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_YUYV,
- .de2_fmt = SUN8I_MIXER_FBFMT_YUYV,
+ .de2_fmt = DE2_MIXER_FBFMT_YUYV,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_YVYU,
- .de2_fmt = SUN8I_MIXER_FBFMT_YVYU,
+ .de2_fmt = DE2_MIXER_FBFMT_YVYU,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_NV16,
- .de2_fmt = SUN8I_MIXER_FBFMT_NV16,
+ .de2_fmt = DE2_MIXER_FBFMT_NV16,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_NV61,
- .de2_fmt = SUN8I_MIXER_FBFMT_NV61,
+ .de2_fmt = DE2_MIXER_FBFMT_NV61,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_NV12,
- .de2_fmt = SUN8I_MIXER_FBFMT_NV12,
+ .de2_fmt = DE2_MIXER_FBFMT_NV12,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_NV21,
- .de2_fmt = SUN8I_MIXER_FBFMT_NV21,
+ .de2_fmt = DE2_MIXER_FBFMT_NV21,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_YUV444,
- .de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
+ .de2_fmt = DE2_MIXER_FBFMT_RGB888,
.rgb = true,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_YUV422,
- .de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
+ .de2_fmt = DE2_MIXER_FBFMT_YUV422,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_YUV420,
- .de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
+ .de2_fmt = DE2_MIXER_FBFMT_YUV420,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_YUV411,
- .de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
+ .de2_fmt = DE2_MIXER_FBFMT_YUV411,
.rgb = false,
.csc = SUN8I_CSC_MODE_YUV2RGB,
},
{
.drm_fmt = DRM_FORMAT_YVU444,
- .de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
+ .de2_fmt = DE2_MIXER_FBFMT_RGB888,
.rgb = true,
.csc = SUN8I_CSC_MODE_YVU2RGB,
},
{
.drm_fmt = DRM_FORMAT_YVU422,
- .de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
+ .de2_fmt = DE2_MIXER_FBFMT_YUV422,
.rgb = false,
.csc = SUN8I_CSC_MODE_YVU2RGB,
},
{
.drm_fmt = DRM_FORMAT_YVU420,
- .de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
+ .de2_fmt = DE2_MIXER_FBFMT_YUV420,
.rgb = false,
.csc = SUN8I_CSC_MODE_YVU2RGB,
},
{
.drm_fmt = DRM_FORMAT_YVU411,
- .de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
+ .de2_fmt = DE2_MIXER_FBFMT_YUV411,
.rgb = false,
.csc = SUN8I_CSC_MODE_YVU2RGB,
},
@@ -265,8 +265,8 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine)
{
DRM_DEBUG_DRIVER("Committing changes\n");
- regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
- SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
+ regmap_write(engine->regs, DE2_MIXER_GLOBAL_DBUFF,
+ DE2_MIXER_GLOBAL_DBUFF_ENABLE);
}
static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
@@ -464,30 +464,30 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
regmap_write(mixer->engine.regs, i, 0);
/* Enable the mixer */
- regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
- SUN8I_MIXER_GLOBAL_CTL_RT_EN);
+ regmap_write(mixer->engine.regs, DE2_MIXER_GLOBAL_CTL,
+ DE2_MIXER_GLOBAL_CTL_RT_EN);
/* Set background color to black */
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
- SUN8I_MIXER_BLEND_COLOR_BLACK);
+ regmap_write(mixer->engine.regs, DE2_MIXER_BLEND_BKCOLOR(base),
+ DE2_MIXER_BLEND_COLOR_BLACK);
/*
* Set fill color of bottom plane to black. Generally not needed
* except when VI plane is at bottom (zpos = 0) and enabled.
*/
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
- SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
- SUN8I_MIXER_BLEND_COLOR_BLACK);
+ regmap_write(mixer->engine.regs, DE2_MIXER_BLEND_PIPE_CTL(base),
+ DE2_MIXER_BLEND_PIPE_CTL_FC_EN(0));
+ regmap_write(mixer->engine.regs, DE2_MIXER_BLEND_ATTR_FCOLOR(base, 0),
+ DE2_MIXER_BLEND_COLOR_BLACK);
plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
for (i = 0; i < plane_cnt; i++)
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_MODE(base, i),
- SUN8I_MIXER_BLEND_MODE_DEF);
+ DE2_MIXER_BLEND_MODE(base, i),
+ DE2_MIXER_BLEND_MODE_DEF);
- regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
- SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
+ regmap_update_bits(mixer->engine.regs, DE2_MIXER_BLEND_PIPE_CTL(base),
+ DE2_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
return 0;
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 025550a1f539..208e8219d2be 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -17,98 +17,98 @@
#include "sun8i_csc.h"
#include "sunxi_engine.h"
-#define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
-#define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x))
+#define DE2_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
+#define DE2_MIXER_COORD(x, y) ((y) << 16 | (x))
-#define SUN8I_MIXER_GLOBAL_CTL 0x0
-#define SUN8I_MIXER_GLOBAL_STATUS 0x4
-#define SUN8I_MIXER_GLOBAL_DBUFF 0x8
-#define SUN8I_MIXER_GLOBAL_SIZE 0xc
+#define DE2_MIXER_GLOBAL_CTL 0x0
+#define DE2_MIXER_GLOBAL_STATUS 0x4
+#define DE2_MIXER_GLOBAL_DBUFF 0x8
+#define DE2_MIXER_GLOBAL_SIZE 0xc
-#define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
+#define DE2_MIXER_GLOBAL_CTL_RT_EN BIT(0)
-#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
+#define DE2_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
#define DE2_BLD_BASE 0x1000
#define DE2_CH_BASE 0x2000
#define DE2_CH_SIZE 0x1000
-#define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0)
-#define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x))
-#define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x))
-#define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x))
-#define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80)
-#define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84)
-#define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88)
-#define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c)
-#define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x))
-#define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0)
-#define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4)
-#define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x))
-#define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x))
-#define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc)
-
-#define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
-#define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
-#define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe)
+#define DE2_MIXER_BLEND_PIPE_CTL(base) ((base) + 0)
+#define DE2_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x))
+#define DE2_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x))
+#define DE2_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x))
+#define DE2_MIXER_BLEND_ROUTE(base) ((base) + 0x80)
+#define DE2_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84)
+#define DE2_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88)
+#define DE2_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c)
+#define DE2_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x))
+#define DE2_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0)
+#define DE2_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4)
+#define DE2_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x))
+#define DE2_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x))
+#define DE2_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc)
+
+#define DE2_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
+#define DE2_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
+#define DE2_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe)
/* colors are always in AARRGGBB format */
-#define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000
+#define DE2_MIXER_BLEND_COLOR_BLACK 0xff000000
/* The following numbers are some still unknown magic numbers */
-#define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
-
-#define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2))
-#define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2)
-
-#define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
-
-#define SUN8I_MIXER_FBFMT_ARGB8888 0
-#define SUN8I_MIXER_FBFMT_ABGR8888 1
-#define SUN8I_MIXER_FBFMT_RGBA8888 2
-#define SUN8I_MIXER_FBFMT_BGRA8888 3
-#define SUN8I_MIXER_FBFMT_XRGB8888 4
-#define SUN8I_MIXER_FBFMT_XBGR8888 5
-#define SUN8I_MIXER_FBFMT_RGBX8888 6
-#define SUN8I_MIXER_FBFMT_BGRX8888 7
-#define SUN8I_MIXER_FBFMT_RGB888 8
-#define SUN8I_MIXER_FBFMT_BGR888 9
-#define SUN8I_MIXER_FBFMT_RGB565 10
-#define SUN8I_MIXER_FBFMT_BGR565 11
-#define SUN8I_MIXER_FBFMT_ARGB4444 12
-#define SUN8I_MIXER_FBFMT_ABGR4444 13
-#define SUN8I_MIXER_FBFMT_RGBA4444 14
-#define SUN8I_MIXER_FBFMT_BGRA4444 15
-#define SUN8I_MIXER_FBFMT_ARGB1555 16
-#define SUN8I_MIXER_FBFMT_ABGR1555 17
-#define SUN8I_MIXER_FBFMT_RGBA5551 18
-#define SUN8I_MIXER_FBFMT_BGRA5551 19
-
-#define SUN8I_MIXER_FBFMT_YUYV 0
-#define SUN8I_MIXER_FBFMT_UYVY 1
-#define SUN8I_MIXER_FBFMT_YVYU 2
-#define SUN8I_MIXER_FBFMT_VYUY 3
-#define SUN8I_MIXER_FBFMT_NV16 4
-#define SUN8I_MIXER_FBFMT_NV61 5
-#define SUN8I_MIXER_FBFMT_YUV422 6
+#define DE2_MIXER_BLEND_MODE_DEF 0x03010301
+
+#define DE2_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2))
+#define DE2_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2)
+
+#define DE2_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
+
+#define DE2_MIXER_FBFMT_ARGB8888 0
+#define DE2_MIXER_FBFMT_ABGR8888 1
+#define DE2_MIXER_FBFMT_RGBA8888 2
+#define DE2_MIXER_FBFMT_BGRA8888 3
+#define DE2_MIXER_FBFMT_XRGB8888 4
+#define DE2_MIXER_FBFMT_XBGR8888 5
+#define DE2_MIXER_FBFMT_RGBX8888 6
+#define DE2_MIXER_FBFMT_BGRX8888 7
+#define DE2_MIXER_FBFMT_RGB888 8
+#define DE2_MIXER_FBFMT_BGR888 9
+#define DE2_MIXER_FBFMT_RGB565 10
+#define DE2_MIXER_FBFMT_BGR565 11
+#define DE2_MIXER_FBFMT_ARGB4444 12
+#define DE2_MIXER_FBFMT_ABGR4444 13
+#define DE2_MIXER_FBFMT_RGBA4444 14
+#define DE2_MIXER_FBFMT_BGRA4444 15
+#define DE2_MIXER_FBFMT_ARGB1555 16
+#define DE2_MIXER_FBFMT_ABGR1555 17
+#define DE2_MIXER_FBFMT_RGBA5551 18
+#define DE2_MIXER_FBFMT_BGRA5551 19
+
+#define DE2_MIXER_FBFMT_YUYV 0
+#define DE2_MIXER_FBFMT_UYVY 1
+#define DE2_MIXER_FBFMT_YVYU 2
+#define DE2_MIXER_FBFMT_VYUY 3
+#define DE2_MIXER_FBFMT_NV16 4
+#define DE2_MIXER_FBFMT_NV61 5
+#define DE2_MIXER_FBFMT_YUV422 6
/* format 7 doesn't exist */
-#define SUN8I_MIXER_FBFMT_NV12 8
-#define SUN8I_MIXER_FBFMT_NV21 9
-#define SUN8I_MIXER_FBFMT_YUV420 10
+#define DE2_MIXER_FBFMT_NV12 8
+#define DE2_MIXER_FBFMT_NV21 9
+#define DE2_MIXER_FBFMT_YUV420 10
/* format 11 doesn't exist */
/* format 12 is semi-planar YUV411 UVUV */
/* format 13 is semi-planar YUV411 VUVU */
-#define SUN8I_MIXER_FBFMT_YUV411 14
+#define DE2_MIXER_FBFMT_YUV411 14
/*
* These sub-engines are still unknown now, the EN registers are here only to
* be used to disable these sub-engines.
*/
-#define SUN8I_MIXER_FCE_EN 0xa0000
-#define SUN8I_MIXER_BWS_EN 0xa2000
-#define SUN8I_MIXER_LTI_EN 0xa4000
-#define SUN8I_MIXER_PEAK_EN 0xa6000
-#define SUN8I_MIXER_ASE_EN 0xa8000
-#define SUN8I_MIXER_FCC_EN 0xaa000
-#define SUN8I_MIXER_DCSC_EN 0xb0000
+#define DE2_MIXER_FCE_EN 0xa0000
+#define DE2_MIXER_BWS_EN 0xa2000
+#define DE2_MIXER_LTI_EN 0xa4000
+#define DE2_MIXER_PEAK_EN 0xa6000
+#define DE2_MIXER_ASE_EN 0xa8000
+#define DE2_MIXER_FCC_EN 0xaa000
+#define DE2_MIXER_DCSC_EN 0xb0000
struct de2_fmt_info {
u32 drm_fmt;
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
index e3fc8fa920fb..e4a3109d373c 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
@@ -39,38 +39,38 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
enable ? "En" : "Dis", channel, overlay);
if (enable)
- val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
+ val = DE2_MIXER_CHAN_UI_LAYER_ATTR_EN;
else
val = 0;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
+ DE2_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
+ DE2_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
if (!enable || zpos != old_zpos) {
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
- SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
+ DE2_MIXER_BLEND_PIPE_CTL(bld_base),
+ DE2_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
0);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ROUTE(bld_base),
- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
+ DE2_MIXER_BLEND_ROUTE(bld_base),
+ DE2_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
0);
}
if (enable) {
- val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+ val = DE2_MIXER_BLEND_PIPE_CTL_EN(zpos);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+ DE2_MIXER_BLEND_PIPE_CTL(bld_base),
val, val);
- val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
+ val = channel << DE2_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ROUTE(bld_base),
- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
+ DE2_MIXER_BLEND_ROUTE(bld_base),
+ DE2_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
val);
}
}
@@ -99,8 +99,8 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
hphase = state->src.x1 & 0xffff;
vphase = state->src.y1 & 0xffff;
- insize = SUN8I_MIXER_SIZE(src_w, src_h);
- outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
+ insize = DE2_MIXER_SIZE(src_w, src_h);
+ outsize = DE2_MIXER_SIZE(dst_w, dst_h);
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
bool interlaced = false;
@@ -109,23 +109,23 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
dst_w, dst_h);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_GLOBAL_SIZE,
+ DE2_MIXER_GLOBAL_SIZE,
outsize);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize);
+ DE2_MIXER_BLEND_OUTSIZE(bld_base), outsize);
if (state->crtc)
interlaced = state->crtc->state->adjusted_mode.flags
& DRM_MODE_FLAG_INTERLACE;
if (interlaced)
- val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
+ val = DE2_MIXER_BLEND_OUTCTL_INTERLACED;
else
val = 0;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_OUTCTL(bld_base),
- SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
+ DE2_MIXER_BLEND_OUTCTL(bld_base),
+ DE2_MIXER_BLEND_OUTCTL_INTERLACED,
val);
DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
@@ -137,10 +137,10 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
state->src.x1 >> 16, state->src.y1 >> 16);
DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, overlay),
+ DE2_MIXER_CHAN_UI_LAYER_SIZE(ch_base, overlay),
insize);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base),
+ DE2_MIXER_CHAN_UI_OVL_SIZE(ch_base),
insize);
if (insize != outsize || hphase || vphase) {
@@ -164,10 +164,10 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
state->dst.x1, state->dst.y1);
DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
- SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
+ DE2_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
+ DE2_MIXER_COORD(state->dst.x1, state->dst.y1));
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
+ DE2_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
outsize);
return 0;
@@ -188,10 +188,10 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
return -EINVAL;
}
- val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
+ val = fmt_info->de2_fmt << DE2_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
+ DE2_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
+ DE2_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
return 0;
}
@@ -224,13 +224,13 @@ static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
/* Set the line width */
DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay),
+ DE2_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay),
fb->pitches[0]);
DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay),
+ DE2_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay),
lower_32_bits(paddr));
return 0;
@@ -255,8 +255,8 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
max_scale = DRM_PLANE_HELPER_NO_SCALING;
if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
- min_scale = SUN8I_UI_SCALER_SCALE_MIN;
- max_scale = SUN8I_UI_SCALER_SCALE_MAX;
+ min_scale = DE2_UI_SCALER_SCALE_MIN;
+ max_scale = DE2_UI_SCALER_SCALE_MAX;
}
return drm_atomic_helper_check_plane_state(state, crtc_state,
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
index f4389cf0ba20..df9e648a5de6 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
@@ -18,32 +18,32 @@
#include <drm/drm_plane.h>
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \
+#define DE2_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \
((base) + 0x20 * (layer) + 0x0)
-#define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \
+#define DE2_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \
((base) + 0x20 * (layer) + 0x4)
-#define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \
+#define DE2_MIXER_CHAN_UI_LAYER_COORD(base, layer) \
((base) + 0x20 * (layer) + 0x8)
-#define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \
+#define DE2_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \
((base) + 0x20 * (layer) + 0xc)
-#define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \
+#define DE2_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \
((base) + 0x20 * (layer) + 0x10)
-#define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \
+#define DE2_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \
((base) + 0x20 * (layer) + 0x14)
-#define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \
+#define DE2_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \
((base) + 0x20 * (layer) + 0x18)
-#define SUN8I_MIXER_CHAN_UI_TOP_HADDR(base) \
+#define DE2_MIXER_CHAN_UI_TOP_HADDR(base) \
((base) + 0x80)
-#define SUN8I_MIXER_CHAN_UI_BOT_HADDR(base) \
+#define DE2_MIXER_CHAN_UI_BOT_HADDR(base) \
((base) + 0x84)
-#define SUN8I_MIXER_CHAN_UI_OVL_SIZE(base) \
+#define DE2_MIXER_CHAN_UI_OVL_SIZE(base) \
((base) + 0x88)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN BIT(0)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK GENMASK(2, 1)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET 8
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24)
+#define DE2_MIXER_CHAN_UI_LAYER_ATTR_EN BIT(0)
+#define DE2_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK GENMASK(2, 1)
+#define DE2_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)
+#define DE2_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET 8
+#define DE2_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24)
struct sun8i_mixer;
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
index 698401ecb53d..59dfe2deae8f 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
@@ -101,7 +101,7 @@ static int sun8i_ui_scaler_coef_index(unsigned int step)
{
unsigned int scale, int_part, float_part;
- scale = step >> (SUN8I_UI_SCALER_SCALE_FRAC - 3);
+ scale = step >> (DE2_UI_SCALER_SCALE_FRAC - 3);
int_part = scale >> 3;
float_part = scale & 0x7;
@@ -131,12 +131,12 @@ void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
base = sun8i_ui_scaler_base(mixer, layer);
if (enable)
- val = SUN8I_SCALER_GSU_CTRL_EN |
- SUN8I_SCALER_GSU_CTRL_COEFF_RDY;
+ val = DE2_SCALER_GSU_CTRL_EN |
+ DE2_SCALER_GSU_CTRL_COEFF_RDY;
else
val = 0;
- regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val);
+ regmap_write(mixer->engine.regs, DE2_SCALER_GSU_CTRL(base), val);
}
void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer,
@@ -152,30 +152,30 @@ void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer,
base = sun8i_ui_scaler_base(mixer, layer);
- hphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16;
- vphase <<= SUN8I_UI_SCALER_PHASE_FRAC - 16;
- hscale <<= SUN8I_UI_SCALER_SCALE_FRAC - 16;
- vscale <<= SUN8I_UI_SCALER_SCALE_FRAC - 16;
+ hphase <<= DE2_UI_SCALER_PHASE_FRAC - 16;
+ vphase <<= DE2_UI_SCALER_PHASE_FRAC - 16;
+ hscale <<= DE2_UI_SCALER_SCALE_FRAC - 16;
+ vscale <<= DE2_UI_SCALER_SCALE_FRAC - 16;
- insize = SUN8I_UI_SCALER_SIZE(src_w, src_h);
- outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h);
+ insize = DE2_UI_SCALER_SIZE(src_w, src_h);
+ outsize = DE2_UI_SCALER_SIZE(dst_w, dst_h);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_OUTSIZE(base), outsize);
+ DE2_SCALER_GSU_OUTSIZE(base), outsize);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_INSIZE(base), insize);
+ DE2_SCALER_GSU_INSIZE(base), insize);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_HSTEP(base), hscale);
+ DE2_SCALER_GSU_HSTEP(base), hscale);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_VSTEP(base), vscale);
+ DE2_SCALER_GSU_VSTEP(base), vscale);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_HPHASE(base), hphase);
+ DE2_SCALER_GSU_HPHASE(base), hphase);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_VPHASE(base), vphase);
+ DE2_SCALER_GSU_VPHASE(base), vphase);
offset = sun8i_ui_scaler_coef_index(hscale) *
- SUN8I_UI_SCALER_COEFF_COUNT;
- for (i = 0; i < SUN8I_UI_SCALER_COEFF_COUNT; i++)
+ DE2_UI_SCALER_COEFF_COUNT;
+ for (i = 0; i < DE2_UI_SCALER_COEFF_COUNT; i++)
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_GSU_HCOEFF(base, i),
+ DE2_SCALER_GSU_HCOEFF(base, i),
lan2coefftab16[offset + i]);
}
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
index 6b4bc1ff3e2c..8db18053e6ee 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
@@ -14,25 +14,25 @@
#define DE2_UI_SCALER_UNIT_SIZE 0x10000
/* this two macros assumes 16 fractional bits which is standard in DRM */
-#define SUN8I_UI_SCALER_SCALE_MIN 1
-#define SUN8I_UI_SCALER_SCALE_MAX ((1UL << 20) - 1)
-
-#define SUN8I_UI_SCALER_SCALE_FRAC 20
-#define SUN8I_UI_SCALER_PHASE_FRAC 20
-#define SUN8I_UI_SCALER_COEFF_COUNT 16
-#define SUN8I_UI_SCALER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
-
-#define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0)
-#define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40)
-#define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80)
-#define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88)
-#define SUN8I_SCALER_GSU_VSTEP(base) ((base) + 0x8c)
-#define SUN8I_SCALER_GSU_HPHASE(base) ((base) + 0x90)
-#define SUN8I_SCALER_GSU_VPHASE(base) ((base) + 0x98)
-#define SUN8I_SCALER_GSU_HCOEFF(base, index) ((base) + 0x200 + 0x4 * (index))
-
-#define SUN8I_SCALER_GSU_CTRL_EN BIT(0)
-#define SUN8I_SCALER_GSU_CTRL_COEFF_RDY BIT(4)
+#define DE2_UI_SCALER_SCALE_MIN 1
+#define DE2_UI_SCALER_SCALE_MAX ((1UL << 20) - 1)
+
+#define DE2_UI_SCALER_SCALE_FRAC 20
+#define DE2_UI_SCALER_PHASE_FRAC 20
+#define DE2_UI_SCALER_COEFF_COUNT 16
+#define DE2_UI_SCALER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
+
+#define DE2_SCALER_GSU_CTRL(base) ((base) + 0x0)
+#define DE2_SCALER_GSU_OUTSIZE(base) ((base) + 0x40)
+#define DE2_SCALER_GSU_INSIZE(base) ((base) + 0x80)
+#define DE2_SCALER_GSU_HSTEP(base) ((base) + 0x88)
+#define DE2_SCALER_GSU_VSTEP(base) ((base) + 0x8c)
+#define DE2_SCALER_GSU_HPHASE(base) ((base) + 0x90)
+#define DE2_SCALER_GSU_VPHASE(base) ((base) + 0x98)
+#define DE2_SCALER_GSU_HCOEFF(base, index) ((base) + 0x200 + 0x4 * (index))
+
+#define DE2_SCALER_GSU_CTRL_EN BIT(0)
+#define DE2_SCALER_GSU_CTRL_COEFF_RDY BIT(4)
void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable);
void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer,
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index 79811eae3735..8ea07f34ad5b 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -33,38 +33,38 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
enable ? "En" : "Dis", channel, overlay);
if (enable)
- val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
+ val = DE2_MIXER_CHAN_VI_LAYER_ATTR_EN;
else
val = 0;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
- SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
+ DE2_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
+ DE2_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
if (!enable || zpos != old_zpos) {
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
- SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
+ DE2_MIXER_BLEND_PIPE_CTL(bld_base),
+ DE2_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
0);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ROUTE(bld_base),
- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
+ DE2_MIXER_BLEND_ROUTE(bld_base),
+ DE2_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
0);
}
if (enable) {
- val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+ val = DE2_MIXER_BLEND_PIPE_CTL_EN(zpos);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+ DE2_MIXER_BLEND_PIPE_CTL(bld_base),
val, val);
- val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
+ val = channel << DE2_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ROUTE(bld_base),
- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
+ DE2_MIXER_BLEND_ROUTE(bld_base),
+ DE2_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
val);
}
}
@@ -114,8 +114,8 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
vphase += remainder << 16;
}
- insize = SUN8I_MIXER_SIZE(src_w, src_h);
- outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
+ insize = DE2_MIXER_SIZE(src_w, src_h);
+ outsize = DE2_MIXER_SIZE(dst_w, dst_h);
/* Set height and width */
DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
@@ -123,10 +123,10 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
(state->src.y1 >> 16) & ~(format->vsub - 1));
DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base, overlay),
+ DE2_MIXER_CHAN_VI_LAYER_SIZE(ch_base, overlay),
insize);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base),
+ DE2_MIXER_CHAN_VI_OVL_SIZE(ch_base),
insize);
/*
@@ -157,10 +157,10 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
state->dst.x1, state->dst.y1);
DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
- SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
+ DE2_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
+ DE2_MIXER_COORD(state->dst.x1, state->dst.y1));
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
+ DE2_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
outsize);
return 0;
@@ -181,10 +181,10 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
return -EINVAL;
}
- val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET;
+ val = fmt_info->de2_fmt << DE2_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
- SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
+ DE2_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
+ DE2_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
if (fmt_info->csc != SUN8I_CSC_MODE_OFF) {
sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc);
@@ -194,13 +194,13 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
}
if (fmt_info->rgb)
- val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
+ val = DE2_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
else
val = 0;
regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
- SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
+ DE2_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
+ DE2_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
return 0;
}
@@ -248,16 +248,16 @@ static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
i + 1, fb->pitches[i]);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base,
- overlay, i),
+ DE2_MIXER_CHAN_VI_LAYER_PITCH(ch_base,
+ overlay, i),
fb->pitches[i]);
DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
i + 1, &paddr);
regmap_write(mixer->engine.regs,
- SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base,
- overlay, i),
+ DE2_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base,
+ overlay, i),
lower_32_bits(paddr));
}
@@ -283,8 +283,8 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
max_scale = DRM_PLANE_HELPER_NO_SCALING;
if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
- min_scale = SUN8I_VI_SCALER_SCALE_MIN;
- max_scale = SUN8I_VI_SCALER_SCALE_MAX;
+ min_scale = DE2_VI_SCALER_SCALE_MIN;
+ max_scale = DE2_VI_SCALER_SCALE_MAX;
}
return drm_atomic_helper_check_plane_state(state, crtc_state,
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
index 46f0237c17bb..dfda659e309c 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
@@ -12,24 +12,24 @@
#include <drm/drm_plane.h>
-#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \
+#define DE2_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \
((base) + 0x30 * (layer) + 0x0)
-#define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \
+#define DE2_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \
((base) + 0x30 * (layer) + 0x4)
-#define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \
+#define DE2_MIXER_CHAN_VI_LAYER_COORD(base, layer) \
((base) + 0x30 * (layer) + 0x8)
-#define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \
+#define DE2_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \
((base) + 0x30 * (layer) + 0xc + 4 * (plane))
-#define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \
+#define DE2_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \
((base) + 0x30 * (layer) + 0x18 + 4 * (plane))
-#define SUN8I_MIXER_CHAN_VI_OVL_SIZE(base) \
+#define DE2_MIXER_CHAN_VI_OVL_SIZE(base) \
((base) + 0xe8)
-#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN BIT(0)
+#define DE2_MIXER_CHAN_VI_LAYER_ATTR_EN BIT(0)
/* RGB mode should be set for RGB formats and cleared for YCbCr */
-#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE BIT(15)
-#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET 8
-#define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)
+#define DE2_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE BIT(15)
+#define DE2_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET 8
+#define DE2_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)
struct sun8i_mixer;
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
index 9f6834c143d7..b69ebca221c3 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
@@ -842,7 +842,7 @@ static int sun8i_vi_scaler_coef_index(unsigned int step)
{
unsigned int scale, int_part, float_part;
- scale = step >> (SUN8I_VI_SCALER_SCALE_FRAC - 3);
+ scale = step >> (DE2_VI_SCALER_SCALE_FRAC - 3);
int_part = scale >> 3;
float_part = scale & 0x7;
@@ -880,24 +880,24 @@ static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base,
}
offset = sun8i_vi_scaler_coef_index(hstep) *
- SUN8I_VI_SCALER_COEFF_COUNT;
- for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) {
- regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, i),
+ DE2_VI_SCALER_COEFF_COUNT;
+ for (i = 0; i < DE2_VI_SCALER_COEFF_COUNT; i++) {
+ regmap_write(map, DE2_SCALER_VSU_YHCOEFF0(base, i),
lan3coefftab32_left[offset + i]);
- regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, i),
+ regmap_write(map, DE2_SCALER_VSU_YHCOEFF1(base, i),
lan3coefftab32_right[offset + i]);
- regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, i),
+ regmap_write(map, DE2_SCALER_VSU_CHCOEFF0(base, i),
ch_left[offset + i]);
- regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, i),
+ regmap_write(map, DE2_SCALER_VSU_CHCOEFF1(base, i),
ch_right[offset + i]);
}
offset = sun8i_vi_scaler_coef_index(hstep) *
- SUN8I_VI_SCALER_COEFF_COUNT;
- for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) {
- regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, i),
+ DE2_VI_SCALER_COEFF_COUNT;
+ for (i = 0; i < DE2_VI_SCALER_COEFF_COUNT; i++) {
+ regmap_write(map, DE2_SCALER_VSU_YVCOEFF(base, i),
lan2coefftab32[offset + i]);
- regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, i),
+ regmap_write(map, DE2_SCALER_VSU_CVCOEFF(base, i),
cy[offset + i]);
}
}
@@ -909,13 +909,12 @@ void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
base = sun8i_vi_scaler_base(mixer, layer);
if (enable)
- val = SUN8I_SCALER_VSU_CTRL_EN |
- SUN8I_SCALER_VSU_CTRL_COEFF_RDY;
+ val = DE2_SCALER_VSU_CTRL_EN | DE2_SCALER_VSU_CTRL_COEFF_RDY;
else
val = 0;
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CTRL(base), val);
+ DE2_SCALER_VSU_CTRL(base), val);
}
void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
@@ -929,13 +928,13 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
base = sun8i_vi_scaler_base(mixer, layer);
- hphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
- vphase <<= SUN8I_VI_SCALER_PHASE_FRAC - 16;
- hscale <<= SUN8I_VI_SCALER_SCALE_FRAC - 16;
- vscale <<= SUN8I_VI_SCALER_SCALE_FRAC - 16;
+ hphase <<= DE2_VI_SCALER_PHASE_FRAC - 16;
+ vphase <<= DE2_VI_SCALER_PHASE_FRAC - 16;
+ hscale <<= DE2_VI_SCALER_SCALE_FRAC - 16;
+ vscale <<= DE2_VI_SCALER_SCALE_FRAC - 16;
- insize = SUN8I_VI_SCALER_SIZE(src_w, src_h);
- outsize = SUN8I_VI_SCALER_SIZE(dst_w, dst_h);
+ insize = DE2_VI_SCALER_SIZE(src_w, src_h);
+ outsize = DE2_VI_SCALER_SIZE(dst_w, dst_h);
/*
* This is chroma V/H phase calculation as it appears in
@@ -945,38 +944,38 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
if (format->hsub == 2 && format->vsub == 2) {
chphase = hphase >> 1;
cvphase = (vphase >> 1) -
- (1UL << (SUN8I_VI_SCALER_SCALE_FRAC - 2));
+ (1UL << (DE2_VI_SCALER_SCALE_FRAC - 2));
} else {
chphase = hphase;
cvphase = vphase;
}
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_OUTSIZE(base), outsize);
+ DE2_SCALER_VSU_OUTSIZE(base), outsize);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YINSIZE(base), insize);
+ DE2_SCALER_VSU_YINSIZE(base), insize);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YHSTEP(base), hscale);
+ DE2_SCALER_VSU_YHSTEP(base), hscale);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YVSTEP(base), vscale);
+ DE2_SCALER_VSU_YVSTEP(base), vscale);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YHPHASE(base), hphase);
+ DE2_SCALER_VSU_YHPHASE(base), hphase);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_YVPHASE(base), vphase);
+ DE2_SCALER_VSU_YVPHASE(base), vphase);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CINSIZE(base),
- SUN8I_VI_SCALER_SIZE(src_w / format->hsub,
- src_h / format->vsub));
+ DE2_SCALER_VSU_CINSIZE(base),
+ DE2_VI_SCALER_SIZE(src_w / format->hsub,
+ src_h / format->vsub));
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CHSTEP(base),
+ DE2_SCALER_VSU_CHSTEP(base),
hscale / format->hsub);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CVSTEP(base),
+ DE2_SCALER_VSU_CVSTEP(base),
vscale / format->vsub);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CHPHASE(base), chphase);
+ DE2_SCALER_VSU_CHPHASE(base), chphase);
regmap_write(mixer->engine.regs,
- SUN8I_SCALER_VSU_CVPHASE(base), cvphase);
+ DE2_SCALER_VSU_CVPHASE(base), cvphase);
sun8i_vi_scaler_set_coeff(mixer->engine.regs, base,
hscale, vscale, format);
}
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
index f3de87122f07..b3168cae59b8 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
@@ -16,35 +16,35 @@
#define DE2_VI_SCALER_UNIT_SIZE 0x20000
/* this two macros assumes 16 fractional bits which is standard in DRM */
-#define SUN8I_VI_SCALER_SCALE_MIN 1
-#define SUN8I_VI_SCALER_SCALE_MAX ((1UL << 20) - 1)
-
-#define SUN8I_VI_SCALER_SCALE_FRAC 20
-#define SUN8I_VI_SCALER_PHASE_FRAC 20
-#define SUN8I_VI_SCALER_COEFF_COUNT 32
-#define SUN8I_VI_SCALER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
-
-#define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0)
-#define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40)
-#define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80)
-#define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88)
-#define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c)
-#define SUN8I_SCALER_VSU_YHPHASE(base) ((base) + 0x90)
-#define SUN8I_SCALER_VSU_YVPHASE(base) ((base) + 0x98)
-#define SUN8I_SCALER_VSU_CINSIZE(base) ((base) + 0xc0)
-#define SUN8I_SCALER_VSU_CHSTEP(base) ((base) + 0xc8)
-#define SUN8I_SCALER_VSU_CVSTEP(base) ((base) + 0xcc)
-#define SUN8I_SCALER_VSU_CHPHASE(base) ((base) + 0xd0)
-#define SUN8I_SCALER_VSU_CVPHASE(base) ((base) + 0xd8)
-#define SUN8I_SCALER_VSU_YHCOEFF0(base, i) ((base) + 0x200 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_YHCOEFF1(base, i) ((base) + 0x300 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_YVCOEFF(base, i) ((base) + 0x400 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_CHCOEFF0(base, i) ((base) + 0x600 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_CHCOEFF1(base, i) ((base) + 0x700 + 0x4 * (i))
-#define SUN8I_SCALER_VSU_CVCOEFF(base, i) ((base) + 0x800 + 0x4 * (i))
-
-#define SUN8I_SCALER_VSU_CTRL_EN BIT(0)
-#define SUN8I_SCALER_VSU_CTRL_COEFF_RDY BIT(4)
+#define DE2_VI_SCALER_SCALE_MIN 1
+#define DE2_VI_SCALER_SCALE_MAX ((1UL << 20) - 1)
+
+#define DE2_VI_SCALER_SCALE_FRAC 20
+#define DE2_VI_SCALER_PHASE_FRAC 20
+#define DE2_VI_SCALER_COEFF_COUNT 32
+#define DE2_VI_SCALER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
+
+#define DE2_SCALER_VSU_CTRL(base) ((base) + 0x0)
+#define DE2_SCALER_VSU_OUTSIZE(base) ((base) + 0x40)
+#define DE2_SCALER_VSU_YINSIZE(base) ((base) + 0x80)
+#define DE2_SCALER_VSU_YHSTEP(base) ((base) + 0x88)
+#define DE2_SCALER_VSU_YVSTEP(base) ((base) + 0x8c)
+#define DE2_SCALER_VSU_YHPHASE(base) ((base) + 0x90)
+#define DE2_SCALER_VSU_YVPHASE(base) ((base) + 0x98)
+#define DE2_SCALER_VSU_CINSIZE(base) ((base) + 0xc0)
+#define DE2_SCALER_VSU_CHSTEP(base) ((base) + 0xc8)
+#define DE2_SCALER_VSU_CVSTEP(base) ((base) + 0xcc)
+#define DE2_SCALER_VSU_CHPHASE(base) ((base) + 0xd0)
+#define DE2_SCALER_VSU_CVPHASE(base) ((base) + 0xd8)
+#define DE2_SCALER_VSU_YHCOEFF0(base, i) ((base) + 0x200 + 0x4 * (i))
+#define DE2_SCALER_VSU_YHCOEFF1(base, i) ((base) + 0x300 + 0x4 * (i))
+#define DE2_SCALER_VSU_YVCOEFF(base, i) ((base) + 0x400 + 0x4 * (i))
+#define DE2_SCALER_VSU_CHCOEFF0(base, i) ((base) + 0x600 + 0x4 * (i))
+#define DE2_SCALER_VSU_CHCOEFF1(base, i) ((base) + 0x700 + 0x4 * (i))
+#define DE2_SCALER_VSU_CVCOEFF(base, i) ((base) + 0x800 + 0x4 * (i))
+
+#define DE2_SCALER_VSU_CTRL_EN BIT(0)
+#define DE2_SCALER_VSU_CTRL_COEFF_RDY BIT(4)
void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable);
void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 11/29] drm/sun4i: Fix DE2 mixer size
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (9 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 10/29] drm/sun4i: Rename DE2 registers related macros Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 12/29] drm/sun4i: Disable unused DE2 sub-engines Jernej Skrabec
` (18 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
DE2 mixer is always 0x6000 bytes in size on all known SoCs.
While at it, introduce a macro for that.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 2 +-
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 71c0f6dc8a49..7beb3065a522 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -460,7 +460,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
base = sun8i_blender_base(mixer);
/* Reset the registers */
- for (i = 0x0; i < 0x20000; i += 4)
+ for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
regmap_write(mixer->engine.regs, i, 0);
/* Enable the mixer */
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 208e8219d2be..e2aa42e8f715 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -29,6 +29,8 @@
#define DE2_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
+#define DE2_MIXER_UNIT_SIZE 0x6000
+
#define DE2_BLD_BASE 0x1000
#define DE2_CH_BASE 0x2000
#define DE2_CH_SIZE 0x1000
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 12/29] drm/sun4i: Disable unused DE2 sub-engines
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (10 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 11/29] drm/sun4i: Fix DE2 mixer size Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 13/29] drm/sun4i: Add basic support for DE3 Jernej Skrabec
` (17 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Some sub-engines are unused. Disable them explicitly.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 8 ++++++++
drivers/gpu/drm/sun4i/sun8i_mixer.h | 4 ++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 7beb3065a522..2cb24d987005 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -462,6 +462,14 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
/* Reset the registers */
for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
regmap_write(mixer->engine.regs, i, 0);
+ /* Disable unused sub-engines */
+ regmap_write(mixer->engine.regs, DE2_MIXER_FCE_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_BWS_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_LTI_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_PEAK_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_ASE_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_FCC_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_DCSC_EN, 0);
/* Enable the mixer */
regmap_write(mixer->engine.regs, DE2_MIXER_GLOBAL_CTL,
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index e2aa42e8f715..f26ee6af6cba 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -101,8 +101,8 @@
#define DE2_MIXER_FBFMT_YUV411 14
/*
- * These sub-engines are still unknown now, the EN registers are here only to
- * be used to disable these sub-engines.
+ * Sub-engines listed bellow are unused for now. The EN registers are here only
+ * to be used to disable these sub-engines.
*/
#define DE2_MIXER_FCE_EN 0xa0000
#define DE2_MIXER_BWS_EN 0xa2000
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 13/29] drm/sun4i: Add basic support for DE3
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (11 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 12/29] drm/sun4i: Disable unused DE2 sub-engines Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 14/29] drm/sun4i: Add support for H6 DE3 mixer 0 Jernej Skrabec
` (16 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Display Engine 3 is an upgrade of DE2 with new features like support for
10 bit color formats and support for AFBC.
Most of DE2 code works with DE3, except some small details.
Implement basic support for DE3. Support for 10 bit colort formats and
AFBC, among others missing features, will be added later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_csc.c | 83 +++++++++++++++++++++++++
drivers/gpu/drm/sun4i/sun8i_mixer.c | 38 +++++++----
drivers/gpu/drm/sun4i/sun8i_mixer.h | 33 +++++++++-
drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 10 ++-
drivers/gpu/drm/sun4i/sun8i_ui_scaler.h | 1 +
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 8 +++
drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 2 +
drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 19 +++++-
drivers/gpu/drm/sun4i/sun8i_vi_scaler.h | 23 +++++++
9 files changed, 201 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
index 755b60bae408..e0e8bf263792 100644
--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
@@ -34,6 +34,41 @@ static const u32 yvu2rgb[] = {
0x000004A8, 0x00000000, 0x00000813, 0xFFFBAC4A,
};
+/*
+ * DE3 has a bit different CSC units. Factors are in two's complement format.
+ * First three factors in a row are multiplication factors which have 17 bits
+ * for fractional part. Fourth value in a row is comprised of two factors.
+ * Upper 16 bits represents difference, which is subtracted from the input
+ * value before multiplication and lower 16 bits represents constant, which
+ * is addes at the end.
+ *
+ * x' = c00 * (x + d0) + c01 * (y + d1) + c02 * (z + d2) + const0
+ * y' = c10 * (x + d0) + c11 * (y + d1) + c12 * (z + d2) + const1
+ * z' = c20 * (x + d0) + c21 * (y + d1) + c22 * (z + d2) + const2
+ *
+ * Please note that above formula is true only for Blender CSC. Other DE3 CSC
+ * units takes only positive value for difference. From what can be deducted
+ * from BSP driver code, those units probably automatically assume that
+ * difference has to be subtracted.
+ *
+ * Layout of factors in table:
+ * c00 c01 c02 [d0 const0]
+ * c10 c11 c12 [d1 const1]
+ * c20 c21 c22 [d2 const2]
+ */
+
+static const u32 yuv2rgb_de3[] = {
+ 0x0002542a, 0x00000000, 0x0003312a, 0xffc00000,
+ 0x0002542a, 0xffff376b, 0xfffe5fc3, 0xfe000000,
+ 0x0002542a, 0x000408d3, 0x00000000, 0xfe000000,
+};
+
+static const u32 yvu2rgb_de3[] = {
+ 0x0002542a, 0x0003312a, 0x00000000, 0xffc00000,
+ 0x0002542a, 0xfffe5fc3, 0xffff376b, 0xfe000000,
+ 0x0002542a, 0x00000000, 0x000408d3, 0xfe000000,
+};
+
static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
enum sun8i_csc_mode mode)
{
@@ -61,6 +96,28 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
}
}
+static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
+ enum sun8i_csc_mode mode)
+{
+ const u32 *table;
+ u32 base_reg;
+
+ switch (mode) {
+ case SUN8I_CSC_MODE_YUV2RGB:
+ table = yuv2rgb_de3;
+ break;
+ case SUN8I_CSC_MODE_YVU2RGB:
+ table = yvu2rgb_de3;
+ break;
+ default:
+ DRM_WARN("Wrong CSC mode specified.\n");
+ return;
+ }
+
+ base_reg = DE3_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0, 0);
+ regmap_bulk_write(map, base_reg, table, 12);
+}
+
static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable)
{
u32 val;
@@ -73,11 +130,32 @@ static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable)
regmap_update_bits(map, DE2_CSC_CTRL(base), DE2_CSC_CTRL_EN, val);
}
+static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable)
+{
+ u32 val, mask;
+
+ mask = DE3_MIXER_BLEND_CSC_CTL_EN(layer);
+
+ if (enable)
+ val = mask;
+ else
+ val = 0;
+
+ regmap_update_bits(map, DE3_MIXER_BLEND_CSC_CTL(DE3_BLD_BASE),
+ mask, val);
+}
+
void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
enum sun8i_csc_mode mode)
{
u32 base;
+ if (mixer->cfg->is_de3) {
+ sun8i_de3_ccsc_set_coefficients(mixer->engine.regs,
+ layer, mode);
+ return;
+ }
+
base = ccsc_base[mixer->cfg->ccsc][layer];
sun8i_csc_set_coefficients(mixer->engine.regs, base, mode);
@@ -87,6 +165,11 @@ void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
{
u32 base;
+ if (mixer->cfg->is_de3) {
+ sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable);
+ return;
+ }
+
base = ccsc_base[mixer->cfg->ccsc][layer];
sun8i_csc_enable(mixer->engine.regs, base, enable);
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 2cb24d987005..64daeb017d10 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -459,17 +459,33 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
base = sun8i_blender_base(mixer);
- /* Reset the registers */
- for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
- regmap_write(mixer->engine.regs, i, 0);
- /* Disable unused sub-engines */
- regmap_write(mixer->engine.regs, DE2_MIXER_FCE_EN, 0);
- regmap_write(mixer->engine.regs, DE2_MIXER_BWS_EN, 0);
- regmap_write(mixer->engine.regs, DE2_MIXER_LTI_EN, 0);
- regmap_write(mixer->engine.regs, DE2_MIXER_PEAK_EN, 0);
- regmap_write(mixer->engine.regs, DE2_MIXER_ASE_EN, 0);
- regmap_write(mixer->engine.regs, DE2_MIXER_FCC_EN, 0);
- regmap_write(mixer->engine.regs, DE2_MIXER_DCSC_EN, 0);
+ /* Reset registers and disable unused sub-engines */
+ if (mixer->cfg->is_de3) {
+ for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
+ regmap_write(mixer->engine.regs, i, 0);
+
+ regmap_write(mixer->engine.regs, DE3_MIXER_FCE_EN, 0);
+ regmap_write(mixer->engine.regs, DE3_MIXER_PEAK_EN, 0);
+ regmap_write(mixer->engine.regs, DE3_MIXER_LCTI_EN, 0);
+ regmap_write(mixer->engine.regs, DE3_MIXER_BLS_EN, 0);
+ regmap_write(mixer->engine.regs, DE3_MIXER_FCC_EN, 0);
+ regmap_write(mixer->engine.regs, DE3_MIXER_DNS_EN, 0);
+ regmap_write(mixer->engine.regs, DE3_MIXER_DRC_EN, 0);
+ regmap_write(mixer->engine.regs, DE3_MIXER_FMT_EN, 0);
+ regmap_write(mixer->engine.regs, DE3_MIXER_CDC0_EN, 0);
+ regmap_write(mixer->engine.regs, DE3_MIXER_CDC1_EN, 0);
+ } else {
+ for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
+ regmap_write(mixer->engine.regs, i, 0);
+
+ regmap_write(mixer->engine.regs, DE2_MIXER_FCE_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_BWS_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_LTI_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_PEAK_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_ASE_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_FCC_EN, 0);
+ regmap_write(mixer->engine.regs, DE2_MIXER_DCSC_EN, 0);
+ }
/* Enable the mixer */
regmap_write(mixer->engine.regs, DE2_MIXER_GLOBAL_CTL,
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index f26ee6af6cba..4dcc85f0a53e 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -30,11 +30,16 @@
#define DE2_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
#define DE2_MIXER_UNIT_SIZE 0x6000
+#define DE3_MIXER_UNIT_SIZE 0x3000
#define DE2_BLD_BASE 0x1000
#define DE2_CH_BASE 0x2000
#define DE2_CH_SIZE 0x1000
+#define DE3_BLD_BASE 0x0800
+#define DE3_CH_BASE 0x1000
+#define DE3_CH_SIZE 0x0800
+
#define DE2_MIXER_BLEND_PIPE_CTL(base) ((base) + 0)
#define DE2_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x))
#define DE2_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x))
@@ -49,6 +54,11 @@
#define DE2_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x))
#define DE2_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x))
#define DE2_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc)
+#define DE3_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100)
+#define DE3_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \
+ ((base) + 0x110 + (layer) * 0x30 + (x) * 0x10 + 4 * (y))
+#define DE3_MIXER_BLEND_CSC_CONST(base, layer, i) \
+ ((base) + 0x110 + (layer) * 0x30 + (i) * 0x10 + 0x0c)
#define DE2_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
#define DE2_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
@@ -63,6 +73,9 @@
#define DE2_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
+#define DE3_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch)
+#define DE3_MIXER_BLEND_CSC_CONST_VAL(d, c) (((d) << 16) | ((c) & 0xffff))
+
#define DE2_MIXER_FBFMT_ARGB8888 0
#define DE2_MIXER_FBFMT_ABGR8888 1
#define DE2_MIXER_FBFMT_RGBA8888 2
@@ -112,6 +125,17 @@
#define DE2_MIXER_FCC_EN 0xaa000
#define DE2_MIXER_DCSC_EN 0xb0000
+#define DE3_MIXER_FCE_EN 0x70000
+#define DE3_MIXER_PEAK_EN 0x70800
+#define DE3_MIXER_LCTI_EN 0x71000
+#define DE3_MIXER_BLS_EN 0x71800
+#define DE3_MIXER_FCC_EN 0x72000
+#define DE3_MIXER_DNS_EN 0x80000
+#define DE3_MIXER_DRC_EN 0xa0000
+#define DE3_MIXER_FMT_EN 0xa8000
+#define DE3_MIXER_CDC0_EN 0xd0000
+#define DE3_MIXER_CDC1_EN 0xd8000
+
struct de2_fmt_info {
u32 drm_fmt;
u32 de2_fmt;
@@ -133,6 +157,7 @@ struct de2_fmt_info {
* are invalid.
* @mod_rate: module clock rate that needs to be set in order to have
* a functional block.
+ * @is_de3: true, if this is next gen display engine 3.0, false otherwise.
*/
struct sun8i_mixer_cfg {
int vi_num;
@@ -140,6 +165,7 @@ struct sun8i_mixer_cfg {
int scaler_mask;
int ccsc;
unsigned long mod_rate;
+ bool is_de3;
};
struct sun8i_mixer {
@@ -162,13 +188,16 @@ engine_to_sun8i_mixer(struct sunxi_engine *engine)
static inline u32
sun8i_blender_base(struct sun8i_mixer *mixer)
{
- return DE2_BLD_BASE;
+ return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
}
static inline u32
sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
{
- return DE2_CH_BASE + channel * DE2_CH_SIZE;
+ if (mixer->cfg->is_de3)
+ return DE3_CH_BASE + channel * DE3_CH_SIZE;
+ else
+ return DE2_CH_BASE + channel * DE2_CH_SIZE;
}
const struct de2_fmt_info *sun8i_mixer_format_info(u32 format);
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
index 59dfe2deae8f..680b4ee08ab0 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
@@ -93,8 +93,14 @@ static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel)
{
int vi_num = mixer->cfg->vi_num;
- return DE2_VI_SCALER_UNIT_BASE + DE2_VI_SCALER_UNIT_SIZE * vi_num +
- DE2_UI_SCALER_UNIT_SIZE * (channel - vi_num);
+ if (mixer->cfg->is_de3)
+ return DE3_VI_SCALER_UNIT_BASE +
+ DE3_VI_SCALER_UNIT_SIZE * vi_num +
+ DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num);
+ else
+ return DE2_VI_SCALER_UNIT_BASE +
+ DE2_VI_SCALER_UNIT_SIZE * vi_num +
+ DE2_UI_SCALER_UNIT_SIZE * (channel - vi_num);
}
static int sun8i_ui_scaler_coef_index(unsigned int step)
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
index 8db18053e6ee..427241ff1f47 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
@@ -12,6 +12,7 @@
#include "sun8i_mixer.h"
#define DE2_UI_SCALER_UNIT_SIZE 0x10000
+#define DE3_UI_SCALER_UNIT_SIZE 0x08000
/* this two macros assumes 16 fractional bits which is standard in DRM */
#define DE2_UI_SCALER_SCALE_MIN 1
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index 8ea07f34ad5b..7b7ac8bdf75f 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -202,6 +202,14 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
DE2_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
DE2_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
+ /* It seems that YUV formats use global alpha setting. */
+ if (mixer->cfg->is_de3)
+ regmap_update_bits(mixer->engine.regs,
+ DE2_MIXER_CHAN_VI_LAYER_ATTR(ch_base,
+ overlay),
+ DE3_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK,
+ DE3_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(0xff));
+
return 0;
}
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
index dfda659e309c..eb3988a153f9 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h
@@ -30,6 +30,8 @@
#define DE2_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE BIT(15)
#define DE2_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET 8
#define DE2_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)
+#define DE3_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24)
+#define DE3_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(x) ((x) << 24)
struct sun8i_mixer;
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
index b69ebca221c3..b1953569cccb 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
@@ -835,7 +835,12 @@ static const u32 bicubic4coefftab32[480] = {
static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
{
- return DE2_VI_SCALER_UNIT_BASE + DE2_VI_SCALER_UNIT_SIZE * channel;
+ if (mixer->cfg->is_de3)
+ return DE3_VI_SCALER_UNIT_BASE +
+ DE3_VI_SCALER_UNIT_SIZE * channel;
+ else
+ return DE2_VI_SCALER_UNIT_BASE +
+ DE2_VI_SCALER_UNIT_SIZE * channel;
}
static int sun8i_vi_scaler_coef_index(unsigned int step)
@@ -950,6 +955,18 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
cvphase = vphase;
}
+ if (mixer->cfg->is_de3) {
+ u32 val;
+
+ if (format->hsub == 1 && format->vsub == 1)
+ val = DE3_SCALER_VSU_SCALE_MODE_UI;
+ else
+ val = DE3_SCALER_VSU_SCALE_MODE_NORMAL;
+
+ regmap_write(mixer->engine.regs,
+ DE3_SCALER_VSU_SCALE_MODE(base), val);
+ }
+
regmap_write(mixer->engine.regs,
DE2_SCALER_VSU_OUTSIZE(base), outsize);
regmap_write(mixer->engine.regs,
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
index b3168cae59b8..a9cf4b1ce642 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
@@ -15,6 +15,9 @@
#define DE2_VI_SCALER_UNIT_BASE 0x20000
#define DE2_VI_SCALER_UNIT_SIZE 0x20000
+#define DE3_VI_SCALER_UNIT_BASE 0x20000
+#define DE3_VI_SCALER_UNIT_SIZE 0x08000
+
/* this two macros assumes 16 fractional bits which is standard in DRM */
#define DE2_VI_SCALER_SCALE_MIN 1
#define DE2_VI_SCALER_SCALE_MAX ((1UL << 20) - 1)
@@ -25,6 +28,11 @@
#define DE2_VI_SCALER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
#define DE2_SCALER_VSU_CTRL(base) ((base) + 0x0)
+#define DE3_SCALER_VSU_SCALE_MODE(base) ((base) + 0x10)
+#define DE3_SCALER_VSU_DIR_THR(base) ((base) + 0x20)
+#define DE3_SCALER_VSU_EDGE_THR(base) ((base) + 0x24)
+#define DE3_SCALER_VSU_EDSCL_CTRL(base) ((base) + 0x28)
+#define DE3_SCALER_VSU_ANGLE_THR(base) ((base) + 0x2c)
#define DE2_SCALER_VSU_OUTSIZE(base) ((base) + 0x40)
#define DE2_SCALER_VSU_YINSIZE(base) ((base) + 0x80)
#define DE2_SCALER_VSU_YHSTEP(base) ((base) + 0x88)
@@ -46,6 +54,21 @@
#define DE2_SCALER_VSU_CTRL_EN BIT(0)
#define DE2_SCALER_VSU_CTRL_COEFF_RDY BIT(4)
+#define DE3_SCALER_VSU_SUB_ZERO_DIR_THR(x) (((x) << 24) & 0xFF)
+#define DE3_SCALER_VSU_ZERO_DIR_THR(x) (((x) << 16) & 0xFF)
+#define DE3_SCALER_VSU_HORZ_DIR_THR(x) (((x) << 8) & 0xFF)
+#define DE3_SCALER_VSU_VERT_DIR_THR(x) ((x) & 0xFF)
+
+#define DE3_SCALER_VSU_SCALE_MODE_UI 0
+#define DE3_SCALER_VSU_SCALE_MODE_NORMAL 1
+#define DE3_SCALER_VSU_SCALE_MODE_ED_SCALE 2
+
+#define DE3_SCALER_VSU_EDGE_SHIFT(x) (((x) << 16) & 0xF)
+#define DE3_SCALER_VSU_EDGE_OFFSET(x) ((x) & 0xFF)
+
+#define DE3_SCALER_VSU_ANGLE_SHIFT(x) (((x) << 16) & 0xF)
+#define DE3_SCALER_VSU_ANGLE_OFFSET(x) ((x) & 0xFF)
+
void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable);
void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 14/29] drm/sun4i: Add support for H6 DE3 mixer 0
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (12 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 13/29] drm/sun4i: Add basic support for DE3 Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 15/29] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a Jernej Skrabec
` (15 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Mixer 0 has 1 VI and 3 UI planes, scaler on all planes and can output
4K image @60Hz. It also support 10 bit colors, which are not yet
implemented.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 64daeb017d10..ace8b6cb8a8b 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -613,6 +613,15 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
.vi_num = 1,
};
+static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
+ .ccsc = 0,
+ .is_de3 = true,
+ .mod_rate = 600000000,
+ .scaler_mask = 0xf,
+ .ui_num = 3,
+ .vi_num = 1,
+};
+
static const struct of_device_id sun8i_mixer_of_table[] = {
{
.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
@@ -646,6 +655,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun50i-a64-de2-mixer-1",
.data = &sun50i_a64_mixer1_cfg,
},
+ {
+ .compatible = "allwinner,sun50i-h6-de3-mixer-0",
+ .data = &sun50i_h6_mixer0_cfg,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 15/29] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (13 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 14/29] drm/sun4i: Add support for H6 DE3 mixer 0 Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-09 17:40 ` Laurent Pinchart
2018-10-07 9:38 ` [PATCH v2 16/29] drm/sun4i: Not all DW HDMI controllers has scrambled addresses Jernej Skrabec
` (14 subsequent siblings)
29 siblings, 1 reply; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
It turns out that even new DW HDMI controllers exhibits same magenta
line issues as older versions.
Enable workaround for v2.12a.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 5971976284bf..df1c7a2d6961 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1664,6 +1664,7 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
case 0x131a:
case 0x132a:
case 0x201a:
+ case 0x212a:
count = 1;
break;
default:
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 16/29] drm/sun4i: Not all DW HDMI controllers has scrambled addresses
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (14 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 15/29] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 17/29] drm/sun4i: dw-hdmi: Make mode_valid function configurable Jernej Skrabec
` (13 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Currently supported Allwinner SoCs with DW HDMI controller have
scrambled addresses and read lock. However, that is not true in general.
For example, A80 and H6 have normal addresses and normal read access.
Move code for unscrambling addresses and unlocking read access to it's
own function and call it from init function.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 23 +++++++++++++++--------
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 471993097ced..365cb5a9fb77 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -279,8 +279,21 @@ static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = {
.setup_hpd = &dw_hdmi_phy_setup_hpd,
};
+static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)
+{
+ /* enable read access to HDMI controller */
+ regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
+ SUN8I_HDMI_PHY_READ_EN_MAGIC);
+
+ /* unscramble register offsets */
+ regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
+ SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
+}
+
static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy)
{
+ sun8i_hdmi_phy_unlock(phy);
+
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,
SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);
@@ -298,6 +311,8 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)
{
unsigned int val;
+ sun8i_hdmi_phy_unlock(phy);
+
regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0);
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
SUN8I_HDMI_PHY_ANA_CFG1_ENBI,
@@ -372,14 +387,6 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)
void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
{
- /* enable read access to HDMI controller */
- regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
- SUN8I_HDMI_PHY_READ_EN_MAGIC);
-
- /* unscramble register offsets */
- regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
- SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
-
phy->variant->phy_init(phy);
}
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 17/29] drm/sun4i: dw-hdmi: Make mode_valid function configurable
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (15 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 16/29] drm/sun4i: Not all DW HDMI controllers has scrambled addresses Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 18/29] drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock Jernej Skrabec
` (12 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Since it is not possible to access sun8i-dw-hdmi driver private data
inside mode_valid function, make it configurable. That way different
versions of HDMI controllers can set different function, depending on
it's limitations.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 18 ++++++++++++++----
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 6 ++++++
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index ed2983770e9c..ec122136ee9d 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -5,6 +5,7 @@
#include <linux/component.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <drm/drm_of.h>
@@ -33,8 +34,8 @@ static const struct drm_encoder_funcs sun8i_dw_hdmi_encoder_funcs = {
};
static enum drm_mode_status
-sun8i_dw_hdmi_mode_valid(struct drm_connector *connector,
- const struct drm_display_mode *mode)
+sun8i_dw_hdmi_mode_valid_a83t(struct drm_connector *connector,
+ const struct drm_display_mode *mode)
{
if (mode->clock > 297000)
return MODE_CLOCK_HIGH;
@@ -102,6 +103,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
hdmi->dev = &pdev->dev;
encoder = &hdmi->encoder;
+ hdmi->quirks = of_device_get_match_data(dev);
+
encoder->possible_crtcs =
sun8i_dw_hdmi_find_possible_crtcs(drm, dev->of_node);
/*
@@ -168,7 +171,7 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
sun8i_hdmi_phy_init(hdmi->phy);
- plat_data->mode_valid = &sun8i_dw_hdmi_mode_valid;
+ plat_data->mode_valid = hdmi->quirks->mode_valid;
plat_data->phy_ops = sun8i_hdmi_phy_get_ops();
plat_data->phy_name = "sun8i_dw_hdmi_phy";
plat_data->phy_data = hdmi->phy;
@@ -230,8 +233,15 @@ static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
return 0;
}
+static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
+ .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
+};
+
static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
- { .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
+ {
+ .compatible = "allwinner,sun8i-a83t-dw-hdmi",
+ .data = &sun8i_a83t_quirks,
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids);
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index 7fdc1ecd2892..a645b8bc9f58 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -170,6 +170,11 @@ struct sun8i_hdmi_phy {
struct sun8i_hdmi_phy_variant *variant;
};
+struct sun8i_dw_hdmi_quirks {
+ enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
+ const struct drm_display_mode *mode);
+};
+
struct sun8i_dw_hdmi {
struct clk *clk_tmds;
struct device *dev;
@@ -178,6 +183,7 @@ struct sun8i_dw_hdmi {
struct sun8i_hdmi_phy *phy;
struct dw_hdmi_plat_data plat_data;
struct regulator *regulator;
+ const struct sun8i_dw_hdmi_quirks *quirks;
struct reset_control *rst_ctrl;
};
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 18/29] drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (16 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 17/29] drm/sun4i: dw-hdmi: Make mode_valid function configurable Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-08 9:14 ` Maxime Ripard
2018-10-07 9:38 ` [PATCH v2 19/29] dt-bindings: display: sunxi: add DT binding for Allwinner H6 DW HDMI Jernej Skrabec
` (11 subsequent siblings)
29 siblings, 1 reply; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
It turns out that H6 HDMI BSP kernel driver doesn't change TMDS rate at
all. At this point it is not clear whether it is just not necessary or
it would cause some kind of issues.
Add a quirk for it.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 5 ++++-
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index ec122136ee9d..e9e93f174b35 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -165,7 +165,9 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
goto err_disable_clk_tmds;
}
- drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
+ if (hdmi->quirks->set_rate)
+ drm_encoder_helper_add(encoder,
+ &sun8i_dw_hdmi_encoder_helper_funcs);
drm_encoder_init(drm, encoder, &sun8i_dw_hdmi_encoder_funcs,
DRM_MODE_ENCODER_TMDS, NULL);
@@ -235,6 +237,7 @@ static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
+ .set_rate = true,
};
static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index a645b8bc9f58..f9eb663865a4 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -173,6 +173,7 @@ struct sun8i_hdmi_phy {
struct sun8i_dw_hdmi_quirks {
enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
const struct drm_display_mode *mode);
+ bool set_rate;
};
struct sun8i_dw_hdmi {
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 19/29] dt-bindings: display: sunxi: add DT binding for Allwinner H6 DW HDMI
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (17 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 18/29] drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 20/29] drm/sun4i: Add support for H6 DW HDMI controller Jernej Skrabec
` (10 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The Allwinner H6 SoC uses a v2.12a DesignWare HDMI controller, with
dedicated CEC and HDCP clocks added; the PHY connected is a standard
DesignWare HDMI PHY.
Add binding for it.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[added HDCP clock and reset]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 62c83b351344..478b288eebd9 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -79,6 +79,7 @@ Required properties:
- compatible: value must be one of:
* "allwinner,sun8i-a83t-dw-hdmi"
* "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"
+ * "allwinner,sun50i-h6-dw-hdmi"
- reg: base address and size of memory-mapped region
- reg-io-width: See dw_hdmi.txt. Shall be 1.
- interrupts: HDMI interrupt number
@@ -86,9 +87,14 @@ Required properties:
* iahb: the HDMI bus clock
* isfr: the HDMI register clock
* tmds: TMDS clock
+ * cec: HDMI CEC clock (H6 only)
+ * hdcp: HDCP clock (H6 only)
+ * hdcp-bus: HDCP bus clock (H6 only)
- clock-names: the clock names mentioned above
- - resets: phandle to the reset controller
- - reset-names: must be "ctrl"
+ - resets:
+ * ctrl: HDMI controller reset
+ * hdcp: HDCP reset (H6 only)
+ - reset-names: reset names mentioned above
- phys: phandle to the DWC HDMI PHY
- phy-names: must be "phy"
@@ -109,6 +115,7 @@ Required properties:
* allwinner,sun8i-h3-hdmi-phy
* allwinner,sun8i-r40-hdmi-phy
* allwinner,sun50i-a64-hdmi-phy
+ * allwinner,sun50i-h6-hdmi-phy
- reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the HDMI PHY
* bus: the HDMI PHY interface clock
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 20/29] drm/sun4i: Add support for H6 DW HDMI controller
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (18 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 19/29] dt-bindings: display: sunxi: add DT binding for Allwinner H6 DW HDMI Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 21/29] drm/sun4i: dw-hdmi-phy: Reorder quirks by family Jernej Skrabec
` (9 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
H6 has DW HDMI 2.0b controller v2.12a.
It supports 4K at 60 Hz and HDCP 2.2.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index e9e93f174b35..0306a51e1b35 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -43,6 +43,17 @@ sun8i_dw_hdmi_mode_valid_a83t(struct drm_connector *connector,
return MODE_OK;
}
+static enum drm_mode_status
+sun8i_dw_hdmi_mode_valid_h6(struct drm_connector *connector,
+ const struct drm_display_mode *mode)
+{
+ /* This is max for HDMI 2.0b (4K@60Hz) */
+ if (mode->clock > 594000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static bool sun8i_dw_hdmi_node_is_tcon_top(struct device_node *node)
{
return IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
@@ -240,11 +251,19 @@ static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
.set_rate = true,
};
+static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
+ .mode_valid = sun8i_dw_hdmi_mode_valid_h6,
+};
+
static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
{
.compatible = "allwinner,sun8i-a83t-dw-hdmi",
.data = &sun8i_a83t_quirks,
},
+ {
+ .compatible = "allwinner,sun50i-h6-dw-hdmi",
+ .data = &sun50i_h6_quirks,
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids);
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 21/29] drm/sun4i: dw-hdmi-phy: Reorder quirks by family
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (19 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 20/29] drm/sun4i: Add support for H6 DW HDMI controller Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 22/29] drm/sun4i: Add support for Synopsys HDMI PHY Jernej Skrabec
` (8 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Currently, quirks and compatibles are sorted alphabetically. However,
they should be sorted by family release date and then alphabetically.
Fix that by moving A64 quirks and compatible to bottom. No functional
change is made.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 365cb5a9fb77..adc3ba7df7e3 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -403,13 +403,6 @@ static struct regmap_config sun8i_hdmi_phy_regmap_config = {
.name = "phy"
};
-static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
- .has_phy_clk = true,
- .phy_init = &sun8i_hdmi_phy_init_h3,
- .phy_disable = &sun8i_hdmi_phy_disable_h3,
- .phy_config = &sun8i_hdmi_phy_config_h3,
-};
-
static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
.phy_init = &sun8i_hdmi_phy_init_a83t,
.phy_disable = &sun8i_hdmi_phy_disable_a83t,
@@ -431,11 +424,14 @@ static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
.phy_config = &sun8i_hdmi_phy_config_h3,
};
+static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
+ .has_phy_clk = true,
+ .phy_init = &sun8i_hdmi_phy_init_h3,
+ .phy_disable = &sun8i_hdmi_phy_disable_h3,
+ .phy_config = &sun8i_hdmi_phy_config_h3,
+};
+
static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
- {
- .compatible = "allwinner,sun50i-a64-hdmi-phy",
- .data = &sun50i_a64_hdmi_phy,
- },
{
.compatible = "allwinner,sun8i-a83t-hdmi-phy",
.data = &sun8i_a83t_hdmi_phy,
@@ -448,6 +444,10 @@ static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
.compatible = "allwinner,sun8i-r40-hdmi-phy",
.data = &sun8i_r40_hdmi_phy,
},
+ {
+ .compatible = "allwinner,sun50i-a64-hdmi-phy",
+ .data = &sun50i_a64_hdmi_phy,
+ },
{ /* sentinel */ }
};
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 22/29] drm/sun4i: Add support for Synopsys HDMI PHY
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (20 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 21/29] drm/sun4i: dw-hdmi-phy: Reorder quirks by family Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 23/29] drm/sun4i: Add support for H6 " Jernej Skrabec
` (7 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Currently sun8i-hdmi-phy driver supports only custom PHYs connected to
DW HDMI controller. Since newest Allwinner SoCs have unmodified Synopsys
PHY, driver has to be reorganized to support them.
Variant structure is expanded to allow differentiation between custom
and Sysnopsys PHYs and to hold Synopsys PHY settings.
Since DW HDMI bridge platform data has different fields for custom and
Sysnopsys PHY, function sun8i_hdmi_phy_get_ops() is replaced with
sun8i_hdmi_phy_set_ops().
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 4 +---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 7 ++++++-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 19 +++++++++++++++++--
3 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index 0306a51e1b35..492c938f119d 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -185,9 +185,7 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
sun8i_hdmi_phy_init(hdmi->phy);
plat_data->mode_valid = hdmi->quirks->mode_valid;
- plat_data->phy_ops = sun8i_hdmi_phy_get_ops();
- plat_data->phy_name = "sun8i_dw_hdmi_phy";
- plat_data->phy_data = hdmi->phy;
+ sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data);
platform_set_drvdata(pdev, hdmi);
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index f9eb663865a4..37646ff9a7a2 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -150,6 +150,10 @@ struct sun8i_hdmi_phy;
struct sun8i_hdmi_phy_variant {
bool has_phy_clk;
bool has_second_pll;
+ bool is_custom_phy;
+ const struct dw_hdmi_curr_ctrl *cur_ctr;
+ const struct dw_hdmi_mpll_config *mpll_cfg;
+ const struct dw_hdmi_phy_config *phy_cfg;
void (*phy_init)(struct sun8i_hdmi_phy *phy);
void (*phy_disable)(struct dw_hdmi *hdmi,
struct sun8i_hdmi_phy *phy);
@@ -198,7 +202,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node);
void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
-const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
+void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
+ struct dw_hdmi_plat_data *plat_data);
int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
bool second_parent);
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index adc3ba7df7e3..635825b55648 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -390,9 +390,20 @@ void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
phy->variant->phy_init(phy);
}
-const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void)
+void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
+ struct dw_hdmi_plat_data *plat_data)
{
- return &sun8i_hdmi_phy_ops;
+ struct sun8i_hdmi_phy_variant *variant = phy->variant;
+
+ if (variant->is_custom_phy) {
+ plat_data->phy_ops = &sun8i_hdmi_phy_ops;
+ plat_data->phy_name = "sun8i_dw_hdmi_phy";
+ plat_data->phy_data = phy;
+ } else {
+ plat_data->mpll_cfg = variant->mpll_cfg;
+ plat_data->cur_ctr = variant->cur_ctr;
+ plat_data->phy_config = variant->phy_cfg;
+ }
}
static struct regmap_config sun8i_hdmi_phy_regmap_config = {
@@ -404,6 +415,7 @@ static struct regmap_config sun8i_hdmi_phy_regmap_config = {
};
static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
+ .is_custom_phy = true,
.phy_init = &sun8i_hdmi_phy_init_a83t,
.phy_disable = &sun8i_hdmi_phy_disable_a83t,
.phy_config = &sun8i_hdmi_phy_config_a83t,
@@ -411,6 +423,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
.has_phy_clk = true,
+ .is_custom_phy = true,
.phy_init = &sun8i_hdmi_phy_init_h3,
.phy_disable = &sun8i_hdmi_phy_disable_h3,
.phy_config = &sun8i_hdmi_phy_config_h3,
@@ -419,6 +432,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
.has_phy_clk = true,
.has_second_pll = true,
+ .is_custom_phy = true,
.phy_init = &sun8i_hdmi_phy_init_h3,
.phy_disable = &sun8i_hdmi_phy_disable_h3,
.phy_config = &sun8i_hdmi_phy_config_h3,
@@ -426,6 +440,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
.has_phy_clk = true,
+ .is_custom_phy = true,
.phy_init = &sun8i_hdmi_phy_init_h3,
.phy_disable = &sun8i_hdmi_phy_disable_h3,
.phy_config = &sun8i_hdmi_phy_config_h3,
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 23/29] drm/sun4i: Add support for H6 HDMI PHY
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (21 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 22/29] drm/sun4i: Add support for Synopsys HDMI PHY Jernej Skrabec
@ 2018-10-07 9:38 ` Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 24/29] drm/sun4i: Initialize registers in tcon-top driver Jernej Skrabec
` (6 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:38 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
H6 has Synopsys DWC HDMI 2.0 TX PHY.
There is no freely available documentation for it, only code found in
BSP kernel. However, judging by the code, PHY is very similar to older
Synopsys HDMI PHY described in i.MX6 documentation. Most registers seem
to be the same.
According to i.MX6 documentation, mpll settings are based on pixel clock
and are not specific to each SoC. Because of that, mpll table in this
commit is based on that documentation and not on BSP code. Other PHY
settings were derived from BSP PHY driver code.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 137 +++++++++++++++++++++++++
1 file changed, 137 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 635825b55648..66ea3a902e36 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -14,6 +14,122 @@
*/
#define I2C_ADDR 0x69
+static const struct dw_hdmi_mpll_config sun50i_h6_mpll_cfg[] = {
+ {
+ 30666000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40f3, 0x0000 },
+ },
+ }, {
+ 36800000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40a2, 0x0001 },
+ },
+ }, {
+ 46000000, {
+ { 0x00b3, 0x0000 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
+ },
+ }, {
+ 61333000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
+ },
+ }, {
+ 73600000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x4061, 0x0002 },
+ },
+ }, {
+ 92000000, {
+ { 0x0072, 0x0001 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
+ },
+ }, {
+ 122666000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
+ },
+ }, {
+ 147200000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4064, 0x0003 },
+ },
+ }, {
+ 184000000, {
+ { 0x0051, 0x0002 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
+ },
+ }, {
+ 226666000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
+ },
+ }, {
+ 272000000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
+ 340000000, {
+ { 0x0040, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
+ 594000000, {
+ { 0x1a40, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
+ ~0UL, {
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ },
+ }
+};
+
+static const struct dw_hdmi_curr_ctrl sun50i_h6_cur_ctr[] = {
+ /* pixelclk bpp8 bpp10 bpp12 */
+ { 25175000, { 0x0000, 0x0000, 0x0000 }, },
+ { 27000000, { 0x0012, 0x0000, 0x0000 }, },
+ { 59400000, { 0x0008, 0x0008, 0x0008 }, },
+ { 72000000, { 0x0008, 0x0008, 0x001b }, },
+ { 74250000, { 0x0013, 0x0013, 0x0013 }, },
+ { 90000000, { 0x0008, 0x001a, 0x001b }, },
+ { 118800000, { 0x001b, 0x001a, 0x001b }, },
+ { 144000000, { 0x001b, 0x001a, 0x0034 }, },
+ { 180000000, { 0x001b, 0x0033, 0x0034 }, },
+ { 216000000, { 0x0036, 0x0033, 0x0034 }, },
+ { 237600000, { 0x0036, 0x0033, 0x001b }, },
+ { 288000000, { 0x0036, 0x001b, 0x001b }, },
+ { 297000000, { 0x0019, 0x001b, 0x0019 }, },
+ { 330000000, { 0x0036, 0x001b, 0x001b }, },
+ { 594000000, { 0x003f, 0x001b, 0x001b }, },
+ { ~0UL, { 0x0000, 0x0000, 0x0000 }, }
+};
+
+static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = {
+ /*pixelclk symbol term vlev*/
+ { 74250000, 0x8009, 0x0004, 0x0232},
+ { 148500000, 0x8029, 0x0004, 0x0273},
+ { 594000000, 0x8039, 0x0004, 0x014a},
+ { ~0UL, 0x0000, 0x0000, 0x0000}
+};
+
static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
struct sun8i_hdmi_phy *phy,
unsigned int clk_rate)
@@ -290,6 +406,16 @@ static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)
SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
}
+static void sun50i_hdmi_phy_init_h6(struct sun8i_hdmi_phy *phy)
+{
+ regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
+ SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
+ SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
+
+ regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
+ 0xffff0000, 0x80c00000);
+}
+
static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy)
{
sun8i_hdmi_phy_unlock(phy);
@@ -446,6 +572,13 @@ static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
.phy_config = &sun8i_hdmi_phy_config_h3,
};
+static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = {
+ .cur_ctr = sun50i_h6_cur_ctr,
+ .mpll_cfg = sun50i_h6_mpll_cfg,
+ .phy_cfg = sun50i_h6_phy_config,
+ .phy_init = &sun50i_hdmi_phy_init_h6,
+};
+
static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
{
.compatible = "allwinner,sun8i-a83t-hdmi-phy",
@@ -463,6 +596,10 @@ static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
.compatible = "allwinner,sun50i-a64-hdmi-phy",
.data = &sun50i_a64_hdmi_phy,
},
+ {
+ .compatible = "allwinner,sun50i-h6-hdmi-phy",
+ .data = &sun50i_h6_hdmi_phy,
+ },
{ /* sentinel */ }
};
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 24/29] drm/sun4i: Initialize registers in tcon-top driver
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (22 preceding siblings ...)
2018-10-07 9:38 ` [PATCH v2 23/29] drm/sun4i: Add support for H6 " Jernej Skrabec
@ 2018-10-07 9:39 ` Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP Jernej Skrabec
` (5 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:39 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
It turns out that TCON TOP registers in H6 SoC have non-zero reset
value. This may cause issues if bits are not changed during
configuration.
To prevent that, initialize registers to 0.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
index 3040a79f298f..37158548b447 100644
--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -167,6 +167,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
goto err_assert_reset;
}
+ /*
+ * At least on H6, some registers have some bits set by default
+ * which may cause issues. Clear them here.
+ */
+ writel(0, regs + TCON_TOP_PORT_SEL_REG);
+ writel(0, regs + TCON_TOP_GATE_SRC_REG);
+
/*
* TCON TOP has two muxes, which select parent clock for each TCON TV
* channel clock. Parent could be either TCON TV or TVE clock. For now
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (23 preceding siblings ...)
2018-10-07 9:39 ` [PATCH v2 24/29] drm/sun4i: Initialize registers in tcon-top driver Jernej Skrabec
@ 2018-10-07 9:39 ` Jernej Skrabec
2018-10-08 8:51 ` Maxime Ripard
2018-10-07 9:39 ` [PATCH v2 26/29] dt-bindings: display: sun4i-drm: document H6 " Jernej Skrabec
` (4 subsequent siblings)
29 siblings, 1 reply; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:39 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
Add quirks support for TCON TOP.
Currently the presence of TCON_TV1 and DSI is controlled via the quirks
structure.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 43 ++++++++++++++++++++------
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
index 37158548b447..ed13233cad88 100644
--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -9,11 +9,17 @@
#include <linux/component.h>
#include <linux/device.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include "sun8i_tcon_top.h"
+struct sun8i_tcon_top_quirks {
+ bool has_tcon_tv1;
+ bool has_dsi;
+};
+
static bool sun8i_tcon_top_node_is_tcon_top(struct device_node *node)
{
return !!of_match_node(sun8i_tcon_top_of_table, node);
@@ -121,10 +127,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
struct platform_device *pdev = to_platform_device(dev);
struct clk_hw_onecell_data *clk_data;
struct sun8i_tcon_top *tcon_top;
+ const struct sun8i_tcon_top_quirks *quirks;
struct resource *res;
void __iomem *regs;
int ret, i;
+ quirks = of_device_get_match_data(&pdev->dev);
+
tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
if (!tcon_top)
return -ENOMEM;
@@ -187,15 +196,23 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
&tcon_top->reg_lock,
TCON_TOP_TCON_TV0_GATE, 0);
- clk_data->hws[CLK_TCON_TOP_TV1] =
- sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
- &tcon_top->reg_lock,
- TCON_TOP_TCON_TV1_GATE, 1);
+ if (quirks->has_tcon_tv1) {
+ clk_data->hws[CLK_TCON_TOP_TV1] =
+ sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
+ &tcon_top->reg_lock,
+ TCON_TOP_TCON_TV1_GATE, 1);
+ } else {
+ clk_data->hws[CLK_TCON_TOP_TV1] = NULL;
+ }
- clk_data->hws[CLK_TCON_TOP_DSI] =
- sun8i_tcon_top_register_gate(dev, "dsi", regs,
- &tcon_top->reg_lock,
- TCON_TOP_TCON_DSI_GATE, 2);
+ if (quirks->has_dsi) {
+ clk_data->hws[CLK_TCON_TOP_DSI] =
+ sun8i_tcon_top_register_gate(dev, "dsi", regs,
+ &tcon_top->reg_lock,
+ TCON_TOP_TCON_DSI_GATE, 2);
+ } else {
+ clk_data->hws[CLK_TCON_TOP_DSI] = NULL;
+ }
for (i = 0; i < CLK_NUM; i++)
if (IS_ERR(clk_data->hws[i])) {
@@ -257,9 +274,17 @@ static int sun8i_tcon_top_remove(struct platform_device *pdev)
return 0;
}
+const struct sun8i_tcon_top_quirks sun8i_r40_tcon_top_quirks = {
+ .has_tcon_tv1 = true,
+ .has_dsi = true,
+};
+
/* sun4i_drv uses this list to check if a device node is a TCON TOP */
const struct of_device_id sun8i_tcon_top_of_table[] = {
- { .compatible = "allwinner,sun8i-r40-tcon-top" },
+ {
+ .compatible = "allwinner,sun8i-r40-tcon-top",
+ .data = &sun8i_r40_tcon_top_quirks
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun8i_tcon_top_of_table);
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 26/29] dt-bindings: display: sun4i-drm: document H6 TCON TOP
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (24 preceding siblings ...)
2018-10-07 9:39 ` [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP Jernej Skrabec
@ 2018-10-07 9:39 ` Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 27/29] drm: sun4i: add support for " Jernej Skrabec
` (3 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:39 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
Allwinner H6 SoC has a cut down version of TCON TOP.
Add binding documentation for it.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[expanded description]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../bindings/display/sunxi/sun4i-drm.txt | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 478b288eebd9..f426bdb42f18 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -228,24 +228,26 @@ It allows display pipeline to be configured in very different ways:
\ [3] TCON-TV1 [1] - TVE1/RGB
Note that both TCON TOP references same physical unit. Both mixers can be
-connected to any TCON.
+connected to any TCON. Not all TCON TOP variants support all features.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-r40-tcon-top
+ * allwinner,sun50i-h6-tcon-top
- reg: base address and size of the memory-mapped region.
- clocks: phandle to the clocks feeding the TCON TOP
* bus: TCON TOP interface clock
* tcon-tv0: TCON TV0 clock
- * tve0: TVE0 clock
- * tcon-tv1: TCON TV1 clock
- * tve1: TVE0 clock
- * dsi: MIPI DSI clock
+ * tve0: TVE0 clock (R40 only)
+ * tcon-tv1: TCON TV1 clock (R40 only)
+ * tve1: TVE0 clock (R40 only)
+ * dsi: MIPI DSI clock (R40 only)
- clock-names: clock name mentioned above
- resets: phandle to the reset line driving the TCON TOP
- #clock-cells : must contain 1
- clock-output-names: Names of clocks created for TCON TV0 channel clock,
- TCON TV1 channel clock and DSI channel clock, in that order.
+ TCON TV1 channel clock (R40 only) and DSI channel clock (R40 only), in
+ that order.
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 27/29] drm: sun4i: add support for H6 TCON TOP
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (25 preceding siblings ...)
2018-10-07 9:39 ` [PATCH v2 26/29] dt-bindings: display: sun4i-drm: document H6 " Jernej Skrabec
@ 2018-10-07 9:39 ` Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 28/29] arm64: dts: allwinner: h6: Add HDMI pipeline Jernej Skrabec
` (2 subsequent siblings)
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:39 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
From: Icenowy Zheng <icenowy@aosc.io>
The TCON TOP on Allwinner H6 SoC is a cut down version of the R40 TCON
TOP, which dropped TCON_TV1 and DSI (which do not exist on H6).
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
index ed13233cad88..d0f1767ec6fc 100644
--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -279,12 +279,20 @@ const struct sun8i_tcon_top_quirks sun8i_r40_tcon_top_quirks = {
.has_dsi = true,
};
+const struct sun8i_tcon_top_quirks sun50i_h6_tcon_top_quirks = {
+ /* Nothing special */
+};
+
/* sun4i_drv uses this list to check if a device node is a TCON TOP */
const struct of_device_id sun8i_tcon_top_of_table[] = {
{
.compatible = "allwinner,sun8i-r40-tcon-top",
.data = &sun8i_r40_tcon_top_quirks
},
+ {
+ .compatible = "allwinner,sun50i-h6-tcon-top",
+ .data = &sun50i_h6_tcon_top_quirks
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun8i_tcon_top_of_table);
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 28/29] arm64: dts: allwinner: h6: Add HDMI pipeline
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (26 preceding siblings ...)
2018-10-07 9:39 ` [PATCH v2 27/29] drm: sun4i: add support for " Jernej Skrabec
@ 2018-10-07 9:39 ` Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 29/29] arm64: dts: allwinner: h6: Enable HDMI output on Pine H64 board Jernej Skrabec
2018-10-07 9:50 ` [linux-sunxi] [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Škrabec
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:39 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
This commit adds all entries needed for HDMI to function properly.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
[added DE3 bus]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 201 +++++++++++++++++++
1 file changed, 201 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 040828d2e2c0..59dda8f89d23 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -6,8 +6,11 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
/ {
interrupt-parent = <&gic>;
@@ -86,12 +89,63 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ de: display-engine {
+ compatible = "allwinner,sun50i-h6-display-engine";
+ allwinner,pipelines = <&mixer0>;
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ de3@1000000 {
+ compatible = "allwinner,sun50i-h6-de3",
+ "allwinner,sun50i-a64-de2";
+ reg = <0x1000000 0x400000>;
+ allwinner,sram = <&de2_sram 1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000000 0x400000>;
+
+ display_clocks: clock@0 {
+ compatible = "allwinner,sun50i-h6-de3-clk";
+ reg = <0x0 0x10000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@100000 {
+ compatible = "allwinner,sun50i-h6-de3-mixer-0";
+ reg = <0x100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon_top_mixer0: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+ };
+ };
+ };
+ };
+ };
+
syscon: syscon@3000000 {
compatible = "allwinner,sun50i-h6-system-control",
"allwinner,sun50i-a64-system-control";
@@ -149,6 +203,11 @@
interrupt-controller;
#interrupt-cells = <3>;
+ hdmi_pins: hdmi-pins {
+ pins = "PH8", "PH9", "PH10";
+ function = "hdmi";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
@@ -258,6 +317,148 @@
status = "disabled";
};
+ hdmi: hdmi@6000000 {
+ compatible = "allwinner,sun50i-h6-dw-hdmi";
+ reg = <0x06000000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
+ <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
+ clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
+ "hdcp-bus";
+ resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
+ reset-names = "ctrl", "hdcp";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon_top: endpoint {
+ remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy@6010000 {
+ compatible = "allwinner,sun50i-h6-hdmi-phy";
+ reg = <0x06010000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_HDMI>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
+ tcon_top: tcon-top@6510000 {
+ compatible = "allwinner,sun50i-h6-tcon-top";
+ reg = <0x06510000 0x1000>;
+ clocks = <&ccu CLK_BUS_TCON_TOP>,
+ <&ccu CLK_TCON_TV0>;
+ clock-names = "bus",
+ "tcon-tv0";
+ clock-output-names = "tcon-top-tv0";
+ resets = <&ccu RST_BUS_TCON_TOP>;
+ reset-names = "rst";
+ #clock-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon_top_mixer0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_top_mixer0_out_tcon_tv: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_hdmi_in: port@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ tcon_top_hdmi_in_tcon_tv: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_tv_out_tcon_top>;
+ };
+ };
+
+ tcon_top_hdmi_out: port@5 {
+ reg = <5>;
+
+ tcon_top_hdmi_out_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in_tcon_top>;
+ };
+ };
+ };
+ };
+
+ tcon_tv: lcd-controller@6515000 {
+ compatible = "allwinner,sun50i-h6-tcon-tv",
+ "allwinner,sun8i-r40-tcon-tv";
+ reg = <0x06515000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV0>,
+ <&tcon_top CLK_TCON_TOP_TV0>;
+ clock-names = "ahb",
+ "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV0>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv_in: port@0 {
+ reg = <0>;
+
+ tcon_tv_in_tcon_top_mixer0: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
+ };
+ };
+
+ tcon_tv_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon_tv_out_tcon_top: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
+ };
+ };
+ };
+ };
+
r_ccu: clock@7010000 {
compatible = "allwinner,sun50i-h6-r-ccu";
reg = <0x07010000 0x400>;
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v2 29/29] arm64: dts: allwinner: h6: Enable HDMI output on Pine H64 board
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (27 preceding siblings ...)
2018-10-07 9:39 ` [PATCH v2 28/29] arm64: dts: allwinner: h6: Add HDMI pipeline Jernej Skrabec
@ 2018-10-07 9:39 ` Jernej Skrabec
2018-10-07 9:50 ` [linux-sunxi] [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Škrabec
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Skrabec @ 2018-10-07 9:39 UTC (permalink / raw)
To: maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Pine H64 board has HDMI type A connector.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 48daec7f78ba..36db21314996 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -21,6 +21,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -41,6 +52,20 @@
};
};
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
--
2.19.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [linux-sunxi] [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
` (28 preceding siblings ...)
2018-10-07 9:39 ` [PATCH v2 29/29] arm64: dts: allwinner: h6: Enable HDMI output on Pine H64 board Jernej Skrabec
@ 2018-10-07 9:50 ` Jernej Škrabec
29 siblings, 0 replies; 52+ messages in thread
From: Jernej Škrabec @ 2018-10-07 9:50 UTC (permalink / raw)
To: linux-sunxi
Cc: maxime.ripard, wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel
Dne nedelja, 07. oktober 2018 ob 11:38:36 CEST je Jernej Skrabec napisal(a):
> This series adds support for Display Engine 3.0 and HDMI 2.0a, which
> can be found on H6 SoC.
>
> Display Engine 3.0 in comparison to 2.0 mostly adds features needed for
> displaying and processing 10-bit and AFBC formats, which are not yet
> supported by this series.
>
> This series is based on linux-next at next-20180828, which has working
> R40 display pipeline support. I'll rebase series on later linux-next, if
> needed, once R40 display pipeline support is reintroduced.
Sorry, I forgot to update above text. It is based on next-20181004 and R40
HDMI support is already fixed.
Best regards,
Jernej
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 01/29] dt-bindings: bus: add H6 DE3 bus binding
2018-10-07 9:38 ` [PATCH v2 01/29] dt-bindings: bus: add H6 DE3 bus binding Jernej Skrabec
@ 2018-10-08 8:31 ` Maxime Ripard
2018-10-08 14:25 ` Jernej Škrabec
0 siblings, 1 reply; 52+ messages in thread
From: Maxime Ripard @ 2018-10-08 8:31 UTC (permalink / raw)
To: Jernej Skrabec
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi, Icenowy Zheng
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On Sun, Oct 07, 2018 at 11:38:37AM +0200, Jernej Skrabec wrote:
> From: Icenowy Zheng <icenowy@aosc.io>
>
> The Allwinner H6 DE3 bus is similar to the A64 DE2 one.
>
> Add its compatible string with the A64 string as fallback to the
> binding.
>
> Some description of the binding is modified to make it more generic.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
> index 87dfb33fb3be..ac1445b95f41 100644
> --- a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
> +++ b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
> @@ -1,11 +1,14 @@
> -Device tree bindings for Allwinner A64 DE2 bus
> +Device tree bindings for Allwinner DE2/3 bus
>
> The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C)
> -to be claimed for enabling the access.
> +to be claimed for enabling the access. The DE3 on Allwinner H6 is at the same
> +situation, and the binding also applies.
>
> Required properties:
>
> - - compatible: Should contain "allwinner,sun50i-a64-de2"
> + - compatible: Should be one of:
> + - "allwinner,sun50i-a64-de2"
> + - "allwinner,sun50i-a6-de3", "allwinner,sun50i-a64-de2"
^ that would be h6 I guess?
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP
2018-10-07 9:39 ` [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP Jernej Skrabec
@ 2018-10-08 8:51 ` Maxime Ripard
2018-10-08 9:06 ` Chen-Yu Tsai
2018-10-08 14:30 ` Jernej Škrabec
0 siblings, 2 replies; 52+ messages in thread
From: Maxime Ripard @ 2018-10-08 8:51 UTC (permalink / raw)
To: Jernej Skrabec
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi, Icenowy Zheng
[-- Attachment #1: Type: text/plain, Size: 3121 bytes --]
On Sun, Oct 07, 2018 at 11:39:01AM +0200, Jernej Skrabec wrote:
> From: Icenowy Zheng <icenowy@aosc.io>
>
> Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
>
> Add quirks support for TCON TOP.
>
> Currently the presence of TCON_TV1 and DSI is controlled via the quirks
> structure.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 43 ++++++++++++++++++++------
> 1 file changed, 34 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> index 37158548b447..ed13233cad88 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> @@ -9,11 +9,17 @@
> #include <linux/component.h>
> #include <linux/device.h>
> #include <linux/module.h>
> +#include <linux/of_device.h>
> #include <linux/of_graph.h>
> #include <linux/platform_device.h>
>
> #include "sun8i_tcon_top.h"
>
> +struct sun8i_tcon_top_quirks {
> + bool has_tcon_tv1;
> + bool has_dsi;
> +};
> +
> static bool sun8i_tcon_top_node_is_tcon_top(struct device_node *node)
> {
> return !!of_match_node(sun8i_tcon_top_of_table, node);
> @@ -121,10 +127,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> struct platform_device *pdev = to_platform_device(dev);
> struct clk_hw_onecell_data *clk_data;
> struct sun8i_tcon_top *tcon_top;
> + const struct sun8i_tcon_top_quirks *quirks;
> struct resource *res;
> void __iomem *regs;
> int ret, i;
>
> + quirks = of_device_get_match_data(&pdev->dev);
> +
> tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
> if (!tcon_top)
> return -ENOMEM;
> @@ -187,15 +196,23 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> &tcon_top->reg_lock,
> TCON_TOP_TCON_TV0_GATE, 0);
>
> - clk_data->hws[CLK_TCON_TOP_TV1] =
> - sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> - &tcon_top->reg_lock,
> - TCON_TOP_TCON_TV1_GATE, 1);
> + if (quirks->has_tcon_tv1) {
> + clk_data->hws[CLK_TCON_TOP_TV1] =
> + sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> + &tcon_top->reg_lock,
> + TCON_TOP_TCON_TV1_GATE, 1);
> + } else {
> + clk_data->hws[CLK_TCON_TOP_TV1] = NULL;
> + }
>
> - clk_data->hws[CLK_TCON_TOP_DSI] =
> - sun8i_tcon_top_register_gate(dev, "dsi", regs,
> - &tcon_top->reg_lock,
> - TCON_TOP_TCON_DSI_GATE, 2);
> + if (quirks->has_dsi) {
> + clk_data->hws[CLK_TCON_TOP_DSI] =
> + sun8i_tcon_top_register_gate(dev, "dsi", regs,
> + &tcon_top->reg_lock,
> + TCON_TOP_TCON_DSI_GATE, 2);
> + } else {
> + clk_data->hws[CLK_TCON_TOP_DSI] = NULL;
clk_data has been kzalloc'd so its content is already NULL.
And you shouldn't have brackets for single line blocks.
with that fixed,
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP
2018-10-08 8:51 ` Maxime Ripard
@ 2018-10-08 9:06 ` Chen-Yu Tsai
2018-10-08 10:20 ` Maxime Ripard
2018-10-08 14:30 ` Jernej Škrabec
1 sibling, 1 reply; 52+ messages in thread
From: Chen-Yu Tsai @ 2018-10-08 9:06 UTC (permalink / raw)
To: Maxime Ripard
Cc: Jernej Skrabec, Rob Herring, Stephen Boyd, David Airlie,
Archit Taneja, Andrzej Hajda, Laurent Pinchart, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
On Mon, Oct 8, 2018 at 4:51 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Sun, Oct 07, 2018 at 11:39:01AM +0200, Jernej Skrabec wrote:
> > From: Icenowy Zheng <icenowy@aosc.io>
> >
> > Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
> >
> > Add quirks support for TCON TOP.
> >
> > Currently the presence of TCON_TV1 and DSI is controlled via the quirks
> > structure.
> >
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > ---
> > drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 43 ++++++++++++++++++++------
> > 1 file changed, 34 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > index 37158548b447..ed13233cad88 100644
> > --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > @@ -9,11 +9,17 @@
> > #include <linux/component.h>
> > #include <linux/device.h>
> > #include <linux/module.h>
> > +#include <linux/of_device.h>
> > #include <linux/of_graph.h>
> > #include <linux/platform_device.h>
> >
> > #include "sun8i_tcon_top.h"
> >
> > +struct sun8i_tcon_top_quirks {
> > + bool has_tcon_tv1;
> > + bool has_dsi;
> > +};
> > +
> > static bool sun8i_tcon_top_node_is_tcon_top(struct device_node *node)
> > {
> > return !!of_match_node(sun8i_tcon_top_of_table, node);
> > @@ -121,10 +127,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > struct platform_device *pdev = to_platform_device(dev);
> > struct clk_hw_onecell_data *clk_data;
> > struct sun8i_tcon_top *tcon_top;
> > + const struct sun8i_tcon_top_quirks *quirks;
> > struct resource *res;
> > void __iomem *regs;
> > int ret, i;
> >
> > + quirks = of_device_get_match_data(&pdev->dev);
> > +
> > tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
> > if (!tcon_top)
> > return -ENOMEM;
> > @@ -187,15 +196,23 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > &tcon_top->reg_lock,
> > TCON_TOP_TCON_TV0_GATE, 0);
> >
> > - clk_data->hws[CLK_TCON_TOP_TV1] =
> > - sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > - &tcon_top->reg_lock,
> > - TCON_TOP_TCON_TV1_GATE, 1);
> > + if (quirks->has_tcon_tv1) {
> > + clk_data->hws[CLK_TCON_TOP_TV1] =
> > + sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > + &tcon_top->reg_lock,
> > + TCON_TOP_TCON_TV1_GATE, 1);
> > + } else {
> > + clk_data->hws[CLK_TCON_TOP_TV1] = NULL;
> > + }
> >
> > - clk_data->hws[CLK_TCON_TOP_DSI] =
> > - sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > - &tcon_top->reg_lock,
> > - TCON_TOP_TCON_DSI_GATE, 2);
> > + if (quirks->has_dsi) {
> > + clk_data->hws[CLK_TCON_TOP_DSI] =
> > + sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > + &tcon_top->reg_lock,
> > + TCON_TOP_TCON_DSI_GATE, 2);
> > + } else {
> > + clk_data->hws[CLK_TCON_TOP_DSI] = NULL;
>
> clk_data has been kzalloc'd so its content is already NULL.
>
> And you shouldn't have brackets for single line blocks.
>
> with that fixed,
FYI checkpatch.pl complains if you use brackets for the if block
but not for the else block. They should be matching.
ChenYu
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 18/29] drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock
2018-10-07 9:38 ` [PATCH v2 18/29] drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock Jernej Skrabec
@ 2018-10-08 9:14 ` Maxime Ripard
2018-10-08 15:09 ` Jernej Škrabec
0 siblings, 1 reply; 52+ messages in thread
From: Maxime Ripard @ 2018-10-08 9:14 UTC (permalink / raw)
To: Jernej Skrabec
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi
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Hi,
On Sun, Oct 07, 2018 at 11:38:54AM +0200, Jernej Skrabec wrote:
> It turns out that H6 HDMI BSP kernel driver doesn't change TMDS rate at
> all. At this point it is not clear whether it is just not necessary or
> it would cause some kind of issues.
>
> Add a quirk for it.
>
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 5 ++++-
> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 +
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> index ec122136ee9d..e9e93f174b35 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> @@ -165,7 +165,9 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
> goto err_disable_clk_tmds;
> }
>
> - drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
> + if (hdmi->quirks->set_rate)
> + drm_encoder_helper_add(encoder,
> + &sun8i_dw_hdmi_encoder_helper_funcs);
That seems a bit backward, it only works because we only have mode_set
at the moment, and the only thing it does is changing the clock
rate. As soon as we change one of these two assumptions, the code will
break.
Why not just return in mode_set if that boolean is true?
> drm_encoder_init(drm, encoder, &sun8i_dw_hdmi_encoder_funcs,
> DRM_MODE_ENCODER_TMDS, NULL);
>
> @@ -235,6 +237,7 @@ static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
>
> static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
> .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
> + .set_rate = true,
> };
>
> static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> index a645b8bc9f58..f9eb663865a4 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> @@ -173,6 +173,7 @@ struct sun8i_hdmi_phy {
> struct sun8i_dw_hdmi_quirks {
> enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
> const struct drm_display_mode *mode);
> + bool set_rate;
This triggers a check in checkpatch. You should address them (and
there's several in your series).
With both addressed,
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Thanks!
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 10/29] drm/sun4i: Rename DE2 registers related macros
2018-10-07 9:38 ` [PATCH v2 10/29] drm/sun4i: Rename DE2 registers related macros Jernej Skrabec
@ 2018-10-08 10:18 ` Maxime Ripard
2018-10-08 14:28 ` Jernej Škrabec
0 siblings, 1 reply; 52+ messages in thread
From: Maxime Ripard @ 2018-10-08 10:18 UTC (permalink / raw)
To: Jernej Skrabec
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi
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Hi,
On Sun, Oct 07, 2018 at 11:38:46AM +0200, Jernej Skrabec wrote:
> In preparation to introduce DE3 support, change prefix from "SUN8I_" to
> "DE2_". Current prefix suggest that it's valid only for one family,
> whereas in reality, DE2 unit is used also on sun50i family.
> Additionally, it will be easier to distinguish DE3 specific macros by
> using "DE3_" prefix.
>
> No functional change in this commit.
I'm not too sure about this one. There's basically two ways to look at
this: you described the first one, and the second one would be to
treat it as we do for the compatibles: the IP was introduced on one
SoC family, and then got used on some other ones.
Trying to always match the one you have however have a quite big
maintainance cost, as can be shown by your patch: you always have to
adapt comments, function names, defines, etc. This creates a lot of
useless churns (ie, non-functional changes) in the drivers, that need
to be written in the first place, and then reviewed.
It's just not worth it.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP
2018-10-08 9:06 ` Chen-Yu Tsai
@ 2018-10-08 10:20 ` Maxime Ripard
2018-10-08 10:50 ` Chen-Yu Tsai
0 siblings, 1 reply; 52+ messages in thread
From: Maxime Ripard @ 2018-10-08 10:20 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Jernej Skrabec, Rob Herring, Stephen Boyd, David Airlie,
Archit Taneja, Andrzej Hajda, Laurent Pinchart, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
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On Mon, Oct 08, 2018 at 05:06:45PM +0800, Chen-Yu Tsai wrote:
> On Mon, Oct 8, 2018 at 4:51 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Sun, Oct 07, 2018 at 11:39:01AM +0200, Jernej Skrabec wrote:
> > > From: Icenowy Zheng <icenowy@aosc.io>
> > >
> > > Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
> > >
> > > Add quirks support for TCON TOP.
> > >
> > > Currently the presence of TCON_TV1 and DSI is controlled via the quirks
> > > structure.
> > >
> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > ---
> > > drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 43 ++++++++++++++++++++------
> > > 1 file changed, 34 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > index 37158548b447..ed13233cad88 100644
> > > --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > @@ -9,11 +9,17 @@
> > > #include <linux/component.h>
> > > #include <linux/device.h>
> > > #include <linux/module.h>
> > > +#include <linux/of_device.h>
> > > #include <linux/of_graph.h>
> > > #include <linux/platform_device.h>
> > >
> > > #include "sun8i_tcon_top.h"
> > >
> > > +struct sun8i_tcon_top_quirks {
> > > + bool has_tcon_tv1;
> > > + bool has_dsi;
> > > +};
> > > +
> > > static bool sun8i_tcon_top_node_is_tcon_top(struct device_node *node)
> > > {
> > > return !!of_match_node(sun8i_tcon_top_of_table, node);
> > > @@ -121,10 +127,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > > struct platform_device *pdev = to_platform_device(dev);
> > > struct clk_hw_onecell_data *clk_data;
> > > struct sun8i_tcon_top *tcon_top;
> > > + const struct sun8i_tcon_top_quirks *quirks;
> > > struct resource *res;
> > > void __iomem *regs;
> > > int ret, i;
> > >
> > > + quirks = of_device_get_match_data(&pdev->dev);
> > > +
> > > tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
> > > if (!tcon_top)
> > > return -ENOMEM;
> > > @@ -187,15 +196,23 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > > &tcon_top->reg_lock,
> > > TCON_TOP_TCON_TV0_GATE, 0);
> > >
> > > - clk_data->hws[CLK_TCON_TOP_TV1] =
> > > - sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > > - &tcon_top->reg_lock,
> > > - TCON_TOP_TCON_TV1_GATE, 1);
> > > + if (quirks->has_tcon_tv1) {
> > > + clk_data->hws[CLK_TCON_TOP_TV1] =
> > > + sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > > + &tcon_top->reg_lock,
> > > + TCON_TOP_TCON_TV1_GATE, 1);
> > > + } else {
> > > + clk_data->hws[CLK_TCON_TOP_TV1] = NULL;
> > > + }
> > >
> > > - clk_data->hws[CLK_TCON_TOP_DSI] =
> > > - sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > > - &tcon_top->reg_lock,
> > > - TCON_TOP_TCON_DSI_GATE, 2);
> > > + if (quirks->has_dsi) {
> > > + clk_data->hws[CLK_TCON_TOP_DSI] =
> > > + sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > > + &tcon_top->reg_lock,
> > > + TCON_TOP_TCON_DSI_GATE, 2);
> > > + } else {
> > > + clk_data->hws[CLK_TCON_TOP_DSI] = NULL;
> >
> > clk_data has been kzalloc'd so its content is already NULL.
> >
> > And you shouldn't have brackets for single line blocks.
> >
> > with that fixed,
>
> FYI checkpatch.pl complains if you use brackets for the if block
> but not for the else block. They should be matching.
Checkpatch might not warn on this, but
https://www.kernel.org/doc/Documentation/process/coding-style.rst,
section 3 is pretty clear on whether we should use them or not.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP
2018-10-08 10:20 ` Maxime Ripard
@ 2018-10-08 10:50 ` Chen-Yu Tsai
2018-10-08 12:33 ` Maxime Ripard
0 siblings, 1 reply; 52+ messages in thread
From: Chen-Yu Tsai @ 2018-10-08 10:50 UTC (permalink / raw)
To: Maxime Ripard
Cc: Jernej Skrabec, Rob Herring, Stephen Boyd, David Airlie,
Archit Taneja, Andrzej Hajda, Laurent Pinchart, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
On Mon, Oct 8, 2018 at 6:20 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Mon, Oct 08, 2018 at 05:06:45PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Oct 8, 2018 at 4:51 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > >
> > > On Sun, Oct 07, 2018 at 11:39:01AM +0200, Jernej Skrabec wrote:
> > > > From: Icenowy Zheng <icenowy@aosc.io>
> > > >
> > > > Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
> > > >
> > > > Add quirks support for TCON TOP.
> > > >
> > > > Currently the presence of TCON_TV1 and DSI is controlled via the quirks
> > > > structure.
> > > >
> > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > > ---
> > > > drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 43 ++++++++++++++++++++------
> > > > 1 file changed, 34 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > > index 37158548b447..ed13233cad88 100644
> > > > --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > > @@ -9,11 +9,17 @@
> > > > #include <linux/component.h>
> > > > #include <linux/device.h>
> > > > #include <linux/module.h>
> > > > +#include <linux/of_device.h>
> > > > #include <linux/of_graph.h>
> > > > #include <linux/platform_device.h>
> > > >
> > > > #include "sun8i_tcon_top.h"
> > > >
> > > > +struct sun8i_tcon_top_quirks {
> > > > + bool has_tcon_tv1;
> > > > + bool has_dsi;
> > > > +};
> > > > +
> > > > static bool sun8i_tcon_top_node_is_tcon_top(struct device_node *node)
> > > > {
> > > > return !!of_match_node(sun8i_tcon_top_of_table, node);
> > > > @@ -121,10 +127,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > > > struct platform_device *pdev = to_platform_device(dev);
> > > > struct clk_hw_onecell_data *clk_data;
> > > > struct sun8i_tcon_top *tcon_top;
> > > > + const struct sun8i_tcon_top_quirks *quirks;
> > > > struct resource *res;
> > > > void __iomem *regs;
> > > > int ret, i;
> > > >
> > > > + quirks = of_device_get_match_data(&pdev->dev);
> > > > +
> > > > tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
> > > > if (!tcon_top)
> > > > return -ENOMEM;
> > > > @@ -187,15 +196,23 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > > > &tcon_top->reg_lock,
> > > > TCON_TOP_TCON_TV0_GATE, 0);
> > > >
> > > > - clk_data->hws[CLK_TCON_TOP_TV1] =
> > > > - sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > > > - &tcon_top->reg_lock,
> > > > - TCON_TOP_TCON_TV1_GATE, 1);
> > > > + if (quirks->has_tcon_tv1) {
> > > > + clk_data->hws[CLK_TCON_TOP_TV1] =
> > > > + sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > > > + &tcon_top->reg_lock,
> > > > + TCON_TOP_TCON_TV1_GATE, 1);
> > > > + } else {
> > > > + clk_data->hws[CLK_TCON_TOP_TV1] = NULL;
> > > > + }
> > > >
> > > > - clk_data->hws[CLK_TCON_TOP_DSI] =
> > > > - sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > > > - &tcon_top->reg_lock,
> > > > - TCON_TOP_TCON_DSI_GATE, 2);
> > > > + if (quirks->has_dsi) {
> > > > + clk_data->hws[CLK_TCON_TOP_DSI] =
> > > > + sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > > > + &tcon_top->reg_lock,
> > > > + TCON_TOP_TCON_DSI_GATE, 2);
> > > > + } else {
> > > > + clk_data->hws[CLK_TCON_TOP_DSI] = NULL;
> > >
> > > clk_data has been kzalloc'd so its content is already NULL.
> > >
> > > And you shouldn't have brackets for single line blocks.
> > >
> > > with that fixed,
> >
> > FYI checkpatch.pl complains if you use brackets for the if block
> > but not for the else block. They should be matching.
>
> Checkpatch might not warn on this, but
> https://www.kernel.org/doc/Documentation/process/coding-style.rst,
> section 3 is pretty clear on whether we should use them or not.
Right. What I'm pointing out what checkpatch.pl complains about is
shown in the second last example in section 3:
This does not apply if only one branch of a conditional statement
is a single
statement; in the latter case use braces in both branches:
Which is where I think your comment on "shouldn't have brackets for
single line blocks"
is pointing in the opposite direction.
ChenYu
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP
2018-10-08 10:50 ` Chen-Yu Tsai
@ 2018-10-08 12:33 ` Maxime Ripard
2018-10-08 13:10 ` Chen-Yu Tsai
0 siblings, 1 reply; 52+ messages in thread
From: Maxime Ripard @ 2018-10-08 12:33 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Jernej Skrabec, Rob Herring, Stephen Boyd, David Airlie,
Archit Taneja, Andrzej Hajda, Laurent Pinchart, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
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On Mon, Oct 08, 2018 at 06:50:44PM +0800, Chen-Yu Tsai wrote:
> On Mon, Oct 8, 2018 at 6:20 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Mon, Oct 08, 2018 at 05:06:45PM +0800, Chen-Yu Tsai wrote:
> > > On Mon, Oct 8, 2018 at 4:51 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > > >
> > > > On Sun, Oct 07, 2018 at 11:39:01AM +0200, Jernej Skrabec wrote:
> > > > > From: Icenowy Zheng <icenowy@aosc.io>
> > > > >
> > > > > Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
> > > > >
> > > > > Add quirks support for TCON TOP.
> > > > >
> > > > > Currently the presence of TCON_TV1 and DSI is controlled via the quirks
> > > > > structure.
> > > > >
> > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > > > ---
> > > > > drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 43 ++++++++++++++++++++------
> > > > > 1 file changed, 34 insertions(+), 9 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > > > index 37158548b447..ed13233cad88 100644
> > > > > --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > > > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > > > @@ -9,11 +9,17 @@
> > > > > #include <linux/component.h>
> > > > > #include <linux/device.h>
> > > > > #include <linux/module.h>
> > > > > +#include <linux/of_device.h>
> > > > > #include <linux/of_graph.h>
> > > > > #include <linux/platform_device.h>
> > > > >
> > > > > #include "sun8i_tcon_top.h"
> > > > >
> > > > > +struct sun8i_tcon_top_quirks {
> > > > > + bool has_tcon_tv1;
> > > > > + bool has_dsi;
> > > > > +};
> > > > > +
> > > > > static bool sun8i_tcon_top_node_is_tcon_top(struct device_node *node)
> > > > > {
> > > > > return !!of_match_node(sun8i_tcon_top_of_table, node);
> > > > > @@ -121,10 +127,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > > > > struct platform_device *pdev = to_platform_device(dev);
> > > > > struct clk_hw_onecell_data *clk_data;
> > > > > struct sun8i_tcon_top *tcon_top;
> > > > > + const struct sun8i_tcon_top_quirks *quirks;
> > > > > struct resource *res;
> > > > > void __iomem *regs;
> > > > > int ret, i;
> > > > >
> > > > > + quirks = of_device_get_match_data(&pdev->dev);
> > > > > +
> > > > > tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
> > > > > if (!tcon_top)
> > > > > return -ENOMEM;
> > > > > @@ -187,15 +196,23 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > > > > &tcon_top->reg_lock,
> > > > > TCON_TOP_TCON_TV0_GATE, 0);
> > > > >
> > > > > - clk_data->hws[CLK_TCON_TOP_TV1] =
> > > > > - sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > > > > - &tcon_top->reg_lock,
> > > > > - TCON_TOP_TCON_TV1_GATE, 1);
> > > > > + if (quirks->has_tcon_tv1) {
> > > > > + clk_data->hws[CLK_TCON_TOP_TV1] =
> > > > > + sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > > > > + &tcon_top->reg_lock,
> > > > > + TCON_TOP_TCON_TV1_GATE, 1);
> > > > > + } else {
> > > > > + clk_data->hws[CLK_TCON_TOP_TV1] = NULL;
> > > > > + }
> > > > >
> > > > > - clk_data->hws[CLK_TCON_TOP_DSI] =
> > > > > - sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > > > > - &tcon_top->reg_lock,
> > > > > - TCON_TOP_TCON_DSI_GATE, 2);
> > > > > + if (quirks->has_dsi) {
> > > > > + clk_data->hws[CLK_TCON_TOP_DSI] =
> > > > > + sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > > > > + &tcon_top->reg_lock,
> > > > > + TCON_TOP_TCON_DSI_GATE, 2);
> > > > > + } else {
> > > > > + clk_data->hws[CLK_TCON_TOP_DSI] = NULL;
> > > >
> > > > clk_data has been kzalloc'd so its content is already NULL.
> > > >
> > > > And you shouldn't have brackets for single line blocks.
> > > >
> > > > with that fixed,
> > >
> > > FYI checkpatch.pl complains if you use brackets for the if block
> > > but not for the else block. They should be matching.
> >
> > Checkpatch might not warn on this, but
> > https://www.kernel.org/doc/Documentation/process/coding-style.rst,
> > section 3 is pretty clear on whether we should use them or not.
>
> Right. What I'm pointing out what checkpatch.pl complains about is
> shown in the second last example in section 3:
>
> This does not apply if only one branch of a conditional statement
> is a single
> statement; in the latter case use braces in both branches:
>
> Which is where I think your comment on "shouldn't have brackets for
> single line blocks"
> is pointing in the opposite direction.
I think we have a communication failure :)
The two blocks above are single line blocks, even though the line is
wrapped. So whether or not there is an else condition or not doesn't
matter, you shouldn't have braces at all.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP
2018-10-08 12:33 ` Maxime Ripard
@ 2018-10-08 13:10 ` Chen-Yu Tsai
0 siblings, 0 replies; 52+ messages in thread
From: Chen-Yu Tsai @ 2018-10-08 13:10 UTC (permalink / raw)
To: Maxime Ripard
Cc: Jernej Skrabec, Rob Herring, Stephen Boyd, David Airlie,
Archit Taneja, Andrzej Hajda, Laurent Pinchart, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi, Icenowy Zheng
On Mon, Oct 8, 2018 at 8:33 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Mon, Oct 08, 2018 at 06:50:44PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Oct 8, 2018 at 6:20 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > >
> > > On Mon, Oct 08, 2018 at 05:06:45PM +0800, Chen-Yu Tsai wrote:
> > > > On Mon, Oct 8, 2018 at 4:51 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > > > >
> > > > > On Sun, Oct 07, 2018 at 11:39:01AM +0200, Jernej Skrabec wrote:
> > > > > > From: Icenowy Zheng <icenowy@aosc.io>
> > > > > >
> > > > > > Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
> > > > > >
> > > > > > Add quirks support for TCON TOP.
> > > > > >
> > > > > > Currently the presence of TCON_TV1 and DSI is controlled via the quirks
> > > > > > structure.
> > > > > >
> > > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > > > > ---
> > > > > > drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 43 ++++++++++++++++++++------
> > > > > > 1 file changed, 34 insertions(+), 9 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > > > > index 37158548b447..ed13233cad88 100644
> > > > > > --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > > > > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > > > > > @@ -9,11 +9,17 @@
> > > > > > #include <linux/component.h>
> > > > > > #include <linux/device.h>
> > > > > > #include <linux/module.h>
> > > > > > +#include <linux/of_device.h>
> > > > > > #include <linux/of_graph.h>
> > > > > > #include <linux/platform_device.h>
> > > > > >
> > > > > > #include "sun8i_tcon_top.h"
> > > > > >
> > > > > > +struct sun8i_tcon_top_quirks {
> > > > > > + bool has_tcon_tv1;
> > > > > > + bool has_dsi;
> > > > > > +};
> > > > > > +
> > > > > > static bool sun8i_tcon_top_node_is_tcon_top(struct device_node *node)
> > > > > > {
> > > > > > return !!of_match_node(sun8i_tcon_top_of_table, node);
> > > > > > @@ -121,10 +127,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > > > > > struct platform_device *pdev = to_platform_device(dev);
> > > > > > struct clk_hw_onecell_data *clk_data;
> > > > > > struct sun8i_tcon_top *tcon_top;
> > > > > > + const struct sun8i_tcon_top_quirks *quirks;
> > > > > > struct resource *res;
> > > > > > void __iomem *regs;
> > > > > > int ret, i;
> > > > > >
> > > > > > + quirks = of_device_get_match_data(&pdev->dev);
> > > > > > +
> > > > > > tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
> > > > > > if (!tcon_top)
> > > > > > return -ENOMEM;
> > > > > > @@ -187,15 +196,23 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
> > > > > > &tcon_top->reg_lock,
> > > > > > TCON_TOP_TCON_TV0_GATE, 0);
> > > > > >
> > > > > > - clk_data->hws[CLK_TCON_TOP_TV1] =
> > > > > > - sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > > > > > - &tcon_top->reg_lock,
> > > > > > - TCON_TOP_TCON_TV1_GATE, 1);
> > > > > > + if (quirks->has_tcon_tv1) {
> > > > > > + clk_data->hws[CLK_TCON_TOP_TV1] =
> > > > > > + sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > > > > > + &tcon_top->reg_lock,
> > > > > > + TCON_TOP_TCON_TV1_GATE, 1);
> > > > > > + } else {
> > > > > > + clk_data->hws[CLK_TCON_TOP_TV1] = NULL;
> > > > > > + }
> > > > > >
> > > > > > - clk_data->hws[CLK_TCON_TOP_DSI] =
> > > > > > - sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > > > > > - &tcon_top->reg_lock,
> > > > > > - TCON_TOP_TCON_DSI_GATE, 2);
> > > > > > + if (quirks->has_dsi) {
> > > > > > + clk_data->hws[CLK_TCON_TOP_DSI] =
> > > > > > + sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > > > > > + &tcon_top->reg_lock,
> > > > > > + TCON_TOP_TCON_DSI_GATE, 2);
> > > > > > + } else {
> > > > > > + clk_data->hws[CLK_TCON_TOP_DSI] = NULL;
> > > > >
> > > > > clk_data has been kzalloc'd so its content is already NULL.
> > > > >
> > > > > And you shouldn't have brackets for single line blocks.
> > > > >
> > > > > with that fixed,
> > > >
> > > > FYI checkpatch.pl complains if you use brackets for the if block
> > > > but not for the else block. They should be matching.
> > >
> > > Checkpatch might not warn on this, but
> > > https://www.kernel.org/doc/Documentation/process/coding-style.rst,
> > > section 3 is pretty clear on whether we should use them or not.
> >
> > Right. What I'm pointing out what checkpatch.pl complains about is
> > shown in the second last example in section 3:
> >
> > This does not apply if only one branch of a conditional statement
> > is a single
> > statement; in the latter case use braces in both branches:
> >
> > Which is where I think your comment on "shouldn't have brackets for
> > single line blocks"
> > is pointing in the opposite direction.
>
> I think we have a communication failure :)
>
> The two blocks above are single line blocks, even though the line is
> wrapped. So whether or not there is an else condition or not doesn't
> matter, you shouldn't have braces at all.
Ah... It was a single line split wrapped to two lines...
Sorry for the noise.
ChenYu
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 01/29] dt-bindings: bus: add H6 DE3 bus binding
2018-10-08 8:31 ` Maxime Ripard
@ 2018-10-08 14:25 ` Jernej Škrabec
0 siblings, 0 replies; 52+ messages in thread
From: Jernej Škrabec @ 2018-10-08 14:25 UTC (permalink / raw)
To: Maxime Ripard
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi, Icenowy Zheng
Dne ponedeljek, 08. oktober 2018 ob 10:31:54 CEST je Maxime Ripard napisal(a):
> On Sun, Oct 07, 2018 at 11:38:37AM +0200, Jernej Skrabec wrote:
> > From: Icenowy Zheng <icenowy@aosc.io>
> >
> > The Allwinner H6 DE3 bus is similar to the A64 DE2 one.
> >
> > Add its compatible string with the A64 string as fallback to the
> > binding.
> >
> > Some description of the binding is modified to make it more generic.
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > ---
> >
> > Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt | 9 ++++++---
> > 1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
> > b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt index
> > 87dfb33fb3be..ac1445b95f41 100644
> > --- a/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
> > +++ b/Documentation/devicetree/bindings/bus/sun50i-de2-bus.txt
> > @@ -1,11 +1,14 @@
> > -Device tree bindings for Allwinner A64 DE2 bus
> > +Device tree bindings for Allwinner DE2/3 bus
> >
> > The Allwinner A64 DE2 is on a special bus, which needs a SRAM region
> > (SRAM C)>
> > -to be claimed for enabling the access.
> > +to be claimed for enabling the access. The DE3 on Allwinner H6 is at the
> > same +situation, and the binding also applies.
> >
> > Required properties:
> > - - compatible: Should contain "allwinner,sun50i-a64-de2"
> > + - compatible: Should be one of:
> > + - "allwinner,sun50i-a64-de2"
> > + - "allwinner,sun50i-a6-de3", "allwinner,sun50i-a64-de2"
>
> ^ that would be h6 I
> guess?
Good catch! Yes, it should.
Best regards,
Jernej
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 10/29] drm/sun4i: Rename DE2 registers related macros
2018-10-08 10:18 ` Maxime Ripard
@ 2018-10-08 14:28 ` Jernej Škrabec
2018-10-09 15:53 ` Maxime Ripard
0 siblings, 1 reply; 52+ messages in thread
From: Jernej Škrabec @ 2018-10-08 14:28 UTC (permalink / raw)
To: Maxime Ripard
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi
Dne ponedeljek, 08. oktober 2018 ob 12:18:28 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Sun, Oct 07, 2018 at 11:38:46AM +0200, Jernej Skrabec wrote:
> > In preparation to introduce DE3 support, change prefix from "SUN8I_" to
> > "DE2_". Current prefix suggest that it's valid only for one family,
> > whereas in reality, DE2 unit is used also on sun50i family.
> > Additionally, it will be easier to distinguish DE3 specific macros by
> > using "DE3_" prefix.
> >
> > No functional change in this commit.
>
> I'm not too sure about this one. There's basically two ways to look at
> this: you described the first one, and the second one would be to
> treat it as we do for the compatibles: the IP was introduced on one
> SoC family, and then got used on some other ones.
>
> Trying to always match the one you have however have a quite big
> maintainance cost, as can be shown by your patch: you always have to
> adapt comments, function names, defines, etc. This creates a lot of
> useless churns (ie, non-functional changes) in the drivers, that need
> to be written in the first place, and then reviewed.
>
> It's just not worth it.
Well, using family neutral way would mean that there is no need anymore for
adaptation in the future, but as you wish.
What prefix should I use for DE3 specific registers?
Best regards,
Jernej
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP
2018-10-08 8:51 ` Maxime Ripard
2018-10-08 9:06 ` Chen-Yu Tsai
@ 2018-10-08 14:30 ` Jernej Škrabec
1 sibling, 0 replies; 52+ messages in thread
From: Jernej Škrabec @ 2018-10-08 14:30 UTC (permalink / raw)
To: Maxime Ripard
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi, Icenowy Zheng
Dne ponedeljek, 08. oktober 2018 ob 10:51:12 CEST je Maxime Ripard napisal(a):
> On Sun, Oct 07, 2018 at 11:39:01AM +0200, Jernej Skrabec wrote:
> > From: Icenowy Zheng <icenowy@aosc.io>
> >
> > Some SoCs, such as H6, doesn't have a full-featured TCON TOP.
> >
> > Add quirks support for TCON TOP.
> >
> > Currently the presence of TCON_TV1 and DSI is controlled via the quirks
> > structure.
> >
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > ---
> >
> > drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 43 ++++++++++++++++++++------
> > 1 file changed, 34 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c index 37158548b447..ed13233cad88
> > 100644
> > --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > @@ -9,11 +9,17 @@
> >
> > #include <linux/component.h>
> > #include <linux/device.h>
> > #include <linux/module.h>
> >
> > +#include <linux/of_device.h>
> >
> > #include <linux/of_graph.h>
> > #include <linux/platform_device.h>
> >
> > #include "sun8i_tcon_top.h"
> >
> > +struct sun8i_tcon_top_quirks {
> > + bool has_tcon_tv1;
> > + bool has_dsi;
> > +};
> > +
> >
> > static bool sun8i_tcon_top_node_is_tcon_top(struct device_node *node)
> > {
> >
> > return !!of_match_node(sun8i_tcon_top_of_table, node);
> >
> > @@ -121,10 +127,13 @@ static int sun8i_tcon_top_bind(struct device *dev,
> > struct device *master,>
> > struct platform_device *pdev = to_platform_device(dev);
> > struct clk_hw_onecell_data *clk_data;
> > struct sun8i_tcon_top *tcon_top;
> >
> > + const struct sun8i_tcon_top_quirks *quirks;
> >
> > struct resource *res;
> > void __iomem *regs;
> > int ret, i;
> >
> > + quirks = of_device_get_match_data(&pdev->dev);
> > +
> >
> > tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
> > if (!tcon_top)
> >
> > return -ENOMEM;
> >
> > @@ -187,15 +196,23 @@ static int sun8i_tcon_top_bind(struct device *dev,
> > struct device *master,>
> > &tcon_top->reg_lock,
> > TCON_TOP_TCON_TV0_GATE, 0);
> >
> > - clk_data->hws[CLK_TCON_TOP_TV1] =
> > - sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > - &tcon_top->reg_lock,
> > - TCON_TOP_TCON_TV1_GATE, 1);
> > + if (quirks->has_tcon_tv1) {
> > + clk_data->hws[CLK_TCON_TOP_TV1] =
> > + sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
> > + &tcon_top->reg_lock,
> > + TCON_TOP_TCON_TV1_GATE, 1);
> > + } else {
> > + clk_data->hws[CLK_TCON_TOP_TV1] = NULL;
> > + }
> >
> > - clk_data->hws[CLK_TCON_TOP_DSI] =
> > - sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > - &tcon_top->reg_lock,
> > - TCON_TOP_TCON_DSI_GATE, 2);
> > + if (quirks->has_dsi) {
> > + clk_data->hws[CLK_TCON_TOP_DSI] =
> > + sun8i_tcon_top_register_gate(dev, "dsi", regs,
> > + &tcon_top->reg_lock,
> > + TCON_TOP_TCON_DSI_GATE, 2);
> > + } else {
> > + clk_data->hws[CLK_TCON_TOP_DSI] = NULL;
>
> clk_data has been kzalloc'd so its content is already NULL.
>
> And you shouldn't have brackets for single line blocks.
Ah, yes. I'm not original author so I missed that during a review. I'll fix it
in new revision.
Best regards,
Jernej
>
> with that fixed,
>
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> Maxime
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 18/29] drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock
2018-10-08 9:14 ` Maxime Ripard
@ 2018-10-08 15:09 ` Jernej Škrabec
2018-10-09 9:14 ` Maxime Ripard
0 siblings, 1 reply; 52+ messages in thread
From: Jernej Škrabec @ 2018-10-08 15:09 UTC (permalink / raw)
To: Maxime Ripard
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi
Dne ponedeljek, 08. oktober 2018 ob 11:14:06 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Sun, Oct 07, 2018 at 11:38:54AM +0200, Jernej Skrabec wrote:
> > It turns out that H6 HDMI BSP kernel driver doesn't change TMDS rate at
> > all. At this point it is not clear whether it is just not necessary or
> > it would cause some kind of issues.
> >
> > Add a quirk for it.
> >
> > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > ---
> >
> > drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 5 ++++-
> > drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 +
> > 2 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> > b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c index ec122136ee9d..e9e93f174b35
> > 100644
> > --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> > +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> > @@ -165,7 +165,9 @@ static int sun8i_dw_hdmi_bind(struct device *dev,
> > struct device *master,>
> > goto err_disable_clk_tmds;
> >
> > }
> >
> > - drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
> > + if (hdmi->quirks->set_rate)
> > + drm_encoder_helper_add(encoder,
> > + &sun8i_dw_hdmi_encoder_helper_funcs);
>
> That seems a bit backward, it only works because we only have mode_set
> at the moment, and the only thing it does is changing the clock
> rate. As soon as we change one of these two assumptions, the code will
> break.
>
> Why not just return in mode_set if that boolean is true?
My original intention was to optimize execution time a bit. If there is no
helpers registered, there is no need to call callback which does nothing. But
your way is probably more reasonable approach.
However, I'm pretty sure that even older HDMI controller doesn't need this
rate changing code. All tests shown that changing HDMI controller divider
doesn't have an effect on video or audio output. It's only there because BSP
kernel driver set rate and AW engineer said it's necessary.
>
> > drm_encoder_init(drm, encoder, &sun8i_dw_hdmi_encoder_funcs,
> >
> > DRM_MODE_ENCODER_TMDS, NULL);
> >
> > @@ -235,6 +237,7 @@ static int sun8i_dw_hdmi_remove(struct platform_device
> > *pdev)>
> > static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
> >
> > .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
> >
> > + .set_rate = true,
> >
> > };
> >
> > static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index a645b8bc9f58..f9eb663865a4
> > 100644
> > --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > @@ -173,6 +173,7 @@ struct sun8i_hdmi_phy {
> >
> > struct sun8i_dw_hdmi_quirks {
> >
> > enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
> >
> > const struct drm_display_mode *mode);
> >
> > + bool set_rate;
>
> This triggers a check in checkpatch. You should address them (and
> there's several in your series).
Till now we used bools in driver internal structures in spite of this
warnings. So should we start using unsigned int? Or maybe bitfield with
unsigned int as a base according to https://lkml.org/lkml/2017/11/21/384
As far as other issues reported by strict checkpatch go, most of them are DT
lines over 80 charachters. This was tolerated till now. Last type of issues is
that macro parameters weren't enclosed with braces. These issues won't be
reported anymore in new series because sun8i_csc.h won't be touched if I drop
patch which renames DE2 register macros (but original issue will remain).
Best regards,
Jernej
>
> With both addressed,
> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> Thanks!
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 18/29] drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock
2018-10-08 15:09 ` Jernej Škrabec
@ 2018-10-09 9:14 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2018-10-09 9:14 UTC (permalink / raw)
To: Jernej Škrabec
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 4518 bytes --]
On Mon, Oct 08, 2018 at 05:09:42PM +0200, Jernej Škrabec wrote:
> Dne ponedeljek, 08. oktober 2018 ob 11:14:06 CEST je Maxime Ripard napisal(a):
> > Hi,
> >
> > On Sun, Oct 07, 2018 at 11:38:54AM +0200, Jernej Skrabec wrote:
> > > It turns out that H6 HDMI BSP kernel driver doesn't change TMDS rate at
> > > all. At this point it is not clear whether it is just not necessary or
> > > it would cause some kind of issues.
> > >
> > > Add a quirk for it.
> > >
> > > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > > ---
> > >
> > > drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 5 ++++-
> > > drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 +
> > > 2 files changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> > > b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c index ec122136ee9d..e9e93f174b35
> > > 100644
> > > --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> > > +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> > > @@ -165,7 +165,9 @@ static int sun8i_dw_hdmi_bind(struct device *dev,
> > > struct device *master,>
> > > goto err_disable_clk_tmds;
> > >
> > > }
> > >
> > > - drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
> > > + if (hdmi->quirks->set_rate)
> > > + drm_encoder_helper_add(encoder,
> > > + &sun8i_dw_hdmi_encoder_helper_funcs);
> >
> > That seems a bit backward, it only works because we only have mode_set
> > at the moment, and the only thing it does is changing the clock
> > rate. As soon as we change one of these two assumptions, the code will
> > break.
> >
> > Why not just return in mode_set if that boolean is true?
>
> My original intention was to optimize execution time a bit. If there is no
> helpers registered, there is no need to call callback which does nothing. But
> your way is probably more reasonable approach.
>
> However, I'm pretty sure that even older HDMI controller doesn't need this
> rate changing code. All tests shown that changing HDMI controller divider
> doesn't have an effect on video or audio output. It's only there because BSP
> kernel driver set rate and AW engineer said it's necessary.
Maybe we can simply remove it then, and see if it breaks. Given the
feedback from Allwinner, I'd prefer to have the behaviour they
recommend though, at least from MMC experience, it proved to be
needed.
> >
> > > drm_encoder_init(drm, encoder, &sun8i_dw_hdmi_encoder_funcs,
> > >
> > > DRM_MODE_ENCODER_TMDS, NULL);
> > >
> > > @@ -235,6 +237,7 @@ static int sun8i_dw_hdmi_remove(struct platform_device
> > > *pdev)>
> > > static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
> > >
> > > .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
> > >
> > > + .set_rate = true,
> > >
> > > };
> > >
> > > static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
> > >
> > > diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > > b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index a645b8bc9f58..f9eb663865a4
> > > 100644
> > > --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > > +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > > @@ -173,6 +173,7 @@ struct sun8i_hdmi_phy {
> > >
> > > struct sun8i_dw_hdmi_quirks {
> > >
> > > enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
> > >
> > > const struct drm_display_mode *mode);
> > >
> > > + bool set_rate;
> >
> > This triggers a check in checkpatch. You should address them (and
> > there's several in your series).
>
> Till now we used bools in driver internal structures in spite of this
> warnings. So should we start using unsigned int? Or maybe bitfield with
> unsigned int as a base according to https://lkml.org/lkml/2017/11/21/384
That warning has been introduced pretty recently, so we do indeed have
some drivers that use a bool in their structure.
> As far as other issues reported by strict checkpatch go, most of them are DT
> lines over 80 charachters. This was tolerated till now. Last type of issues is
> that macro parameters weren't enclosed with braces. These issues won't be
> reported anymore in new series because sun8i_csc.h won't be touched if I drop
> patch which renames DE2 register macros (but original issue will remain).
Yeah, I don't worry about those.
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 10/29] drm/sun4i: Rename DE2 registers related macros
2018-10-08 14:28 ` Jernej Škrabec
@ 2018-10-09 15:53 ` Maxime Ripard
0 siblings, 0 replies; 52+ messages in thread
From: Maxime Ripard @ 2018-10-09 15:53 UTC (permalink / raw)
To: Jernej Škrabec
Cc: wens, robh+dt, sboyd, airlied, architt, a.hajda,
Laurent.pinchart, devicetree, linux-arm-kernel, linux-kernel,
linux-clk, dri-devel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 1974 bytes --]
On Mon, Oct 08, 2018 at 04:28:41PM +0200, Jernej Škrabec wrote:
> Dne ponedeljek, 08. oktober 2018 ob 12:18:28 CEST je Maxime Ripard napisal(a):
> > Hi,
> >
> > On Sun, Oct 07, 2018 at 11:38:46AM +0200, Jernej Skrabec wrote:
> > > In preparation to introduce DE3 support, change prefix from "SUN8I_" to
> > > "DE2_". Current prefix suggest that it's valid only for one family,
> > > whereas in reality, DE2 unit is used also on sun50i family.
> > > Additionally, it will be easier to distinguish DE3 specific macros by
> > > using "DE3_" prefix.
> > >
> > > No functional change in this commit.
> >
> > I'm not too sure about this one. There's basically two ways to look at
> > this: you described the first one, and the second one would be to
> > treat it as we do for the compatibles: the IP was introduced on one
> > SoC family, and then got used on some other ones.
> >
> > Trying to always match the one you have however have a quite big
> > maintainance cost, as can be shown by your patch: you always have to
> > adapt comments, function names, defines, etc. This creates a lot of
> > useless churns (ie, non-functional changes) in the drivers, that need
> > to be written in the first place, and then reviewed.
> >
> > It's just not worth it.
>
> Well, using family neutral way would mean that there is no need
> anymore for adaptation in the future, but as you wish.
If you consider only the DE case, where it has been numbered by
design, yes. If you consider all the other controllers that haven't
been (like, SPI, or the USB PHY, for example), then you end up with
two drivers that are using the same names, with no easy way to tell
which is which
> What prefix should I use for DE3 specific registers?
We should just follow the same pattern, and use the first family where
it was introduced. So sun50i, I guess?
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 15/29] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a
2018-10-07 9:38 ` [PATCH v2 15/29] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a Jernej Skrabec
@ 2018-10-09 17:40 ` Laurent Pinchart
2018-10-09 17:56 ` Ilia Mirkin
2018-10-15 17:43 ` [linux-sunxi] " Jernej Škrabec
0 siblings, 2 replies; 52+ messages in thread
From: Laurent Pinchart @ 2018-10-09 17:40 UTC (permalink / raw)
To: Jernej Skrabec
Cc: maxime.ripard, wens, robh+dt, sboyd, airlied, architt, a.hajda,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
Hi Jernej,
Thank you for the patch.
On Sunday, 7 October 2018 12:38:51 EEST Jernej Skrabec wrote:
> It turns out that even new DW HDMI controllers exhibits same magenta
> line issues as older versions.
>
> Enable workaround for v2.12a.
This doesn't affect the platforms I maintain, so I can't really test this, but
I'm wondering whether there could be other platforms using a v2.12a DW HDMI
that wouldn't need the workaround.
My platforms use a previous version, namely v2.01a. The workaround for that
version has been enabled by
commit 9c305eb442f3b371fc722ade827bbf673514123e
Author: Neil Armstrong <narmstrong@baylibre.com>
Date: Fri Feb 23 12:44:37 2018 +0100
drm: bridge: dw-hdmi: Fix overflow workaround for Amlogic Meson GX SoCs
I haven't paid too much attention to the patch back then, and have now double-
checked the HDMI output on R-Car Gen3. Enabling the workaround doesn't cause
any regression, and reverting the commit doesn't cause any issue either. I
thus wonder whether we shouldn't enable the workaround with count = 1 in the
default case instead of adding new IP core versions to the list. It would be
nice if someone from Synopsys could comment on this.
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index
> 5971976284bf..df1c7a2d6961 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -1664,6 +1664,7 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi
> *hdmi) case 0x131a:
> case 0x132a:
> case 0x201a:
> + case 0x212a:
> count = 1;
> break;
> default:
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 15/29] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a
2018-10-09 17:40 ` Laurent Pinchart
@ 2018-10-09 17:56 ` Ilia Mirkin
2018-10-09 21:23 ` Russell King - ARM Linux
2018-10-15 17:43 ` [linux-sunxi] " Jernej Škrabec
1 sibling, 1 reply; 52+ messages in thread
From: Ilia Mirkin @ 2018-10-09 17:56 UTC (permalink / raw)
To: Laurent Pinchart
Cc: jernej.skrabec, maxime.ripard, Chen-Yu Tsai, Rob Herring, sboyd,
David Airlie, Archit Taneja, Andrzej Hajda, devicetree,
linux-arm-kernel, LKML, linux-clk, dri-devel, linux-sunxi
On Tue, Oct 9, 2018 at 1:40 PM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> Hi Jernej,
>
> Thank you for the patch.
>
> On Sunday, 7 October 2018 12:38:51 EEST Jernej Skrabec wrote:
> > It turns out that even new DW HDMI controllers exhibits same magenta
> > line issues as older versions.
> >
> > Enable workaround for v2.12a.
>
> This doesn't affect the platforms I maintain, so I can't really test this, but
> I'm wondering whether there could be other platforms using a v2.12a DW HDMI
> that wouldn't need the workaround.
>
> My platforms use a previous version, namely v2.01a. The workaround for that
> version has been enabled by
>
> commit 9c305eb442f3b371fc722ade827bbf673514123e
> Author: Neil Armstrong <narmstrong@baylibre.com>
> Date: Fri Feb 23 12:44:37 2018 +0100
>
> drm: bridge: dw-hdmi: Fix overflow workaround for Amlogic Meson GX SoCs
>
> I haven't paid too much attention to the patch back then, and have now double-
> checked the HDMI output on R-Car Gen3. Enabling the workaround doesn't cause
> any regression, and reverting the commit doesn't cause any issue either. I
> thus wonder whether we shouldn't enable the workaround with count = 1 in the
> default case instead of adding new IP core versions to the list. It would be
> nice if someone from Synopsys could comment on this.
I hope this comment isn't *incredibly* off-topic, but we encountered a
similar issue with NVIDIA (and I believe AMD) hardware a while back,
related to HDMI. This was due to infoframes not being sent, but
(perhaps) HDMI Audio being enabled.
This was a single vertical(!) line. It was described as "purple", but
not sure that's distinguishable from "magenta" by most people. [ Fixed
by a522946174 on nouveau, sample bug report
https://bugs.freedesktop.org/show_bug.cgi?id=79912 ]
Cheers,
-ilia
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v2 15/29] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a
2018-10-09 17:56 ` Ilia Mirkin
@ 2018-10-09 21:23 ` Russell King - ARM Linux
0 siblings, 0 replies; 52+ messages in thread
From: Russell King - ARM Linux @ 2018-10-09 21:23 UTC (permalink / raw)
To: Ilia Mirkin
Cc: Laurent Pinchart, devicetree, jernej.skrabec, Andrzej Hajda,
maxime.ripard, David Airlie, linux-sunxi, Archit Taneja,
dri-devel, LKML, sboyd, Chen-Yu Tsai, Rob Herring, linux-clk,
linux-arm-kernel
On Tue, Oct 09, 2018 at 01:56:04PM -0400, Ilia Mirkin wrote:
> On Tue, Oct 9, 2018 at 1:40 PM Laurent Pinchart
> <laurent.pinchart@ideasonboard.com> wrote:
> > commit 9c305eb442f3b371fc722ade827bbf673514123e
> > Author: Neil Armstrong <narmstrong@baylibre.com>
> > Date: Fri Feb 23 12:44:37 2018 +0100
> >
> > drm: bridge: dw-hdmi: Fix overflow workaround for Amlogic Meson GX SoCs
> >
> > I haven't paid too much attention to the patch back then, and have now double-
> > checked the HDMI output on R-Car Gen3. Enabling the workaround doesn't cause
> > any regression, and reverting the commit doesn't cause any issue either. I
> > thus wonder whether we shouldn't enable the workaround with count = 1 in the
> > default case instead of adding new IP core versions to the list. It would be
> > nice if someone from Synopsys could comment on this.
>
> I hope this comment isn't *incredibly* off-topic, but we encountered a
> similar issue with NVIDIA (and I believe AMD) hardware a while back,
> related to HDMI. This was due to infoframes not being sent, but
> (perhaps) HDMI Audio being enabled.
You're probably right about the infoframes. The errata documentation
for this workaround on iMX6 states:
Each time one writes to some FC registers, and depending on the clock relation of sfr clk and tmds
clk, some of these train of pulses (when these registers are configured in sequence), may not be
caught by the arithmetic unit while it is busy processing/updating the first ones, so, it gets wrong
video timing values, although the registers FC_* hold correct values. Even a soft reset will not
make the arithmetic unit update correctly. Video will still pass correctly to the HDMI, but packets
would not because the frame composer is holding internally incorrect video timing and this will
quickly build up and overflow the packet FIFOs.
So, the workaround is about kicking the frame composer so that the
packets (iow, non-video data) are passed through correctly.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [linux-sunxi] [PATCH v2 04/29] clk: sunxi-ng: h6: Set video PLLs limits
2018-10-07 9:38 ` [PATCH v2 04/29] clk: sunxi-ng: h6: Set video PLLs limits Jernej Skrabec
@ 2018-10-12 8:13 ` Jagan Teki
2018-10-12 9:03 ` Chen-Yu Tsai
0 siblings, 1 reply; 52+ messages in thread
From: Jagan Teki @ 2018-10-12 8:13 UTC (permalink / raw)
To: jernej.skrabec, maxime.ripard, wens
Cc: robh+dt, sboyd, airlied, architt, a.hajda, Laurent.pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
On Sunday 07 October 2018 03:08 PM, Jernej Skrabec wrote:
> Video PLL factors can be set in a way that final PLL rate is outside
> stable range. H6 user manual specifically says that N factor should not
> be below 12. While it doesn't says anything about maximum stable rate, it
Manual says "In application, PLL_FACTOR_N should be more than or equal
to 11" can't it be 11?
> is clear that PLL doesn't work at 6.096 GHz (254 * 24 MHz).
>
> Set minimum allowed PLL video rate to 288 MHz (12 * 24 MHz) and maximum
> to 2.4 GHz, which is maximum in BSP driver.
Is this max freq from here [1]
[1]
https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clk/sunxi/clk-sun50iw6.c#L164
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [linux-sunxi] [PATCH v2 04/29] clk: sunxi-ng: h6: Set video PLLs limits
2018-10-12 8:13 ` [linux-sunxi] " Jagan Teki
@ 2018-10-12 9:03 ` Chen-Yu Tsai
0 siblings, 0 replies; 52+ messages in thread
From: Chen-Yu Tsai @ 2018-10-12 9:03 UTC (permalink / raw)
To: Jagan Teki
Cc: Jernej Skrabec, Maxime Ripard, Rob Herring, Stephen Boyd,
David Airlie, Archit Taneja, Andrzej Hajda, Laurent Pinchart,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel,
linux-sunxi
On Fri, Oct 12, 2018 at 4:14 PM Jagan Teki <jagan@openedev.com> wrote:
>
> On Sunday 07 October 2018 03:08 PM, Jernej Skrabec wrote:
> > Video PLL factors can be set in a way that final PLL rate is outside
> > stable range. H6 user manual specifically says that N factor should not
> > be below 12. While it doesn't says anything about maximum stable rate, it
>
> Manual says "In application, PLL_FACTOR_N should be more than or equal
> to 11" can't it be 11?
PLL_FACTOR_N is the raw value, which starts from 0.
That translates to an actual factor of 12 used in the calculations.
> > is clear that PLL doesn't work at 6.096 GHz (254 * 24 MHz).
> >
> > Set minimum allowed PLL video rate to 288 MHz (12 * 24 MHz) and maximum
> > to 2.4 GHz, which is maximum in BSP driver.
>
> Is this max freq from here [1]
>
> [1]
> https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clk/sunxi/clk-sun50iw6.c#L164
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [linux-sunxi] Re: [PATCH v2 15/29] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a
2018-10-09 17:40 ` Laurent Pinchart
2018-10-09 17:56 ` Ilia Mirkin
@ 2018-10-15 17:43 ` Jernej Škrabec
1 sibling, 0 replies; 52+ messages in thread
From: Jernej Škrabec @ 2018-10-15 17:43 UTC (permalink / raw)
To: linux-sunxi, laurent.pinchart
Cc: maxime.ripard, wens, robh+dt, sboyd, airlied, architt, a.hajda,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, dri-devel
Hi,
Dne torek, 09. oktober 2018 ob 19:40:44 CEST je Laurent Pinchart napisal(a):
> Hi Jernej,
>
> Thank you for the patch.
>
> On Sunday, 7 October 2018 12:38:51 EEST Jernej Skrabec wrote:
> > It turns out that even new DW HDMI controllers exhibits same magenta
> > line issues as older versions.
> >
> > Enable workaround for v2.12a.
>
> This doesn't affect the platforms I maintain, so I can't really test this,
> but I'm wondering whether there could be other platforms using a v2.12a DW
> HDMI that wouldn't need the workaround.
>
> My platforms use a previous version, namely v2.01a. The workaround for that
> version has been enabled by
>
> commit 9c305eb442f3b371fc722ade827bbf673514123e
> Author: Neil Armstrong <narmstrong@baylibre.com>
> Date: Fri Feb 23 12:44:37 2018 +0100
>
> drm: bridge: dw-hdmi: Fix overflow workaround for Amlogic Meson GX SoCs
>
> I haven't paid too much attention to the patch back then, and have now
> double- checked the HDMI output on R-Car Gen3. Enabling the workaround
> doesn't cause any regression, and reverting the commit doesn't cause any
> issue either. I thus wonder whether we shouldn't enable the workaround with
> count = 1 in the default case instead of adding new IP core versions to the
> list. It would be nice if someone from Synopsys could comment on this.
I was thinking about that too, or even having parameter in dw_hdmi_plat_data
which would tell how many times to repeat workaround procedure for a specific
platform. But this might be an overkill.
Best regards,
Jernej
>
> > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > ---
> >
> > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index
> > 5971976284bf..df1c7a2d6961 100644
> > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > @@ -1664,6 +1664,7 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi
> >
> > *hdmi) case 0x131a:
> > case 0x132a:
> >
> > case 0x201a:
> > + case 0x212a:
> > count = 1;
> > break;
> >
> > default:
^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2018-10-15 17:43 UTC | newest]
Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-07 9:38 [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 01/29] dt-bindings: bus: add H6 DE3 bus binding Jernej Skrabec
2018-10-08 8:31 ` Maxime Ripard
2018-10-08 14:25 ` Jernej Škrabec
2018-10-07 9:38 ` [PATCH v2 02/29] clk: sunxi-ng: Adjust MP clock parent rate when allowed Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 03/29] clk: sunxi-ng: Use u64 for calculation of NM rate Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 04/29] clk: sunxi-ng: h6: Set video PLLs limits Jernej Skrabec
2018-10-12 8:13 ` [linux-sunxi] " Jagan Teki
2018-10-12 9:03 ` Chen-Yu Tsai
2018-10-07 9:38 ` [PATCH v2 05/29] dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 06/29] clk: sunxi-ng: Add support for H6 DE3 clocks Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 07/29] dt-bindings: display: sun4i-drm: Add H6 display engine compatibles Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 08/29] drm/sun4i: Add compatible for H6 display engine Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 09/29] drm/sun4i: Rework DE2 register defines Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 10/29] drm/sun4i: Rename DE2 registers related macros Jernej Skrabec
2018-10-08 10:18 ` Maxime Ripard
2018-10-08 14:28 ` Jernej Škrabec
2018-10-09 15:53 ` Maxime Ripard
2018-10-07 9:38 ` [PATCH v2 11/29] drm/sun4i: Fix DE2 mixer size Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 12/29] drm/sun4i: Disable unused DE2 sub-engines Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 13/29] drm/sun4i: Add basic support for DE3 Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 14/29] drm/sun4i: Add support for H6 DE3 mixer 0 Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 15/29] drm/bridge/synopsys: dw-hdmi: Enable workaround for v2.12a Jernej Skrabec
2018-10-09 17:40 ` Laurent Pinchart
2018-10-09 17:56 ` Ilia Mirkin
2018-10-09 21:23 ` Russell King - ARM Linux
2018-10-15 17:43 ` [linux-sunxi] " Jernej Škrabec
2018-10-07 9:38 ` [PATCH v2 16/29] drm/sun4i: Not all DW HDMI controllers has scrambled addresses Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 17/29] drm/sun4i: dw-hdmi: Make mode_valid function configurable Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 18/29] drm/sun4i: dw-hdmi: Add quirk for setting TMDS clock Jernej Skrabec
2018-10-08 9:14 ` Maxime Ripard
2018-10-08 15:09 ` Jernej Škrabec
2018-10-09 9:14 ` Maxime Ripard
2018-10-07 9:38 ` [PATCH v2 19/29] dt-bindings: display: sunxi: add DT binding for Allwinner H6 DW HDMI Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 20/29] drm/sun4i: Add support for H6 DW HDMI controller Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 21/29] drm/sun4i: dw-hdmi-phy: Reorder quirks by family Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 22/29] drm/sun4i: Add support for Synopsys HDMI PHY Jernej Skrabec
2018-10-07 9:38 ` [PATCH v2 23/29] drm/sun4i: Add support for H6 " Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 24/29] drm/sun4i: Initialize registers in tcon-top driver Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 25/29] drm: sun4i: add quirks for TCON TOP Jernej Skrabec
2018-10-08 8:51 ` Maxime Ripard
2018-10-08 9:06 ` Chen-Yu Tsai
2018-10-08 10:20 ` Maxime Ripard
2018-10-08 10:50 ` Chen-Yu Tsai
2018-10-08 12:33 ` Maxime Ripard
2018-10-08 13:10 ` Chen-Yu Tsai
2018-10-08 14:30 ` Jernej Škrabec
2018-10-07 9:39 ` [PATCH v2 26/29] dt-bindings: display: sun4i-drm: document H6 " Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 27/29] drm: sun4i: add support for " Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 28/29] arm64: dts: allwinner: h6: Add HDMI pipeline Jernej Skrabec
2018-10-07 9:39 ` [PATCH v2 29/29] arm64: dts: allwinner: h6: Enable HDMI output on Pine H64 board Jernej Skrabec
2018-10-07 9:50 ` [linux-sunxi] [PATCH v2 00/29] Allwinner H6 DE3 and HDMI support Jernej Škrabec
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