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Mon, 15 Oct 2018 20:55:56 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::bd60:9d30:b818:b828]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::bd60:9d30:b818:b828%3]) with mapi id 15.20.1228.027; Mon, 15 Oct 2018 20:55:56 +0000 From: "Moger, Babu" To: "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "reinette.chatre@intel.com" , "fenghua.yu@intel.com" , "james.morse@arm.com" , "tony.luck@intel.com" , "corbet@lwn.net" CC: "x86@kernel.org" , "peterz@infradead.org" , "Moger, Babu" , "pombredanne@nexb.com" , "gregkh@linuxfoundation.org" , "kstewart@linuxfoundation.org" , "bp@suse.de" , "rafael.j.wysocki@intel.com" , "ak@linux.intel.com" , "kirill.shutemov@linux.intel.com" , "xiaochen.shen@intel.com" , "colin.king@canonical.com" , "Hurwitz, Sherry" , "Lendacky, Thomas" , "pbonzini@redhat.com" , "dwmw@amazon.co.uk" , "luto@kernel.org" , "jroedel@suse.de" , "jannh@google.com" , "dima@arista.com" , "jpoimboe@redhat.com" , "vkuznets@redhat.com" , "linux-kernel@vger.kernel.org" , "mchehab+samsung@kernel.org" , "davem@davemloft.net" , "akpm@linux-foundation.org" , "arnd@arndb.de" Subject: [PATCH v4 11/13] arch/x86: Introduce QOS feature for AMD Thread-Topic: [PATCH v4 11/13] arch/x86: Introduce QOS feature for AMD Thread-Index: AQHUZMl3qlKuTXhw4k+veXXr0nV/qQ== Date: Mon, 15 Oct 2018 20:55:56 +0000 Message-ID: <20181015205514.25387-12-babu.moger@amd.com> References: <20181015205514.25387-1-babu.moger@amd.com> In-Reply-To: <20181015205514.25387-1-babu.moger@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR02CA0017.namprd02.prod.outlook.com (2603:10b6:805:a2::30) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR12MB1850;20:NVZ7G6+NsdCYsbLAhmep0E4+d+6ZIjCss7FLBIvkLzUpFjb3YpHa5NhFFLVoQI85+RjUScGpuu5XS1ix/Fed44HxyXQjPUuUYSCjnD/mihKRI3e6ngCBBcoHZyYIYfF9K7Xbw9sJOi6B2yonfp9MrO0TW3mzaR23nh4Lqvl3mYqYD+vs9p2uke7PuVh71NbbS7JAE07/0WzJm2YEQFaxKcq2va60cc86k3Xmey640UZE41h8Fu/Ar9IHPsjSanKq x-ms-office365-filtering-correlation-id: a7a5fcec-7aeb-4d5a-5334-08d632e09a27 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020);SRVR:DM5PR12MB1850; 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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: U8da3JBqkI4d/PepZg3GBYkFnsb5JPEBVcoGLvxTcFo8AJHrv228awrTdSA4NHjqqVjPl4VyWzyIt1f88nnvuoKmRZ+Q58MK6UYpLr8hTfNACOe5/iLXOH8y+t7jCcT6TELqX4rPnXOpBxJ5rVNOA7uWKNAZfua4m2bsD7zjWMJpOJ2jedZpqPu+5Bof7tO62avuqFq5Y0mt2dcb82LOkTz+eLwYKJ9gJFfkFpy5CspR3CLM/4SWo2xlIbeJ/FmhSbBaMvlX4YX31Y5RxG4KYINpJtgwi64jzaguwkiI7I7CEADjrxLm0fo6DFdVbHBplVGMtEFn/ulxJhAPOgXViFIvOnHyQf9tpMUAIS3fLa8= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7a5fcec-7aeb-4d5a-5334-08d632e09a27 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Oct 2018 20:55:56.4498 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1850 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enables QOS feature on AMD. Following QoS sub-features are supported in AMD if the underlying hardware supports it. - L3 Cache allocation enforcement - L3 Cache occupancy monitoring - L3 Code-Data Prioritization support - Memory Bandwidth Enforcement(Allocation) The specification for this feature is available at https://developer.amd.com/wp-content/resources/56375.pdf There are differences in the way some of the features are implemented. Separate those functions and add those as vendor specific functions. The major difference is in MBA feature. - AMD uses CPUID leaf 0x80000020 to initialize the MBA features. - AMD uses direct bandwidth value instead of delay based on bandwidth values. - MSR register base addresses are different for MBA. - Also AMD allows non-contiguous L3 cache bit masks. Adds following functions to take care of the differences. rdt_get_mem_config_amd : MBA initialization function parse_bw_amd : Bandwidth parsing mba_wrmsr_amd: Writes bandwidth value cbm_validate_amd : L3 cache bitmask validation Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl.c | 69 +++++++++++++++++++++- arch/x86/kernel/cpu/resctrl.h | 5 ++ arch/x86/kernel/cpu/resctrl_ctrlmondata.c | 70 +++++++++++++++++++++++ 3 files changed, 142 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl.c b/arch/x86/kernel/cpu/resctrl.c index 9dd96e190f34..45f7ee7562ee 100644 --- a/arch/x86/kernel/cpu/resctrl.c +++ b/arch/x86/kernel/cpu/resctrl.c @@ -61,6 +61,9 @@ mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m= , struct rdt_resource *r); static void cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *= r); +static void +mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, + struct rdt_resource *r); =20 #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains) =20 @@ -280,6 +283,31 @@ static bool rdt_get_mem_config(struct rdt_resource *r) return true; } =20 +static bool rdt_get_mem_config_amd(struct rdt_resource *r) +{ + union cpuid_0x10_3_eax eax; + union cpuid_0x10_x_edx edx; + u32 ebx, ecx; + + cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full); + r->num_closid =3D edx.split.cos_max + 1; + r->default_ctrl =3D MAX_MBA_BW_AMD; + + /* AMD does not use delay. Set delay_linear to false by default */ + r->membw.delay_linear =3D false; + + /* FIX ME - May need to be read from MSR */ + r->membw.min_bw =3D 0; + r->membw.bw_gran =3D 1; + /* Max value is 2048, Data width should be 4 in decimal */ + r->data_width =3D 4; + + r->alloc_capable =3D true; + r->alloc_enabled =3D true; + + return true; +} + static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) { union cpuid_0x10_1_eax eax; @@ -339,6 +367,16 @@ static int get_cache_id(int cpu, int level) return -1; } =20 +static void +mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resour= ce *r) +{ + unsigned int i; + + /* Write the bw values for mba. */ + for (i =3D m->low; i < m->high; i++) + wrmsrl(r->msr_base + i, d->ctrl_val[i]); +} + /* * Map the memory b/w percentage value to delay values * that can be written to QOS_MSRs. @@ -786,8 +824,13 @@ static bool __init rdt_cpu_has(int flag) static __init bool rdt_mba_config(void) { if (rdt_cpu_has(X86_FEATURE_MBA)) { - if (rdt_get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA])) - return true; + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) { + if (rdt_get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA])) + return true; + } else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) { + if (rdt_get_mem_config_amd(&rdt_resources_all[RDT_RESOURCE_MBA])) + return true; + } } =20 return false; @@ -888,10 +931,32 @@ static __init void rdt_init_res_defs_intel(void) } } =20 +static __init void rdt_init_res_defs_amd(void) +{ + struct rdt_resource *r; + + for_each_rdt_resource(r) { + if (r->rid =3D=3D RDT_RESOURCE_L3 || + r->rid =3D=3D RDT_RESOURCE_L3DATA || + r->rid =3D=3D RDT_RESOURCE_L3CODE || + r->rid =3D=3D RDT_RESOURCE_L2 || + r->rid =3D=3D RDT_RESOURCE_L2DATA || + r->rid =3D=3D RDT_RESOURCE_L2CODE) + r->cbm_validate =3D cbm_validate_amd; + else if (r->rid =3D=3D RDT_RESOURCE_MBA) { + r->msr_base =3D IA32_MBA_BW_BASE; + r->msr_update =3D mba_wrmsr_amd; + r->parse_ctrlval =3D parse_bw_amd; + } + } +} + static __init void rdt_init_res_defs(void) { if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) rdt_init_res_defs_intel(); + else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + rdt_init_res_defs_amd(); } =20 static enum cpuhp_state rdt_online; diff --git a/arch/x86/kernel/cpu/resctrl.h b/arch/x86/kernel/cpu/resctrl.h index 825d5571539e..3b8b5ade77ab 100644 --- a/arch/x86/kernel/cpu/resctrl.h +++ b/arch/x86/kernel/cpu/resctrl.h @@ -11,6 +11,7 @@ #define IA32_L3_CBM_BASE 0xc90 #define IA32_L2_CBM_BASE 0xd10 #define IA32_MBA_THRTL_BASE 0xd50 +#define IA32_MBA_BW_BASE 0xc0000200 =20 #define IA32_QM_CTR 0x0c8e #define IA32_QM_EVTSEL 0x0c8d @@ -34,6 +35,7 @@ #define MAX_MBA_BW 100u #define MBA_IS_LINEAR 0x4 #define MBA_MAX_MBPS U32_MAX +#define MAX_MBA_BW_AMD 0x800 =20 #define RMID_VAL_ERROR BIT_ULL(63) #define RMID_VAL_UNAVAIL BIT_ULL(62) @@ -451,6 +453,8 @@ int parse_cbm(struct rdt_parse_data *data, struct rdt_r= esource *r, struct rdt_domain *d); int parse_bw_intel(struct rdt_parse_data *data, struct rdt_resource *r, struct rdt_domain *d); +int parse_bw_amd(struct rdt_parse_data *data, struct rdt_resource *r, + struct rdt_domain *d); =20 extern struct mutex rdtgroup_mutex; =20 @@ -583,5 +587,6 @@ bool has_busy_rmid(struct rdt_resource *r, struct rdt_d= omain *d); void __check_limbo(struct rdt_domain *d, bool force_free); void update_mba_bw_intel(struct rdtgroup *rgrp, struct rdt_domain *dom_mbm= ); bool cbm_validate_intel(char *buf, u32 *data, struct rdt_resource *r); +bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r); =20 #endif /* _ASM_X86_RESCTRL_H */ diff --git a/arch/x86/kernel/cpu/resctrl_ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl_ctrlmondata.c index 867da06223b5..d88898dba23d 100644 --- a/arch/x86/kernel/cpu/resctrl_ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl_ctrlmondata.c @@ -28,6 +28,52 @@ #include #include "resctrl.h" =20 +/* + * Check whether MBA bandwidth percentage value is correct. The value is + * checked against the minimum and max bandwidth values specified by the + * hardware. The allocated bandwidth percentage is rounded to the next + * control step available on the hardware. + */ +static bool bw_validate_amd(char *buf, unsigned long *data, + struct rdt_resource *r) +{ + unsigned long bw; + int ret; + + ret =3D kstrtoul(buf, 10, &bw); + if (ret) { + rdt_last_cmd_printf("Non-decimal digit in MB value %s\n", buf); + return false; + } + + if (bw < r->membw.min_bw || bw > r->default_ctrl) { + rdt_last_cmd_printf("MB value %ld out of range [%d,%d]\n", bw, + r->membw.min_bw, r->default_ctrl); + return false; + } + + *data =3D roundup(bw, (unsigned long)r->membw.bw_gran); + return true; +} + +int parse_bw_amd(struct rdt_parse_data *data, struct rdt_resource *r, + struct rdt_domain *d) +{ + unsigned long bw_val; + + if (d->have_new_ctrl) { + rdt_last_cmd_printf("duplicate domain %d\n", d->id); + return -EINVAL; + } + + if (!bw_validate_amd(data->buf, &bw_val, r)) + return -EINVAL; + d->new_ctrl =3D bw_val; + d->have_new_ctrl =3D true; + + return 0; +} + /* * Check whether MBA bandwidth percentage value is correct. The value is * checked against the minimum and max bandwidth values specified by the @@ -123,6 +169,30 @@ bool cbm_validate_intel(char *buf, u32 *data, struct r= dt_resource *r) return true; } =20 +/* + * Check whether a cache bit mask is valid. AMD allows non-contiguous + * bitmasks + */ +bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r) +{ + unsigned long val; + int ret; + + ret =3D kstrtoul(buf, 16, &val); + if (ret) { + rdt_last_cmd_printf("non-hex character in mask %s\n", buf); + return false; + } + + if (val > r->default_ctrl) { + rdt_last_cmd_puts("mask out of range\n"); + return false; + } + + *data =3D val; + return true; +} + /* * Read one cache bit mask (hex). Check that it is valid for the current * resource type. --=20 2.17.1