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* [PATCH 0/2] arm64: dts: qcom: sdm845: Add UFS DT nodes
@ 2018-10-17 17:23 Evan Green
  2018-10-17 17:23 ` [PATCH 1/2] arm64: dts: qcom: sdm845: add UFS controller Evan Green
  2018-10-17 17:23 ` [PATCH 2/2] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Evan Green
  0 siblings, 2 replies; 6+ messages in thread
From: Evan Green @ 2018-10-17 17:23 UTC (permalink / raw)
  To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
	linux-arm-msm, linux-soc, devicetree, linux-kernel
  Cc: swboyd, dianders, Evan Green

This series adds the DT nodes for the Universal Flash Storage controller
present on the SDM845, and activates it for the MTP reference platform.

This series applies atop the for-next branch of:
https://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git
because it needs the regulator names.

Can Guo (1):
  arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp

Evan Green (1):
  arm64: dts: qcom: sdm845: add UFS controller

 arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 11 +++++
 arch/arm64/boot/dts/qcom/sdm845.dtsi    | 66 +++++++++++++++++++++++++
 2 files changed, 77 insertions(+)

-- 
2.19.1.331.ge82ca0e54c-goog


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/2] arm64: dts: qcom: sdm845: add UFS controller
  2018-10-17 17:23 [PATCH 0/2] arm64: dts: qcom: sdm845: Add UFS DT nodes Evan Green
@ 2018-10-17 17:23 ` Evan Green
  2018-10-18 11:33   ` Vivek Gautam
  2018-10-17 17:23 ` [PATCH 2/2] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Evan Green
  1 sibling, 1 reply; 6+ messages in thread
From: Evan Green @ 2018-10-17 17:23 UTC (permalink / raw)
  To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
	linux-arm-msm, linux-soc, devicetree, linux-kernel
  Cc: swboyd, dianders, Evan Green

This change adds the UFS controller and PHY to SDM845.

Signed-off-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 66 ++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b72bdb0a31a5..20b2c258816a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -808,6 +808,72 @@
 			};
 		};
 
+		ufshc1: ufshc@1d84000 {
+			compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
+				     "jedec,ufs-2.0";
+			reg = <0x1d84000 0x2500>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&ufsphy1_lanes>;
+			phy-names = "ufsphy";
+			lanes-per-direction = <2>;
+			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			clock-names =
+				"core_clk",
+				"bus_aggr_clk",
+				"iface_clk",
+				"core_clk_unipro",
+				"ref_clk",
+				"tx_lane0_sync_clk",
+				"rx_lane0_sync_clk",
+				"rx_lane1_sync_clk";
+			clocks =
+				<&gcc GCC_UFS_PHY_AXI_CLK>,
+				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				<&gcc GCC_UFS_PHY_AHB_CLK>,
+				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				<&rpmhcc RPMH_CXO_CLK>,
+				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+			freq-table-hz =
+				<50000000 200000000>,
+				<0 0>,
+				<0 0>,
+				<37500000 150000000>,
+				<0 0>,
+				<0 0>,
+				<0 0>,
+				<0 0>;
+
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			status = "disabled";
+		};
+
+		ufsphy1: ufsphy@1d87000 {
+			compatible = "qcom,sdm845-qmp-ufs-phy";
+			reg = <0x1d87000 0x18c>;
+			#clock-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clock-names = "ref",
+				      "ref_aux";
+			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+			status = "disabled";
+
+			ufsphy1_lanes: lanes@1d87400 {
+				reg = <0x1d87400 0x108>,
+				      <0x1d87600 0x1e0>,
+				      <0x1d87c00 0x1dc>;
+				#phy-cells = <0>;
+			};
+		};
+
 		tcsr_mutex_regs: syscon@1f40000 {
 			compatible = "syscon";
 			reg = <0x1f40000 0x40000>;
-- 
2.16.4


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/2] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp
  2018-10-17 17:23 [PATCH 0/2] arm64: dts: qcom: sdm845: Add UFS DT nodes Evan Green
  2018-10-17 17:23 ` [PATCH 1/2] arm64: dts: qcom: sdm845: add UFS controller Evan Green
@ 2018-10-17 17:23 ` Evan Green
  2018-10-18 11:34   ` Vivek Gautam
  1 sibling, 1 reply; 6+ messages in thread
From: Evan Green @ 2018-10-17 17:23 UTC (permalink / raw)
  To: Andy Gross, David Brown, Rob Herring, Mark Rutland,
	linux-arm-msm, linux-soc, devicetree, linux-kernel
  Cc: swboyd, dianders, Can Guo, Evan Green

From: Can Guo <cang@codeaurora.org>

This change enables the UFS host controller and PHY on sdm845-mtp.

Signed-off-by: Can Guo <cang@codeaurora.org>
Signed-off-by: Evan Green <evgreen@chromium.org>
---
I was unable to test this on an MTP, if somebody could give this a try I would
be grateful. This applies atop agross/for-next, since it needs the regulators.

 arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index eedfaf8922e2..d5fddea71a85 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -356,6 +356,20 @@
 	status = "okay";
 };
 
+&ufshc1 {
+	status = "okay";
+
+	vcc-supply = <&vreg_l20a_2p95>;
+	vcc-max-microamp = <600000>;
+};
+
+&ufsphy1 {
+	status = "okay";
+
+	vdda-phy-supply = <&vdda_ufs1_core>;
+	vdda-pll-supply = <&vdda_ufs1_1p2>;
+};
+
 &usb_1 {
 	status = "okay";
 };
-- 
2.16.4


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] arm64: dts: qcom: sdm845: add UFS controller
  2018-10-17 17:23 ` [PATCH 1/2] arm64: dts: qcom: sdm845: add UFS controller Evan Green
@ 2018-10-18 11:33   ` Vivek Gautam
  2018-10-18 15:37     ` Evan Green
  0 siblings, 1 reply; 6+ messages in thread
From: Vivek Gautam @ 2018-10-18 11:33 UTC (permalink / raw)
  To: evgreen
  Cc: Andy Gross, David Brown, robh+dt, Mark Rutland, linux-arm-msm,
	open list:ARM/QUALCOMM SUPPORT,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, swboyd, Doug Anderson

Hi Evan,

On Wed, Oct 17, 2018 at 10:55 PM Evan Green <evgreen@chromium.org> wrote:
>
> This change adds the UFS controller and PHY to SDM845.
>
> Signed-off-by: Evan Green <evgreen@chromium.org>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 66 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 66 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index b72bdb0a31a5..20b2c258816a 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -808,6 +808,72 @@
>                         };
>                 };
>
> +               ufshc1: ufshc@1d84000 {
> +                       compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
> +                                    "jedec,ufs-2.0";
> +                       reg = <0x1d84000 0x2500>;
> +                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +                       phys = <&ufsphy1_lanes>;
> +                       phy-names = "ufsphy";
> +                       lanes-per-direction = <2>;
> +                       power-domains = <&gcc UFS_PHY_GDSC>;
> +
> +                       clock-names =
> +                               "core_clk",
> +                               "bus_aggr_clk",
> +                               "iface_clk",
> +                               "core_clk_unipro",
> +                               "ref_clk",
> +                               "tx_lane0_sync_clk",
> +                               "rx_lane0_sync_clk",
> +                               "rx_lane1_sync_clk";
> +                       clocks =
> +                               <&gcc GCC_UFS_PHY_AXI_CLK>,
> +                               <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> +                               <&gcc GCC_UFS_PHY_AHB_CLK>,
> +                               <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> +                               <&rpmhcc RPMH_CXO_CLK>,
> +                               <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> +                               <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> +                               <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> +                       freq-table-hz =
> +                               <50000000 200000000>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <37500000 150000000>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>,
> +                               <0 0>;
> +
> +                       resets = <&gcc GCC_UFS_PHY_BCR>;
> +                       reset-names = "rst";
> +
> +                       status = "disabled";
> +               };
> +
> +               ufsphy1: ufsphy@1d87000 {

nit: s/ufsphy@1d87000/phy@1d87000

> +                       compatible = "qcom,sdm845-qmp-ufs-phy";
> +                       reg = <0x1d87000 0x18c>;
> +                       #clock-cells = <1>;

why do we need this clock-cells? ufsphy i think is not providing any
clocks. Is it?
Rest looks good.

Best regards
Vivek

> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges;
> +                       clock-names = "ref",
> +                                     "ref_aux";
> +                       clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
> +                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> +
> +                       status = "disabled";
> +
> +                       ufsphy1_lanes: lanes@1d87400 {
> +                               reg = <0x1d87400 0x108>,
> +                                     <0x1d87600 0x1e0>,
> +                                     <0x1d87c00 0x1dc>;
> +                               #phy-cells = <0>;
> +                       };
> +               };
> +
>                 tcsr_mutex_regs: syscon@1f40000 {
>                         compatible = "syscon";
>                         reg = <0x1f40000 0x40000>;
> --
> 2.16.4
>


-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp
  2018-10-17 17:23 ` [PATCH 2/2] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Evan Green
@ 2018-10-18 11:34   ` Vivek Gautam
  0 siblings, 0 replies; 6+ messages in thread
From: Vivek Gautam @ 2018-10-18 11:34 UTC (permalink / raw)
  To: evgreen
  Cc: Andy Gross, David Brown, robh+dt, Mark Rutland, linux-arm-msm,
	open list:ARM/QUALCOMM SUPPORT,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, swboyd, Doug Anderson, Can Guo

On Wed, Oct 17, 2018 at 10:55 PM Evan Green <evgreen@chromium.org> wrote:
>
> From: Can Guo <cang@codeaurora.org>
>
> This change enables the UFS host controller and PHY on sdm845-mtp.
>
> Signed-off-by: Can Guo <cang@codeaurora.org>
> Signed-off-by: Evan Green <evgreen@chromium.org>
> ---
> I was unable to test this on an MTP, if somebody could give this a try I would
> be grateful. This applies atop agross/for-next, since it needs the regulators.
>
>  arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> index eedfaf8922e2..d5fddea71a85 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> @@ -356,6 +356,20 @@
>         status = "okay";
>  };
>
> +&ufshc1 {
> +       status = "okay";
> +
> +       vcc-supply = <&vreg_l20a_2p95>;
> +       vcc-max-microamp = <600000>;
> +};
> +
> +&ufsphy1 {
> +       status = "okay";
> +
> +       vdda-phy-supply = <&vdda_ufs1_core>;
> +       vdda-pll-supply = <&vdda_ufs1_1p2>;
> +};
> +
>  &usb_1 {
>         status = "okay";
>  };
> --
> 2.16.4
>

Looks good.
Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org>

Best regards
Vivek

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] arm64: dts: qcom: sdm845: add UFS controller
  2018-10-18 11:33   ` Vivek Gautam
@ 2018-10-18 15:37     ` Evan Green
  0 siblings, 0 replies; 6+ messages in thread
From: Evan Green @ 2018-10-18 15:37 UTC (permalink / raw)
  To: vivek.gautam
  Cc: Andy Gross, David Brown, robh+dt, mark.rutland, linux-arm-msm,
	linux-soc, devicetree, linux-kernel, swboyd, Doug Anderson

On Thu, Oct 18, 2018 at 4:33 AM Vivek Gautam
<vivek.gautam@codeaurora.org> wrote:
>
> Hi Evan,
>
> On Wed, Oct 17, 2018 at 10:55 PM Evan Green <evgreen@chromium.org> wrote:
> >
> > This change adds the UFS controller and PHY to SDM845.
> >
> > Signed-off-by: Evan Green <evgreen@chromium.org>
> > Signed-off-by: Douglas Anderson <dianders@chromium.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sdm845.dtsi | 66 ++++++++++++++++++++++++++++++++++++
> >  1 file changed, 66 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index b72bdb0a31a5..20b2c258816a 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -808,6 +808,72 @@
> >                         };
> >                 };
> >
> > +               ufshc1: ufshc@1d84000 {
> > +                       compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
> > +                                    "jedec,ufs-2.0";
> > +                       reg = <0x1d84000 0x2500>;
> > +                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> > +                       phys = <&ufsphy1_lanes>;
> > +                       phy-names = "ufsphy";
> > +                       lanes-per-direction = <2>;
> > +                       power-domains = <&gcc UFS_PHY_GDSC>;
> > +
> > +                       clock-names =
> > +                               "core_clk",
> > +                               "bus_aggr_clk",
> > +                               "iface_clk",
> > +                               "core_clk_unipro",
> > +                               "ref_clk",
> > +                               "tx_lane0_sync_clk",
> > +                               "rx_lane0_sync_clk",
> > +                               "rx_lane1_sync_clk";
> > +                       clocks =
> > +                               <&gcc GCC_UFS_PHY_AXI_CLK>,
> > +                               <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> > +                               <&gcc GCC_UFS_PHY_AHB_CLK>,
> > +                               <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> > +                               <&rpmhcc RPMH_CXO_CLK>,
> > +                               <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> > +                               <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> > +                               <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> > +                       freq-table-hz =
> > +                               <50000000 200000000>,
> > +                               <0 0>,
> > +                               <0 0>,
> > +                               <37500000 150000000>,
> > +                               <0 0>,
> > +                               <0 0>,
> > +                               <0 0>,
> > +                               <0 0>;
> > +
> > +                       resets = <&gcc GCC_UFS_PHY_BCR>;
> > +                       reset-names = "rst";
> > +
> > +                       status = "disabled";
> > +               };
> > +
> > +               ufsphy1: ufsphy@1d87000 {
>
> nit: s/ufsphy@1d87000/phy@1d87000

Ok, will change.

>
> > +                       compatible = "qcom,sdm845-qmp-ufs-phy";
> > +                       reg = <0x1d87000 0x18c>;
> > +                       #clock-cells = <1>;
>
> why do we need this clock-cells? ufsphy i think is not providing any
> clocks. Is it?

Right. USB provides the pipe clock, but you're right, UFS doesn't
provide any clocks, so I'll remove.

> Rest looks good.
>
> Best regards
> Vivek
>
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +                       ranges;
> > +                       clock-names = "ref",
> > +                                     "ref_aux";
> > +                       clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
> > +                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> > +
> > +                       status = "disabled";
> > +
> > +                       ufsphy1_lanes: lanes@1d87400 {
> > +                               reg = <0x1d87400 0x108>,
> > +                                     <0x1d87600 0x1e0>,
> > +                                     <0x1d87c00 0x1dc>;

Doug, Stephen and I were looking more at the PHY driver and realized
it overreaches its registers here by adding 0x400 to get at the second
lane. We found this unappealing. Our current thinking is to add two
more reg regions here and fix up the binding, so that tx2 and rx2 are
properly specified. I'll try to come up with that patch today and
resend along with this.

-Evan

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2018-10-18 15:38 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-17 17:23 [PATCH 0/2] arm64: dts: qcom: sdm845: Add UFS DT nodes Evan Green
2018-10-17 17:23 ` [PATCH 1/2] arm64: dts: qcom: sdm845: add UFS controller Evan Green
2018-10-18 11:33   ` Vivek Gautam
2018-10-18 15:37     ` Evan Green
2018-10-17 17:23 ` [PATCH 2/2] arm64: dts: qcom: sdm845: Add UFS nodes for sdm845-mtp Evan Green
2018-10-18 11:34   ` Vivek Gautam

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