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From: Willy Tarreau <w@1wt.eu>
To: Richard Genoud <richard.genoud@gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	Gregory CLEMENT <gregory.clement@bootlin.com>,
	Yelena Krivosheev <yelena@marvell.com>,
	Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Nicolas Ferre <nicolas.ferre@microchip.com>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: CRC errors between mvneta and macb
Date: Fri, 19 Oct 2018 17:44:39 +0200	[thread overview]
Message-ID: <20181019154439.GC24045@1wt.eu> (raw)
In-Reply-To: <f6ccdfbd-7a67-ae14-5940-c7614cb143e9@sorico.fr>

On Fri, Oct 19, 2018 at 05:15:03PM +0200, Richard Genoud wrote:
> When there's a CRC error, the TXCLK has its polarity inverted...
> That's a clue !
> 
> But this TXCLK (25MHz) is not used on the g35-ek.
> Only the REFCLK/XT2 (50MHz) is used to synchronise the PHY and the macb.
> So I guess that the TXCLK has a role to play to generate TX+/TX-

Well, just a stupid idea, maybe when this signal is inverted, the TX+/TX-
are desynchronized by half a clock and are not always properly interpreted
on the other side ?

Willy

  reply	other threads:[~2018-10-19 15:44 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-19 15:15 Richard Genoud
2018-10-19 15:44 ` Willy Tarreau [this message]
2018-10-22  6:51   ` Richard Genoud
2018-10-22 15:15     ` Richard Genoud
2018-10-22 16:34       ` Willy Tarreau
2018-10-23  6:56         ` Richard Genoud
2018-10-22 18:19       ` Andrew Lunn
2018-10-23  6:58         ` Richard Genoud
2018-10-23 12:37         ` Richard Genoud

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