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From: Peter Zijlstra <peterz@infradead.org>
To: Guo Ren <ren_guo@c-sky.com>
Cc: akpm@linux-foundation.org, arnd@arndb.de,
	daniel.lezcano@linaro.org, davem@davemloft.net,
	gregkh@linuxfoundation.org, hch@infradead.org,
	marc.zyngier@arm.com, mark.rutland@arm.com, robh@kernel.org,
	tglx@linutronix.de, linux-kernel@vger.kernel.org,
	linux-arch@vger.kernel.org, devicetree@vger.kernel.org,
	robh+dt@kernel.org, c-sky_gcc_upstream@c-sky.com,
	Andrea Parri <andrea.parri@amarulasolutions.com>
Subject: Re: [PATCH V9 11/21] csky: Atomic operations
Date: Sun, 21 Oct 2018 22:55:08 +0200	[thread overview]
Message-ID: <20181021205508.GJ4931@worktop.programming.kicks-ass.net> (raw)
In-Reply-To: <efb6c9bb87f68c6f579ef497096086413effa5c2.1539655732.git.ren_guo@c-sky.com>

On Tue, Oct 16, 2018 at 10:58:30AM +0800, Guo Ren wrote:

> diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h
> new file mode 100644
> index 0000000..0474603
> --- /dev/null
> +++ b/arch/csky/include/asm/spinlock.h
> @@ -0,0 +1,274 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __ASM_CSKY_SPINLOCK_H
> +#define __ASM_CSKY_SPINLOCK_H
> +
> +#include <linux/spinlock_types.h>
> +#include <asm/barrier.h>
> +
> +#ifdef CONFIG_QUEUED_RWLOCKS
> +
> +/*
> + * Ticket-based spin-locking.
> + */
> +static inline void arch_spin_lock(arch_spinlock_t *lock)
> +{
> +	arch_spinlock_t lockval;
> +	u32 ticket_next = 1 << TICKET_NEXT;
> +	u32 *p = &lock->lock;
> +	u32 tmp;
> +
> +	asm volatile (
> +		"1:	ldex.w		%0, (%2) \n"
> +		"	mov		%1, %0	 \n"
> +		"	add		%0, %3	 \n"
> +		"	stex.w		%0, (%2) \n"
> +		"	bez		%0, 1b   \n"
> +		: "=&r" (tmp), "=&r" (lockval)
> +		: "r"(p), "r"(ticket_next)
> +		: "cc");
> +
> +	while (lockval.tickets.next != lockval.tickets.owner)
> +		lockval.tickets.owner = READ_ONCE(lock->tickets.owner);
> +
> +	smp_mb();
> +}
> +
> +static inline int arch_spin_trylock(arch_spinlock_t *lock)
> +{
> +	u32 tmp, contended, res;
> +	u32 ticket_next = 1 << TICKET_NEXT;
> +	u32 *p = &lock->lock;
> +
> +	do {
> +		asm volatile (
> +		"	ldex.w		%0, (%3)   \n"
> +		"	movi		%2, 1	   \n"
> +		"	rotli		%1, %0, 16 \n"
> +		"	cmpne		%1, %0     \n"
> +		"	bt		1f         \n"
> +		"	movi		%2, 0	   \n"
> +		"	add		%0, %0, %4 \n"
> +		"	stex.w		%0, (%3)   \n"
> +		"1:				   \n"
> +		: "=&r" (res), "=&r" (tmp), "=&r" (contended)
> +		: "r"(p), "r"(ticket_next)
> +		: "cc");
> +	} while (!res);
> +
> +	if (!contended)
> +		smp_mb();
> +
> +	return !contended;
> +}
> +
> +static inline void arch_spin_unlock(arch_spinlock_t *lock)
> +{
> +	smp_mb();
> +	lock->tickets.owner++;

	WRITE_ONCE(lock->tickets.owner, lock->tickets.owner + 1);

> +}
> +
> +static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
> +{
> +	return lock.tickets.owner == lock.tickets.next;
> +}
> +
> +static inline int arch_spin_is_locked(arch_spinlock_t *lock)
> +{
> +	return !arch_spin_value_unlocked(READ_ONCE(*lock));
> +}
> +
> +static inline int arch_spin_is_contended(arch_spinlock_t *lock)
> +{
> +	struct __raw_tickets tickets = READ_ONCE(lock->tickets);
> +
> +	return (tickets.next - tickets.owner) > 1;
> +}
> +#define arch_spin_is_contended	arch_spin_is_contended
> +
> +#include <asm/qrwlock.h>
> +
> +/* See include/linux/spinlock.h */
> +#define smp_mb__after_spinlock()	smp_mb()
> +
> +#else /* CONFIG_QUEUED_RWLOCKS */
> +
> +/*
> + * Test-and-set spin-locking.
> + */

I'm still not entirely sure why you want to have two spinlock
implementations; to me that is just extra maintenance overhead.

> +static inline void arch_spin_lock(arch_spinlock_t *lock)
> +{
> +	u32 *p = &lock->lock;
> +	u32 tmp;
> +
> +	asm volatile (
> +		"1:	ldex.w		%0, (%1) \n"
> +		"	bnez		%0, 1b   \n"
> +		"	movi		%0, 1    \n"
> +		"	stex.w		%0, (%1) \n"
> +		"	bez		%0, 1b   \n"
> +		: "=&r" (tmp)
> +		: "r"(p)
> +		: "cc");
> +	smp_mb();
> +}
> +
> +static inline void arch_spin_unlock(arch_spinlock_t *lock)
> +{
> +	u32 *p = &lock->lock;
> +	u32 tmp;
> +
> +	smp_mb();
> +	asm volatile (
> +		"	movi		%0, 0    \n"
> +		"	stw		%0, (%1) \n"
> +		: "=&r" (tmp)
> +		: "r"(p)
> +		: "cc");

	WRITE_ONCE(lock->lock, 0);
?

> +}
> +
> +static inline int arch_spin_trylock(arch_spinlock_t *lock)
> +{
> +	u32 *p = &lock->lock;
> +	u32 tmp;
> +
> +	asm volatile (
> +		"1:	ldex.w		%0, (%1) \n"
> +		"	bnez		%0, 2f   \n"
> +		"	movi		%0, 1    \n"
> +		"	stex.w		%0, (%1) \n"
> +		"	bez		%0, 1b   \n"
> +		"	movi		%0, 0    \n"
> +		"2:				 \n"
> +		: "=&r" (tmp)
> +		: "r"(p)
> +		: "cc");
> +
> +	if (!tmp)
> +		smp_mb();
> +
> +	return !tmp;
> +}
> +
> +#define arch_spin_is_locked(x)	(READ_ONCE((x)->lock) != 0)
> +
> +/*
> + * read lock/unlock/trylock
> + */

Idem, why do you want a second rwlock_t implementation?

> +/*
> + * write lock/unlock/trylock
> + */
> +static inline void arch_write_lock(arch_rwlock_t *lock)
> +{
> +	u32 *p = &lock->lock;
> +	u32 tmp;
> +
> +	asm volatile (
> +		"1:	ldex.w		%0, (%1) \n"
> +		"	bnez		%0, 1b   \n"
> +		"	subi		%0, 1    \n"
> +		"	stex.w		%0, (%1) \n"
> +		"	bez		%0, 1b   \n"
> +		: "=&r" (tmp)
> +		: "r"(p)
> +		: "cc");
> +	smp_mb();
> +}
> +
> +static inline void arch_write_unlock(arch_rwlock_t *lock)
> +{
> +	u32 *p = &lock->lock;
> +	u32 tmp;
> +
> +	smp_mb();
> +	asm volatile (
> +		"1:	ldex.w		%0, (%1) \n"
> +		"	movi		%0, 0    \n"
> +		"	stex.w		%0, (%1) \n"
> +		"	bez		%0, 1b   \n"
> +		: "=&r" (tmp)
> +		: "r"(p)
> +		: "cc");

Isn't that:

	WRITE_ONCE(lock->lock, 0);

> +}
> +
> +static inline int arch_write_trylock(arch_rwlock_t *lock)
> +{
> +	u32 *p = &lock->lock;
> +	u32 tmp;
> +
> +	asm volatile (
> +		"1:	ldex.w		%0, (%1) \n"
> +		"	bnez		%0, 2f   \n"
> +		"	subi		%0, 1    \n"
> +		"	stex.w		%0, (%1) \n"
> +		"	bez		%0, 1b   \n"
> +		"	movi		%0, 0    \n"
> +		"2:				 \n"
> +		: "=&r" (tmp)
> +		: "r"(p)
> +		: "cc");
> +
> +	if (!tmp)
> +		smp_mb();
> +
> +	return !tmp;
> +}

> diff --git a/arch/csky/kernel/atomic.S b/arch/csky/kernel/atomic.S
> new file mode 100644
> index 0000000..d2357c8
> --- /dev/null
> +++ b/arch/csky/kernel/atomic.S
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
> +
> +#include <linux/linkage.h>
> +#include <abi/entry.h>
> +
> +.text
> +
> +/*
> + * int csky_cmpxchg(int oldval, int newval, int *ptr)
> + *
> + * If *ptr != oldval && return 1,
> + * else *ptr = newval return 0.
> + */
> +#ifdef CONFIG_CPU_HAS_LDSTEX
> +ENTRY(csky_cmpxchg)
> +	USPTOKSP
> +	mfcr	a3, epc
> +	INCTRAP	a3
> +
> +	subi    sp, 8
> +	stw     a3, (sp, 0)
> +	mfcr    a3, epsr
> +	stw     a3, (sp, 4)
> +
> +	psrset	ee
> +1:
> +	ldex	a3, (a2)
> +	cmpne	a0, a3
> +	bt16	2f
> +	mov	a3, a1
> +	stex	a3, (a2)
> +	bez	a3, 1b
> +2:
> +	sync.is
> +	mvc	a0
> +	ldw	a3, (sp, 0)
> +	mtcr	a3, epc
> +	ldw     a3, (sp, 4)
> +	mtcr	a3, epsr
> +	addi	sp, 8
> +	KSPTOUSP
> +	rte
> +END(csky_cmpxchg)

I don't understand why you have this; if the CPU has ll/sc, why do you
need syscall support?

In any case, nothing terminally broken; so I suppose that's good enough
for starters. I just really don't understand some decisions (like having
two lock implementations and having that cmpxchg syscall when you have
hardware ll/sc).

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>

  parent reply	other threads:[~2018-10-21 20:55 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-16  2:58 [PATCH V9 00/21] C-SKY(csky) Linux Kernel Port Guo Ren
2018-10-16  2:58 ` [PATCH V9 01/21] csky: Build infrastructure Guo Ren
2018-10-23  0:08   ` Guo Ren
2018-10-24 22:53     ` Arnd Bergmann
2018-10-25 17:04       ` Guo Ren
2018-10-16  2:58 ` [PATCH V9 02/21] csky: defconfig Guo Ren
2018-10-17 14:56   ` Arnd Bergmann
2018-10-16  2:58 ` [PATCH V9 03/21] csky: Kernel booting Guo Ren
2018-10-17 14:58   ` Arnd Bergmann
2018-10-16  2:58 ` [PATCH V9 04/21] csky: Exception handling and mm-fault Guo Ren
2018-10-17 14:59   ` Arnd Bergmann
2018-10-16  2:58 ` [PATCH V9 05/21] csky: System Call Guo Ren
2018-10-17 15:02   ` Arnd Bergmann
2018-10-18  2:02     ` Guo Ren
2018-10-16  2:58 ` [PATCH V9 06/21] csky: Cache and TLB routines Guo Ren
2018-10-17 15:08   ` Arnd Bergmann
2018-10-16  2:58 ` [PATCH V9 07/21] csky: MMU and page table management Guo Ren
2018-10-17 15:06   ` Arnd Bergmann
2018-10-18  2:05     ` Guo Ren
2018-10-16  2:58 ` [PATCH V9 08/21] csky: Process management and Signal Guo Ren
2018-10-17 15:11   ` Arnd Bergmann
2018-10-18  2:37     ` Guo Ren
2018-10-16  2:58 ` [PATCH V9 09/21] csky: VDSO and rt_sigreturn Guo Ren
2018-10-17 15:13   ` Arnd Bergmann
2018-10-16  2:58 ` [PATCH V9 10/21] csky: IRQ handling Guo Ren
2018-10-17 15:14   ` Arnd Bergmann
2018-10-18  2:39     ` Guo Ren
2018-10-16  2:58 ` [PATCH V9 11/21] csky: Atomic operations Guo Ren
2018-10-17 15:17   ` Arnd Bergmann
2018-10-18  2:40     ` Guo Ren
2018-10-21 20:55   ` Peter Zijlstra [this message]
2018-10-22  1:52     ` Guo Ren
2018-10-16  2:58 ` [PATCH V9 12/21] csky: ELF and module probe Guo Ren
2018-10-17 15:18   ` Arnd Bergmann
2018-10-18  2:49     ` Guo Ren
2018-10-18  8:31       ` Arnd Bergmann
2018-10-16  2:58 ` [PATCH V9 13/21] csky: Library functions Guo Ren
2018-10-17 15:24   ` Arnd Bergmann
2018-10-18  3:10     ` Guo Ren
2018-10-16  2:58 ` [PATCH V9 14/21] csky: User access Guo Ren
2018-10-17 15:37   ` Arnd Bergmann
2018-10-16  2:58 ` [PATCH V9 15/21] csky: Debug and Ptrace GDB Guo Ren
2018-10-17 15:46   ` Arnd Bergmann
2018-10-18  3:17     ` Guo Ren
2018-10-16  2:58 ` [PATCH V9 16/21] csky: SMP support Guo Ren
2018-10-17 15:47   ` Arnd Bergmann
2018-10-16  2:58 ` [PATCH V9 17/21] csky: Misc headers Guo Ren
2018-10-17 15:49   ` Arnd Bergmann
2018-10-16  2:58 ` [PATCH V9 18/21] dt-bindings: csky CPU Bindings Guo Ren
2018-10-17 15:50   ` Arnd Bergmann
2018-10-18  3:21     ` Guo Ren
2018-10-18  3:45       ` Guo Ren
2018-10-18 14:31   ` Rob Herring
2018-10-19  2:19     ` Guo Ren
2018-10-16  2:58 ` [PATCH V9 19/21] dt-bindings: Add vendor prefix for csky Guo Ren
2018-10-16  2:58 ` [PATCH V9 20/21] MAINTAINERS: Add csky Guo Ren
2018-10-17 15:51   ` Arnd Bergmann
2018-10-16  5:48 ` [PATCH V9 21/21] csky: support dword access for get_user_size() Guo Ren
2018-10-17 15:44   ` Arnd Bergmann
2018-10-18  3:41     ` Guo Ren
2018-10-18  8:34       ` Arnd Bergmann
2018-10-18  8:57         ` Guo Ren
2018-10-24  7:17           ` Arnd Bergmann
2018-10-25 17:08             ` Guo Ren
2018-10-17 15:58 ` [PATCH V9 00/21] C-SKY(csky) Linux Kernel Port Arnd Bergmann
2018-10-18  4:10   ` Guo Ren
2018-10-18  8:36     ` Arnd Bergmann
2018-10-18  9:03       ` Guo Ren

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