From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CE91C46475 for ; Tue, 23 Oct 2018 18:43:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5AC0E20824 for ; Tue, 23 Oct 2018 18:43:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5AC0E20824 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728970AbeJXDII (ORCPT ); Tue, 23 Oct 2018 23:08:08 -0400 Received: from mga05.intel.com ([192.55.52.43]:55096 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728934AbeJXDIE (ORCPT ); Tue, 23 Oct 2018 23:08:04 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Oct 2018 11:43:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,417,1534834800"; d="scan'208";a="243726606" Received: from chang-linux-2.sc.intel.com ([10.3.52.139]) by orsmga004.jf.intel.com with ESMTP; 23 Oct 2018 11:43:30 -0700 From: "Chang S. Bae" To: Ingo Molnar , Thomas Gleixner , Andy Lutomirski , "H . Peter Anvin" Cc: Andi Kleen , Dave Hansen , Markus T Metzger , Ravi Shankar , "Chang S . Bae" , LKML Subject: [v3 12/12] x86/fsgsbase/64: Add documentation for FSGSBASE Date: Tue, 23 Oct 2018 11:42:34 -0700 Message-Id: <20181023184234.14025-13-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181023184234.14025-1-chang.seok.bae@intel.com> References: <20181023184234.14025-1-chang.seok.bae@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen v2: Minor updates to documentation requested in review. v3: Update for new gcc and various improvements. [ chang: Fix some typo. Fix the example code. ] Signed-off-by: Andi Kleen Signed-off-by: Chang S. Bae Cc: Andy Lutomirski Cc: H. Peter Anvin Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Dave Hansen --- Documentation/x86/fsgs.txt | 104 +++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/x86/fsgs.txt diff --git a/Documentation/x86/fsgs.txt b/Documentation/x86/fsgs.txt new file mode 100644 index 000000000000..7a973a5c1767 --- /dev/null +++ b/Documentation/x86/fsgs.txt @@ -0,0 +1,104 @@ + +Using FS and GS prefixes on 64bit x86 linux + +The x86 architecture supports segment prefixes per instruction to add an +offset to an address. On 64bit x86, these are mostly nops, except for FS +and GS. + +This offers an efficient way to reference a global pointer. + +The compiler has to generate special code to use these base registers, +or they can be accessed with inline assembler. + + mov %gs:offset,%reg + mov %fs:offset,%reg + +On 64bit code, FS is used to address the thread local segment (TLS), declared using +__thread. The compiler then automatically generates the correct prefixes and +relocations to access these values. + +FS is normally managed by the runtime code or the threading library +Overwriting it can break a lot of things (including syscalls and gdb), +but it can make sense to save/restore it for threading purposes. + +GS is freely available, but may need special (compiler or inline assembler) +code to use. + +Traditionally 64bit FS and GS could be set by the arch_prctl system call + + arch_prctl(ARCH_SET_GS, value) + arch_prctl(ARCH_SET_FS, value) + +[There was also an older method using modify_ldt(), inherited from 32bit, +but this is not discussed here.] + +However using a syscall is problematic for user space threading libraries +that want to context switch in user space. The whole point of them +is avoiding the overhead of a syscall. It's also cleaner for compilers +wanting to use the extra register to use instructions to write +it, or read it directly to compute addresses and offsets. + +Newer Intel CPUs (Ivy Bridge and later) added new instructions to directly +access these registers quickly from user context + + RDFSBASE %reg read the FS base (or _readfsbase_u64) + RDGSBASE %reg read the GS base (or _readgsbase_u64) + + WRFSBASE %reg write the FS base (or _writefsbase_u64) + WRGSBASE %reg write the GS base (or _writegsbase_u64) + +If you use the intrinsics include and set the -mfsgsbase option. + +The instructions are supported by the CPU when the "fsgsbase" string is shown in +/proc/cpuinfo (or directly retrieved through the CPUID instruction, +7:0 (ebx), word 9, bit 0) + +The instructions are only available to 64bit binaries. + +In addition the kernel needs to explicitly enable these instructions, as it +may otherwise not correctly context switch the state. Newer Linux +kernels enable this. When the kernel did not enable the instruction +they will fault with an #UD exception. + +An FSGSBASE enabled kernel can be detected by checking the AT_HWCAP2 +bitmask in the aux vector. When the HWCAP2_FSGSBASE bit is set the +kernel supports FSGSBASE. + + #include + #include + + /* Will be eventually in asm/hwcap.h */ + #define HWCAP2_FSGSBASE (1 << 1) + + unsigned val = getauxval(AT_HWCAP2); + if (val & HWCAP2_FSGSBASE) { + asm("wrgsbase %0" :: "r" (ptr)); + } + +No extra CPUID check needed as the kernel will not set this bit if the CPU +does not support it. + +gcc 6 will have special support to directly access data relative +to fs/gs using the __seg_fs and __seg_gs address space pointer +modifiers. + +#ifndef __SEG_GS +#error "Need gcc 6 or later" +#endif + +struct gsdata { + int a; + int b; +} gsdata = { 1, 2 }; + +int __seg_gs *valp = 0; /* offset relative to GS */ + + /* Check if kernel supports FSGSBASE as above */ + + /* Set up new GS */ + asm("wrgsbase %0" :: "r" (&gsdata)); + + /* Now the global pointer can be used normally */ + printf("gsdata.a = %d\n", *valp); + +Andi Kleen -- 2.19.1