From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F74FECDE46 for ; Wed, 24 Oct 2018 17:28:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E466B206B5 for ; Wed, 24 Oct 2018 17:28:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="mLpwzYA1" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E466B206B5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727330AbeJYB5N (ORCPT ); Wed, 24 Oct 2018 21:57:13 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:35938 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726852AbeJYB5M (ORCPT ); Wed, 24 Oct 2018 21:57:12 -0400 Received: by mail-pg1-f196.google.com with SMTP id l6-v6so2651984pgp.3 for ; Wed, 24 Oct 2018 10:28:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k/uUozxxicG3WkgvqwK4qgG8AlCRKL8xFjmeXsyURb0=; b=mLpwzYA14uIfqrIynhahuxN7OKo1exvJzGTSv1h0Yy/vq9efkWF++TTpfSlKNVd5ig E7aCDLMDssKQI9FTo0PVyfqXolGm5+9Rq6h5QqrQho4Yu9usry51knggQOnPS2Xv7JUj tJjO7v+xs8mbu8EAYAErom9D1h667hAmgT8sY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k/uUozxxicG3WkgvqwK4qgG8AlCRKL8xFjmeXsyURb0=; b=o1gEdWwKVDZAUKrVM2iiT6vGi6MpTk/8Q5n3t3IpIg3YbVovWEDTIVPRiHqMxtsyo6 khdgTZMOTIeVCowds2axbMVBEWAgC+lBSW9AjIqpCQ04FMuvOmmpj3aJAsO7AjhqwqkS ua4WTFNeIXvLZbQyjQtPDOmVDUZ4i+Kcux+WUd4S4D3RLSJ6o8kWghc0nSsX91xA4YAd EwgwHZHeJAQsYluAFe/3ENpxrq/alJsTVJTLIHq2QY93PgmHpBlQUWpLDmpSur5d3S4+ +Cfc01qawukqNa1IpuxKmA2zYZrTZoBd4keMLVCXxv9acnIkWPrlm1WFpbQV7zy2sgw+ HwSQ== X-Gm-Message-State: AGRZ1gKudx1DxV/+mQs/6VIlu8hMochhEXVPIsfr4wPVPFJVVRYH+t3F jz+Mdl0VUEwCp/L1paT/tEM5WQ== X-Google-Smtp-Source: AJdET5eyl3+2d4LZXahMwE2HPPpa8C8VmmIbcHxwnES5U7POZN30esBT1dCDg+nbAVczWQhe+IkGXg== X-Received: by 2002:a62:583:: with SMTP id 125-v6mr3488114pff.186.1540402098107; Wed, 24 Oct 2018 10:28:18 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:e418:c825:76cf:5f64]) by smtp.gmail.com with ESMTPSA id v185-v6sm5674265pfv.48.2018.10.24.10.28.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Oct 2018 10:28:17 -0700 (PDT) From: Evan Green To: Rob Herring , Andy Gross , Kishon Vijay Abraham I Cc: Douglas Anderson , Stephen Boyd , Evan Green , Can Guo , linux-kernel@vger.kernel.org, Vivek Gautam , Manu Gautam Subject: [PATCH v4 2/5] phy: qcom-qmp: Utilize fully-specified DT registers Date: Wed, 24 Oct 2018 10:27:32 -0700 Message-Id: <20181024172735.154304-3-evgreen@chromium.org> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20181024172735.154304-1-evgreen@chromium.org> References: <20181024172735.154304-1-evgreen@chromium.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Utilize the newly fixed up DT bindings to get the tx2 and rx2 register regions for the second lane of dual-lane PHYs. Before this change, the driver was simply using lane one's register region and adding 0x400, which reached well beyond the DT-specified register allocation. This would have been a crash were it not for the page size on ARM64. Fix the driver not to rely on the magic of virtual memory by using the newly specified DT register regions for tx2 and rx2. In order to support existing device trees, this change also contains a fallback mode for when those new register regions don't exist, which reverts to the original behavior of overreaching and prints a complaint. Signed-off-by: Evan Green Reviewed-by: Douglas Anderson --- As Doug mentioned, this should land before the dts patches land, otherwise the old driver code will use the tx2 register region as pcs_misc. Changes in v4: None Changes in v3: None Changes in v2: None drivers/phy/qualcomm/phy-qcom-qmp.c | 51 +++++++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index a83332411026..61d5fe115d9d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -72,6 +72,9 @@ #define MAX_PROP_NAME 32 +/* Define the assumed distance between lanes for underspecified device trees. */ +#define QMP_PHY_LEGACY_LANE_STRIDE 0x400 + struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; @@ -733,9 +736,6 @@ struct qmp_phy_cfg { bool has_phy_dp_com_ctrl; /* true, if PHY has secondary tx/rx lanes to be configured */ bool is_dual_lane_phy; - /* Register offset of secondary tx/rx lanes for USB DP combo PHY */ - unsigned int tx_b_lane_offset; - unsigned int rx_b_lane_offset; /* true, if PCS block has no separate SW_RESET register */ bool no_pcs_sw_reset; @@ -748,6 +748,8 @@ struct qmp_phy_cfg { * @tx: iomapped memory space for lane's tx * @rx: iomapped memory space for lane's rx * @pcs: iomapped memory space for lane's pcs + * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) + * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc * @pipe_clk: pipe lock * @index: lane index @@ -759,6 +761,8 @@ struct qmp_phy { void __iomem *tx; void __iomem *rx; void __iomem *pcs; + void __iomem *tx2; + void __iomem *rx2; void __iomem *pcs_misc; struct clk *pipe_clk; unsigned int index; @@ -975,8 +979,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { .has_phy_dp_com_ctrl = true, .is_dual_lane_phy = true, - .tx_b_lane_offset = 0x400, - .rx_b_lane_offset = 0x400, }; static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { @@ -1031,9 +1033,6 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .mask_pcs_ready = PCS_READY, .is_dual_lane_phy = true, - .tx_b_lane_offset = 0x400, - .rx_b_lane_offset = 0x400, - .no_pcs_sw_reset = true, }; @@ -1238,12 +1237,12 @@ static int qcom_qmp_phy_init(struct phy *phy) qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num); /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) - qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs, + qcom_qmp_phy_configure(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num); qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num); if (cfg->is_dual_lane_phy) - qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs, + qcom_qmp_phy_configure(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num); qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); @@ -1614,8 +1613,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) /* * Get memory resources for each phy lane: - * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; and - * pcs_misc (optional) -> 3. + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. + * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 + * For single lane PHYs: pcs_misc (optional) -> 3. */ qphy->tx = of_iomap(np, 0); if (!qphy->tx) @@ -1629,7 +1629,32 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) if (!qphy->pcs) return -ENOMEM; - qphy->pcs_misc = of_iomap(np, 3); + /* + * If this is a dual-lane PHY, then there should be registers for the + * second lane. Some old device trees did not specify this, so fall + * back to old legacy behavior of assuming they can be reached at an + * offset from the first lane. + */ + if (qmp->cfg->is_dual_lane_phy) { + qphy->tx2 = of_iomap(np, 3); + qphy->rx2 = of_iomap(np, 4); + if (!qphy->tx2 || !qphy->rx2) { + dev_warn(dev, + "Underspecified device tree, falling back to legacy register regions\n"); + + /* In the old version, pcs_misc is at index 3. */ + qphy->pcs_misc = qphy->tx2; + qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; + qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; + + } else { + qphy->pcs_misc = of_iomap(np, 5); + } + + } else { + qphy->pcs_misc = of_iomap(np, 3); + } + if (!qphy->pcs_misc) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); -- 2.16.4