[PATCH v2 00/15] drm/sun4i: Allwinner A64 MIPI-DSI support

[PATCH v2 00/15] drm/sun4i: Allwinner A64 MIPI-DSI support

[Jagan Teki]

This series add MIPI-DSI support on Allwinner A64. The same A31 controller
is reused and tweaked for A64 since the register space for both SoC's look same.

A64 PLL_MIPI look difficult to set the proper dclk nkm dividers with
existing clock driver. But Setting the dclk on panel set to 55MHz
(BSP says 30MHz) and min PLL_MIPI rate used as 30MHz. This logic make proper
rounded rate by sun4i_dclk_round_rate which eventually working.

24 / 4 * 55000 = 330000 (24 bit format with 4 lane and 55MHz clock)

[    2.360344] sun4i-drm display-engine: bound 1100000.mixer (ops sun8i_mixer_ops)
[    2.367899] sun4i_dclk_recalc_rate: val = 1, rate = 594000000
[    2.373827] sun4i-drm display-engine: No panel or bridge found... RGB output disabled
[    2.381666] sun4i-drm display-engine: bound 1c0c000.lcd-controller (ops sun4i_tcon_ops)
[    2.389691] sun4i-drm display-engine: bound 1ca0000.dsi (ops sun6i_dsi_ops)
[    2.396653] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    2.403266] [drm] No driver support for vblank timestamp query.
[    2.411632] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[    2.411693] ideal = 220000000, rounded = 0
[    2.411698] ideal = 275000000, rounded = 0
[    2.411716] ideal = 330000000, rounded = 330000000
[    2.411720] sun4i_dclk_round_rate: div = 6 rate = 55000000
[    2.411725] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[    2.411729] ideal = 220000000, rounded = 0
[    2.411732] ideal = 275000000, rounded = 0
[    2.411750] ideal = 330000000, rounded = 330000000
[    2.411753] sun4i_dclk_round_rate: div = 6 rate = 55000000
[    2.411790] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
[    2.411794] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
[    2.411817] NKM: rate = 330000000
[    2.411819] NKM: parent_rate = 297000000
[    2.411821] NKM: _nkm.n = 5
[    2.411823] NKM: _nkm.k = 2
[    2.411825] NKM: _nkm.m = 9
[    2.412175] sun4i_dclk_set_rate div 6
[    2.412182] sun4i_dclk_recalc_rate: val = 6, rate = 55000000

But the same logic seems "not working" on 2-lane panel where dclk on panel
set to 27.5MHz(BSP says 29MHz)

24/2 * 27500 = 330000 (24 bit format with 2 lane and 27.5 MHz clock)

[    1.877154] sun4i-drm display-engine: bound 1100000.mixer (ops sun8i_mixer_ops)
[    1.884695] sun4i_dclk_recalc_rate: val = 1, rate = 594000000
[    1.890659] sun4i-drm display-engine: No panel or bridge found... RGB output disabled
[    1.898515] sun4i-drm display-engine: bound 1c0c000.lcd-controller (ops sun4i_tcon_ops)
[    1.906563] sun4i-drm display-engine: bound 1ca0000.dsi (ops sun6i_dsi_ops)
[    1.913542] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    1.920173] [drm] No driver support for vblank timestamp query.
[    1.929330] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 27500000
[    1.929388] ideal = 110000000, rounded = 0
[    1.929392] ideal = 137500000, rounded = 0
[    1.929396] ideal = 165000000, rounded = 0
[    1.929400] ideal = 192500000, rounded = 0
[    1.929403] ideal = 220000000, rounded = 0
[    1.929407] ideal = 247500000, rounded = 0
[    1.929410] ideal = 275000000, rounded = 0
[    1.929429] ideal = 302500000, rounded = 297000000
[    1.929446] ideal = 330000000, rounded = 330000000
[    1.929449] sun4i_dclk_round_rate: div = 12 rate = 27500000
[    1.929454] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 27500000
[    1.929458] ideal = 110000000, rounded = 0
[    1.929462] ideal = 137500000, rounded = 0
[    1.929465] ideal = 165000000, rounded = 0
[    1.929469] ideal = 192500000, rounded = 0
[    1.929472] ideal = 220000000, rounded = 0
[    1.929476] ideal = 247500000, rounded = 0
[    1.929479] ideal = 275000000, rounded = 0
[    1.929496] ideal = 302500000, rounded = 297000000
[    1.929536] ideal = 330000000, rounded = 330000000
[    1.929539] sun4i_dclk_round_rate: div = 12 rate = 27500000
[    1.929576] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
[    1.929580] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
[    1.929613] NKM: rate = 330000000
[    1.929616] NKM: parent_rate = 297000000
[    1.929619] NKM: _nkm.n = 5
[    1.929620] NKM: _nkm.k = 2
[    1.929622] NKM: _nkm.m = 9
[    1.929966] sun4i_dclk_set_rate div 12
[    1.929974] sun4i_dclk_recalc_rate: val = 12, rate = 27500000
[    1.957513] random: fast init done
[    1.967893] mmc0: new high speed SDIO card at address 0001
[    1.971835] mmc1: new DDR MMC card at address 0001
[    1.973250] mmcblk1: mmc1:0001 8GND3R 7.28 GiB
[    1.974391] mmcblk1boot0: mmc1:0001 8GND3R partition 1 4.00 MiB
[    1.975528] mmcblk1boot1: mmc1:0001 8GND3R partition 2 4.00 MiB
[    1.982660]  mmcblk1: p1 p2 p3 p4 p5 p6
[    3.221053] ------------[ cut here ]------------
[    3.221059] [CRTC:36:crtc-0] vblank wait timed out
[    3.221136] WARNING: CPU: 2 PID: 42 at drivers/gpu/drm/drm_atomic_helper.c:1387 drm_atomic_helper_
wait_for_vblanks.part.9+0x294/0x2a0
[    3.221139] Modules linked in:
[    3.221151] CPU: 2 PID: 42 Comm: kworker/2:1 Not tainted 4.19.0-rc8-next-20181016-00024-g11217d38f
d10-dirty #5
[    3.221154] Hardware name: Amarula A64-Relic (DT)
[    3.221166] Workqueue: events deferred_probe_work_func
[    3.221173] pstate: 60000005 (nZCv daif -PAN -UAO)
[    3.221179] pc : drm_atomic_helper_wait_for_vblanks.part.9+0x294/0x2a0
[    3.221185] lr : drm_atomic_helper_wait_for_vblanks.part.9+0x294/0x2a0
[    3.221187] sp : ffff0000095fb3e0
[    3.221190] x29: ffff0000095fb3e0 x28: 0000000000000001
[    3.221196] x27: 0000000000000000 x26: 0000000000000000
[    3.221202] x25: ffff80003c057000 x24: ffff80003bdbb000
[    3.221207] x23: 0000000000000001 x22: 0000000000000030
[    3.221213] x21: 0000000000000001 x20: ffff80003bdbc018
[    3.221218] x19: 0000000000000000 x18: ffffffffffffffff
[    3.221224] x17: 0000000000000000 x16: 0000000000000000
[    3.221229] x15: ffff0000091d96c8 x14: 00000000fffffff0
[    3.221235] x13: ffff000009340ba0 x12: ffff0000091f1348
[    3.221240] x11: ffff0000091f1000 x10: ffff000009340000
[    3.221246] x9 : 0000000000000000 x8 : 0000000000000000
[    3.221251] x7 : 0000000000000000 x6 : 000000000dc21395
[    3.221256] x5 : 0000000000000000 x4 : 0000000000000000
[    3.221262] x3 : ffffffffffffffff x2 : ffff0000091f1378
[    3.221267] x1 : de241ee6737e7400 x0 : 0000000000000000
[    3.221273] Call trace:
[    3.221279]  drm_atomic_helper_wait_for_vblanks.part.9+0x294/0x2a0
[    3.221285]  drm_atomic_helper_commit_tail_rpm+0x60/0x78
[    3.221289]  commit_tail+0x44/0x78
[    3.221294]  drm_atomic_helper_commit+0xcc/0x148
[    3.221301]  drm_atomic_commit+0x48/0x58
[    3.221309]  restore_fbdev_mode_atomic+0x17c/0x1e8
[    3.221316]  restore_fbdev_mode+0x50/0x190
[    3.221322]  drm_fb_helper_restore_fbdev_mode_unlocked+0x70/0xc8
[    3.221328]  drm_fb_helper_set_par+0x2c/0x60
[    3.221335]  fbcon_init+0x4d8/0x528
[    3.221341]  visual_init+0xb0/0x108
[    3.221346]  do_bind_con_driver+0x1d0/0x3b0
[    3.221351]  do_take_over_console+0x148/0x1d8
[    3.221355]  do_fbcon_takeover+0x6c/0xf0
[    3.221361]  fbcon_event_notify+0x9a4/0x9d0
[    3.221370]  notifier_call_chain+0x50/0x90
[    3.221376]  __blocking_notifier_call_chain+0x4c/0x90
[    3.221382]  blocking_notifier_call_chain+0x14/0x20
[    3.221390]  fb_notifier_call_chain+0x1c/0x28
[    3.221396]  register_framebuffer+0x1ec/0x320
[    3.221402]  __drm_fb_helper_initial_config_and_unlock+0x22c/0x3b0
[    3.221408]  drm_fb_helper_fbdev_setup+0xd4/0x1f8
[    3.221414]  drm_fbdev_cma_init+0x9c/0xe8
[    3.221420]  drm_fb_cma_fbdev_init+0xc/0x20
[    3.221426]  sun4i_framebuffer_init+0x48/0x58
[    3.221431]  sun4i_drv_bind+0x14c/0x1a0
[    3.221436]  try_to_bring_up_master+0x144/0x1a8
[    3.221440]  component_add+0x98/0x160
[    3.221447]  sun8i_mixer_probe+0x18/0x20
[    3.221453]  platform_drv_probe+0x50/0xa8
[    3.221458]  really_probe+0x1e4/0x2a8
[    3.221464]  driver_probe_device+0x58/0x100
[    3.221470]  __device_attach_driver+0x9c/0xf8
[    3.221475]  bus_for_each_drv+0x70/0xc8
[    3.221480]  __device_attach+0xdc/0x138
[    3.221486]  device_initial_probe+0x10/0x18
[    3.221492]  bus_probe_device+0x94/0xa0
[    3.221497]  deferred_probe_work_func+0x6c/0xa0
[    3.221505]  process_one_work+0x1c8/0x318
[    3.221511]  worker_thread+0x234/0x428
[    3.221516]  kthread+0xf8/0x128
[    3.221523]  ret_from_fork+0x10/0x18
[    3.221527] ---[ end trace af12203776f67ca9 ]---
[   13.277055] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [CRTC:36:crtc-0] flip_done timed
 out
[   23.517053] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [CONNECTOR:38:DSI-1] flip_done t
imed out
[   33.757052] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [PLANE:30:plane-1] flip_done tim
ed out
[   33.813049] ------------[ cut here ]------------
[   33.813053] [CRTC:36:crtc-0] vblank wait timed out

Any suggestions,
Jagan.

Jagan Teki (15):
  clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
  clk: sunxi-ng: Add check for minimal rate to NKM PLLs
  clk: sunxi-ng: Add check for maximum rate to NKM PLLs
  drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support
  dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI
  drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param
    transfer
  drm/sun4i: sun6i_mipi_dsi: Fix VBP size calculation
  drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits
  drm/sun4i: sun6i_mipi_dsi: Refactor vertical video start delay
  dt-bindings: panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB
    bridge
  drm/panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge
  clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI
  dt-bindings: sun6i-dsi: Add compatible for A64 DPHY
  arm64: dts: allwinner: a64: Add DSI pipeline
  arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel

 .../panel/bananapi,s070wv20-ct16-icn6211.txt  |  21 ++
 .../bindings/display/sunxi/sun6i-dsi.txt      |   3 +-
 .../dts/allwinner/sun50i-a64-bananapi-m64.dts |  42 +++
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi |  45 +++
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c         |   4 +-
 drivers/clk/sunxi-ng/ccu_nkm.c                |  14 +
 drivers/clk/sunxi-ng/ccu_nkm.h                |   2 +
 drivers/gpu/drm/panel/Kconfig                 |   9 +
 drivers/gpu/drm/panel/Makefile                |   1 +
 .../panel/panel-bananapi-s070wv20-icn6211.c   | 336 ++++++++++++++++++
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c        |  68 +++-
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h        |   5 +
 12 files changed, 532 insertions(+), 18 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16-icn6211.txt
 create mode 100644 drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c

-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 01/15] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY

[Jagan Teki]

DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- none

 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index f7d297368eb2..019d67bf97c4 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -581,7 +581,7 @@ static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
 static const u8 dsi_dphy_table[] = { 0, 2, };
 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
 				       dsi_dphy_parents, dsi_dphy_table,
-				       0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT);
+				       0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
 			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 02/15] clk: sunxi-ng: Add check for minimal rate to NKM PLLs

[Jagan Teki]

Some NKM PLLs doesn't work well when their output clock rate is set below
certain rate.

So, add support for minimal rate for relevant PLLs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- new patch

 drivers/clk/sunxi-ng/ccu_nkm.c | 7 +++++++
 drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 841840e35e61..d17539dc88dd 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -125,6 +125,13 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
 	if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
 		rate *= nkm->fixed_post_div;
 
+	if (rate < nkm->min_rate) {
+		rate = nkm->min_rate;
+		if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+			rate /= nkm->fixed_post_div;
+		return rate;
+	}
+
 	ccu_nkm_find_best(*parent_rate, rate, &_nkm);
 
 	rate = *parent_rate * _nkm.n * _nkm.k / _nkm.m;
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
index cc6efb70a102..ff5bd00f429f 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.h
+++ b/drivers/clk/sunxi-ng/ccu_nkm.h
@@ -35,6 +35,7 @@ struct ccu_nkm {
 	struct ccu_mux_internal	mux;
 
 	unsigned int		fixed_post_div;
+	unsigned int		min_rate;
 
 	struct ccu_common	common;
 };
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 03/15] clk: sunxi-ng: Add check for maximum rate to NKM PLLs

[Jagan Teki]

Some NKM PLLs, frequency can be set above PLL working range.

Add a constraint for maximum supported rate. This way, drivers can
specify which is maximum allowed rate for PLL.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- new patch

 drivers/clk/sunxi-ng/ccu_nkm.c | 7 +++++++
 drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index d17539dc88dd..574fd2cd2a79 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -132,6 +132,13 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
 		return rate;
 	}
 
+	if (nkm->max_rate && rate > nkm->max_rate) {
+		rate = nkm->max_rate;
+		if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
+			rate /= nkm->fixed_post_div;
+		return rate;
+	}
+
 	ccu_nkm_find_best(*parent_rate, rate, &_nkm);
 
 	rate = *parent_rate * _nkm.n * _nkm.k / _nkm.m;
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
index ff5bd00f429f..c82590481188 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.h
+++ b/drivers/clk/sunxi-ng/ccu_nkm.h
@@ -36,6 +36,7 @@ struct ccu_nkm {
 
 	unsigned int		fixed_post_div;
 	unsigned int		min_rate;
+	unsigned int		max_rate;
 
 	struct ccu_common	common;
 };
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 04/15] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support

[Jagan Teki]

The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)

So, alter has_mod_clk bool via driver data for respective
SoC's compatible.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- none

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 47 ++++++++++++++++++++------
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  5 +++
 2 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index e3b34a345546..8e9c76febca2 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -10,6 +10,7 @@
 #include <linux/component.h>
 #include <linux/crc-ccitt.h>
 #include <linux/of_address.h>
+#include <linux/of_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/reset.h>
@@ -981,6 +982,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
 	dsi->host.ops = &sun6i_dsi_host_ops;
 	dsi->host.dev = dev;
 
+	dsi->variant = of_device_get_match_data(dev);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(base)) {
@@ -1001,17 +1004,20 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
 		return PTR_ERR(dsi->reset);
 	}
 
-	dsi->mod_clk = devm_clk_get(dev, "mod");
-	if (IS_ERR(dsi->mod_clk)) {
-		dev_err(dev, "Couldn't get the DSI mod clock\n");
-		return PTR_ERR(dsi->mod_clk);
+	if (dsi->variant->has_mod_clk) {
+		dsi->mod_clk = devm_clk_get(dev, "mod");
+		if (IS_ERR(dsi->mod_clk)) {
+			dev_err(dev, "Couldn't get the DSI mod clock\n");
+			return PTR_ERR(dsi->mod_clk);
+		}
 	}
 
 	/*
 	 * In order to operate properly, that clock seems to be always
 	 * set to 297MHz.
 	 */
-	clk_set_rate_exclusive(dsi->mod_clk, 297000000);
+	if (dsi->variant->has_mod_clk)
+		clk_set_rate_exclusive(dsi->mod_clk, 297000000);
 
 	dphy_node = of_parse_phandle(dev->of_node, "phys", 0);
 	ret = sun6i_dphy_probe(dsi, dphy_node);
@@ -1043,7 +1049,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
 	pm_runtime_disable(dev);
 	sun6i_dphy_remove(dsi);
 err_unprotect_clk:
-	clk_rate_exclusive_put(dsi->mod_clk);
+	if (dsi->variant->has_mod_clk)
+		clk_rate_exclusive_put(dsi->mod_clk);
 	return ret;
 }
 
@@ -1056,7 +1063,8 @@ static int sun6i_dsi_remove(struct platform_device *pdev)
 	mipi_dsi_host_unregister(&dsi->host);
 	pm_runtime_disable(dev);
 	sun6i_dphy_remove(dsi);
-	clk_rate_exclusive_put(dsi->mod_clk);
+	if (dsi->variant->has_mod_clk)
+		clk_rate_exclusive_put(dsi->mod_clk);
 
 	return 0;
 }
@@ -1066,7 +1074,8 @@ static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
 	struct sun6i_dsi *dsi = dev_get_drvdata(dev);
 
 	reset_control_deassert(dsi->reset);
-	clk_prepare_enable(dsi->mod_clk);
+	if (dsi->variant->has_mod_clk)
+		clk_prepare_enable(dsi->mod_clk);
 
 	/*
 	 * Enable the DSI block.
@@ -1094,7 +1103,8 @@ static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
 {
 	struct sun6i_dsi *dsi = dev_get_drvdata(dev);
 
-	clk_disable_unprepare(dsi->mod_clk);
+	if (dsi->variant->has_mod_clk)
+		clk_disable_unprepare(dsi->mod_clk);
 	reset_control_assert(dsi->reset);
 
 	return 0;
@@ -1106,9 +1116,24 @@ static const struct dev_pm_ops sun6i_dsi_pm_ops = {
 			   NULL)
 };
 
+static const struct sun6i_dsi_variant sun6i_a31_dsi = {
+	.has_mod_clk = true,
+};
+
+static const struct sun6i_dsi_variant sun50i_a64_dsi = {
+	.has_mod_clk = false,
+};
+
 static const struct of_device_id sun6i_dsi_of_table[] = {
-	{ .compatible = "allwinner,sun6i-a31-mipi-dsi" },
-	{ }
+	{
+		.compatible = "allwinner,sun6i-a31-mipi-dsi",
+		.data = &sun6i_a31_dsi,
+	},
+	{
+		.compatible = "allwinner,sun50i-a64-mipi-dsi",
+		.data = &sun50i_a64_dsi,
+	},
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
 
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
index dbbc5b3ecbda..597b62227019 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
@@ -20,6 +20,10 @@ struct sun6i_dphy {
 	struct reset_control	*reset;
 };
 
+struct sun6i_dsi_variant {
+	bool			has_mod_clk;
+};
+
 struct sun6i_dsi {
 	struct drm_connector	connector;
 	struct drm_encoder	encoder;
@@ -35,6 +39,7 @@ struct sun6i_dsi {
 	struct sun4i_drv	*drv;
 	struct mipi_dsi_device	*device;
 	struct drm_panel	*panel;
+	const struct sun6i_dsi_variant	*variant;
 };
 
 static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 05/15] dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI

[Jagan Teki]

The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v2:
- none

 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
index 6a6cf5de08b0..9fa6e7a758ad 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
@@ -12,6 +12,7 @@ The DSI Encoder generates the DSI signal from the TCON's.
 Required properties:
   - compatible: value must be one of:
     * allwinner,sun6i-a31-mipi-dsi
+    * allwinner,sun50i-a64-mipi-dsi
   - reg: base address and size of memory-mapped region
   - interrupts: interrupt associated to this IP
   - clocks: phandles to the clocks feeding the DSI encoder
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 06/15] drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param transfer

[Jagan Teki]

Short transfer write support for DCS and Generic transfer types
share similar way to process command sequence in DSI block so
add generic write 2 param transfer type macro so-that the panels
which are requesting similar transfer type may process properly.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- drop dev_err
- add macro in alphabetical

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 8e9c76febca2..fc8560607147 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -871,6 +871,7 @@ static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host,
 	switch (msg->type) {
 	case MIPI_DSI_DCS_SHORT_WRITE:
 	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 		ret = sun6i_dsi_dcs_write_short(dsi, msg);
 		break;
 
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 07/15] drm/sun4i: sun6i_mipi_dsi: Fix VBP size calculation

[Jagan Teki]

According to horizontal and vertical timings are defined
per the diagram from include/drm/drm_modes.h

Back porch = [hv]total - [hv]sync_end

So, update SUN6I_DSI_BASIC_SIZE0_VBP calculation as
mode->vtotal - mode->vsync_end

Horizontal or Vertical back porch calculation in BSP code
is simply following the Linux drm comment diagram from
include/drm/drm_modes.h which is

[hv]back porch = [hv]total - [hv]sync_end

BSP code form BPI-M64-bsp is calculating as vertical back porch as
in linux-sunxi/drivers/video/sunxi/disp2/disp/de/disp_lcd.c

timmings->ver_sync_time= panel_info->lcd_vspw;
timmings->ver_back_porch= panel_info->lcd_vbp-panel_info->lcd_vspw;

vbp = panel->lcd_vbp;
vspw = panel->lcd_vspw;
dsi_dev[sel]->dsi_basic_size0.bits.vbp = vbp-vspw;
dsi_dev[sel]->dsi_basic_size0.bits.vbp = panel->lcd_vbp - panel->lcd_vspw;
=>  timmings->ver_back_porch + panel_info->lcd_vspw - panel_info->lcd_vspw
=>  timmings->ver_back_porch
=>  mode->vtotal - mode->end

Which evatually same as mode->vtotal - mode->vsync_end so update the
same in SUN6I_DSI_BASIC_SIZE0_VBP

On the information note, existing SUN6I_DSI_BASIC_SIZE0_VSA is proper
value.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Add detailed commit message

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index fc8560607147..3a1d48bc1996 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -526,8 +526,8 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
 	regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG,
 		     SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end -
 					       mode->vsync_start) |
-		     SUN6I_DSI_BASIC_SIZE0_VBP(mode->vsync_start -
-					       mode->vdisplay));
+		     SUN6I_DSI_BASIC_SIZE0_VBP(mode->vtotal -
+					       mode->vsync_end));
 
 	regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG,
 		     SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) |
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 08/15] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits

[Jagan Teki]

TCON DRQ set bits for non-burst DSI mode can computed via
horizontal front porch instead of front porch + sync timings.

According to BSP code form BPI-M64-bsp in
linux-sunxi/drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c
TCON DRQ set bits are computed for non-burst mode as

=> panel->lcd_ht -    panel->lcd_x - panel->lcd_hbp
=> (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x)
   - panel->lcd_x - panel->hbp
=> timmings->hor_front_porch
=> mode->hsync_start - mode->hdisplay

So, update the DRQ set bits accordingly.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Add detailed commit message

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 3a1d48bc1996..8d154cf2e6d6 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
 	struct mipi_dsi_device *device = dsi->device;
 	u32 val = 0;
 
-	if ((mode->hsync_end - mode->hdisplay) > 20) {
+	if ((mode->hsync_start - mode->hdisplay) > 20) {
 		/* Maaaaaagic */
-		u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
+		u16 drq = (mode->hsync_start - mode->hdisplay) - 20;
 
 		drq *= mipi_dsi_pixel_format_to_bpp(device->format);
 		drq /= 32;
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 09/15] drm/sun4i: sun6i_mipi_dsi: Refactor vertical video start delay

[Jagan Teki]

Accordingly to BPI-M64-bsp DE DSI code Video start delay
can be computed by subtracting total vertical timing with
front porch timing and with adding 1 delay line for TCON.

Video start delay is computed in BPI-M64-bsp code as
linux-sunxi/drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c

u32 vfp = panel->lcd_vt - panel->lcd_y - panel->lcd_vbp;
=> (panel->lcd_vt) - panel->lcd_y - (panel->lcd_vbp)
=> (timmings->ver_front_porch + panel->lcd_vbp + panel->lcd_y)
   - panel->lcd_y - (panel->lcd_vbp)
=> timmings->ver_front_porch + panel->lcd_vbp + panel->lcd_y
  			     - panel->lcd_y - panel->lcd_vbp
=> timmings->ver_front_porch

So, update the start delay computation accordingly.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Add detailed commit message

 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 8d154cf2e6d6..6bece492b1f7 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -358,7 +358,17 @@ static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
 static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
 					   struct drm_display_mode *mode)
 {
-	return mode->vtotal - (mode->vsync_end - mode->vdisplay) + 1;
+	u32 vfp = mode->vsync_start - mode->vdisplay;
+	u32 start_delay;
+
+	start_delay = mode->vtotal - vfp + 1;
+	if (start_delay > mode->vtotal)
+		start_delay -= mode->vtotal;
+
+	if (!start_delay)
+		start_delay = 1;
+
+	return start_delay;
 }
 
 static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 10/15] dt-bindings: panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge

[Jagan Teki]

Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge panel,
the same panel PCB comes with parallel RBG which is supported via
panel-simple driver with "bananapi,s070wv20-ct16" compatible.

But this binding is specific for MIPI DSI to RGB bridge panels,
which usually accessed using MIPI DSI controller driver.

for information:
- "bananapi,s070wv20-ct16" compatible for parallel RGB panels
- "bananapi,s070wv20-ct16-icn6211" compatible for MIPI-DSI to RGB
bridge panels

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Add detailed commit message
- Update the bindings as MIPI-DSI to RGB bridge

 .../panel/bananapi,s070wv20-ct16-icn6211.txt  | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16-icn6211.txt

diff --git a/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16-icn6211.txt b/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16-icn6211.txt
new file mode 100644
index 000000000000..68a89b6feaee
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16-icn6211.txt
@@ -0,0 +1,21 @@
+Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge
+
+Required properties:
+- compatible: must be "bananapi,s070wv20-ct16-icn6211"
+- reg: DSI virtual channel used by that screen
+- avdd-supply: analog regulator dc1 switch
+- dvdd-supply: 3v3 digital regulator
+- reset-gpios: a GPIO phandle for the reset pin
+
+Optional properties:
+- backlight: phandle for the backlight control.
+
+Example:
+panel@0 {
+	compatible = "bananapi,s070wv20-ct16-icn6211";
+	reg = <0>;
+	avdd-supply = <&reg_dc1sw>;
+	dvdd-supply = <&reg_dldo1>;
+	reset-gpios = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+	backlight = <&backlight_dsi>;
+};
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 11/15] drm/panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge

[Jagan Teki]

Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge
panel which can be used to connect via DSI port on BPI-M64 board,
so add a driver for it.

The same panel PCB comes with parallel RBG which is supported via
panel-simple driver with "bananapi,s070wv20-ct16" compatible.

Panel clock frequency used by BSP is 30MHz but the same cannot
be handle via A64 PLL_MIPI and which is not working. So use 55MHz
so-that it can rounded to 33MHz while calculating nkm dividers.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Add detailed commit message
- Update the compatible string for MIPI-DSI to RGB bridge
- Use clock as 55MHz

 drivers/gpu/drm/panel/Kconfig                 |   9 +
 drivers/gpu/drm/panel/Makefile                |   1 +
 .../panel/panel-bananapi-s070wv20-icn6211.c   | 336 ++++++++++++++++++
 3 files changed, 346 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 6020c30a33b3..20b88c275421 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -17,6 +17,15 @@ config DRM_PANEL_ARM_VERSATILE
 	  reference designs. The panel is detected using special registers
 	  in the Versatile family syscon registers.
 
+config DRM_PANEL_BANANAPI_S070WV20_ICN6211
+	tristate "Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge panel driver"
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y if you want to enable support for panels based on the
+	  Bananapi S070WV20-CT16 MIPI-DSI controller.
+
 config DRM_PANEL_LVDS
 	tristate "Generic LVDS panel driver"
 	depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 5ccaaa9d13af..04696bb85218 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BANANAPI_S070WV20_ICN6211) += panel-bananapi-s070wv20-icn6211.o
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o
diff --git a/drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c b/drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c
new file mode 100644
index 000000000000..643b215bec34
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-bananapi-s070wv20-icn6211.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <linux/backlight.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+
+#include <video/mipi_display.h>
+
+struct s070wv20 {
+	struct drm_panel	panel;
+	struct mipi_dsi_device	*dsi;
+
+	struct backlight_device	*backlight;
+	struct regulator	*dvdd;
+	struct regulator	*avdd;
+	struct gpio_desc	*reset;
+
+	bool			is_enabled;
+	bool			is_prepared;
+};
+
+static inline struct s070wv20 *panel_to_s070wv20(struct drm_panel *panel)
+{
+	return container_of(panel, struct s070wv20, panel);
+}
+
+struct s070wv20_init_cmd {
+	size_t len;
+	const char *data;
+};
+
+#define S070WV20_INIT_CMD(...) { \
+	.len = sizeof((char[]){__VA_ARGS__}), \
+	.data = (char[]){__VA_ARGS__} }
+
+static const struct s070wv20_init_cmd s070wv20_init_cmds[] = {
+	S070WV20_INIT_CMD(0x7A, 0xC1),
+	S070WV20_INIT_CMD(0x20, 0x20),
+	S070WV20_INIT_CMD(0x21, 0xE0),
+	S070WV20_INIT_CMD(0x22, 0x13),
+	S070WV20_INIT_CMD(0x23, 0x28),
+	S070WV20_INIT_CMD(0x24, 0x30),
+	S070WV20_INIT_CMD(0x25, 0x28),
+	S070WV20_INIT_CMD(0x26, 0x00),
+	S070WV20_INIT_CMD(0x27, 0x0D),
+	S070WV20_INIT_CMD(0x28, 0x03),
+	S070WV20_INIT_CMD(0x29, 0x1D),
+	S070WV20_INIT_CMD(0x34, 0x80),
+	S070WV20_INIT_CMD(0x36, 0x28),
+	S070WV20_INIT_CMD(0xB5, 0xA0),
+	S070WV20_INIT_CMD(0x5C, 0xFF),
+	S070WV20_INIT_CMD(0x2A, 0x01),
+	S070WV20_INIT_CMD(0x56, 0x92),
+	S070WV20_INIT_CMD(0x6B, 0x71),
+	S070WV20_INIT_CMD(0x69, 0x2B),
+	S070WV20_INIT_CMD(0x10, 0x40),
+	S070WV20_INIT_CMD(0x11, 0x98),
+	S070WV20_INIT_CMD(0xB6, 0x20),
+	S070WV20_INIT_CMD(0x51, 0x20),
+	S070WV20_INIT_CMD(0x09, 0x10),
+};
+
+static int s070wv20_prepare(struct drm_panel *panel)
+{
+	struct s070wv20 *ctx = panel_to_s070wv20(panel);
+	struct mipi_dsi_device *dsi = ctx->dsi;
+	unsigned int i;
+	int ret;
+
+	if (ctx->is_prepared)
+		return 0;
+
+	msleep(50);
+
+	gpiod_set_value(ctx->reset, 1);
+	msleep(50);
+
+	gpiod_set_value(ctx->reset, 0);
+	msleep(50);
+
+	gpiod_set_value(ctx->reset, 1);
+	msleep(20);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to exit sleep mode: %d\n", ret);
+		return ret;
+	}
+
+	msleep(120);
+
+	for (i = 0; i < ARRAY_SIZE(s070wv20_init_cmds); i++) {
+		const struct s070wv20_init_cmd *cmd = &s070wv20_init_cmds[i];
+
+		ret = mipi_dsi_generic_write(dsi, cmd->data, cmd->len);
+		if (ret < 0)
+			return ret;
+
+		msleep(10);
+	}
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to set display on: %d\n", ret);
+		return ret;
+	}
+
+	ctx->is_prepared = true;
+
+	return 0;
+}
+
+static int s070wv20_enable(struct drm_panel *panel)
+{
+	struct s070wv20 *ctx = panel_to_s070wv20(panel);
+
+	if (ctx->is_enabled)
+		return 0;
+
+	msleep(120);
+
+	backlight_enable(ctx->backlight);
+	ctx->is_enabled = true;
+
+	return 0;
+}
+
+static int s070wv20_disable(struct drm_panel *panel)
+{
+	struct s070wv20 *ctx = panel_to_s070wv20(panel);
+
+	if (!ctx->is_enabled)
+		return 0;
+
+	backlight_disable(ctx->backlight);
+	ctx->is_enabled = false;
+
+	return 0;
+}
+
+static int s070wv20_unprepare(struct drm_panel *panel)
+{
+	struct s070wv20 *ctx = panel_to_s070wv20(panel);
+	int ret;
+
+	if (!ctx->is_prepared)
+		return 0;
+
+	ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
+	if (ret < 0)
+		dev_err(panel->dev, "failed to set display off: %d\n", ret);
+
+	ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
+	if (ret < 0)
+		dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
+
+	msleep(100);
+
+	regulator_disable(ctx->avdd);
+
+	regulator_disable(ctx->dvdd);
+
+	gpiod_set_value(ctx->reset, 0);
+
+	gpiod_set_value(ctx->reset, 1);
+
+	gpiod_set_value(ctx->reset, 0);
+
+	ctx->is_prepared = false;
+
+	return 0;
+}
+
+static const struct drm_display_mode s070wv20_default_mode = {
+	.clock = 55000,
+	.vrefresh = 60,
+
+	.hdisplay = 800,
+	.hsync_start = 800 + 40,
+	.hsync_end = 800 + 40 + 48,
+	.htotal = 800 + 40 + 48 + 40,
+
+	.vdisplay = 480,
+	.vsync_start = 480 + 13,
+	.vsync_end = 480 + 13 + 3,
+	.vtotal = 480 + 13 + 3 + 29,
+};
+
+static int s070wv20_get_modes(struct drm_panel *panel)
+{
+	struct drm_connector *connector = panel->connector;
+	struct s070wv20 *ctx = panel_to_s070wv20(panel);
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(panel->drm, &s070wv20_default_mode);
+	if (!mode) {
+		dev_err(&ctx->dsi->dev, "failed to add mode %ux%ux@%u\n",
+			s070wv20_default_mode.hdisplay,
+			s070wv20_default_mode.vdisplay,
+			s070wv20_default_mode.vrefresh);
+		return -ENOMEM;
+	}
+
+	drm_mode_set_name(mode);
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_probed_add(connector, mode);
+
+	panel->connector->display_info.width_mm = 86;
+	panel->connector->display_info.height_mm = 154;
+
+	return 1;
+}
+
+static const struct drm_panel_funcs s070wv20_funcs = {
+	.disable = s070wv20_disable,
+	.unprepare = s070wv20_unprepare,
+	.prepare = s070wv20_prepare,
+	.enable = s070wv20_enable,
+	.get_modes = s070wv20_get_modes,
+};
+
+static int s070wv20_dsi_probe(struct mipi_dsi_device *dsi)
+{
+	struct device_node *np;
+	struct s070wv20 *ctx;
+	int ret;
+
+	ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+	mipi_dsi_set_drvdata(dsi, ctx);
+	ctx->dsi = dsi;
+
+	drm_panel_init(&ctx->panel);
+	ctx->panel.dev = &dsi->dev;
+	ctx->panel.funcs = &s070wv20_funcs;
+
+	ctx->dvdd = devm_regulator_get(&dsi->dev, "dvdd");
+	if (IS_ERR(ctx->dvdd)) {
+		dev_err(&dsi->dev, "Couldn't get dvdd regulator\n");
+		return PTR_ERR(ctx->dvdd);
+	}
+
+	ctx->avdd = devm_regulator_get(&dsi->dev, "avdd");
+	if (IS_ERR(ctx->avdd)) {
+		dev_err(&dsi->dev, "Couldn't get avdd regulator\n");
+		return PTR_ERR(ctx->avdd);
+	}
+
+	ret = regulator_enable(ctx->dvdd);
+	if (ret)
+		return ret;
+
+	msleep(5);
+
+	ret = regulator_enable(ctx->avdd);
+	if (ret)
+		return ret;
+
+	msleep(5);
+
+	ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
+	if (IS_ERR(ctx->reset)) {
+		dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
+		return PTR_ERR(ctx->reset);
+	}
+
+	np = of_parse_phandle(dsi->dev.of_node, "backlight", 0);
+	if (np) {
+		ctx->backlight = of_find_backlight_by_node(np);
+		of_node_put(np);
+
+		if (!ctx->backlight)
+			return -EPROBE_DEFER;
+	}
+
+	ret = drm_panel_add(&ctx->panel);
+	if (ret < 0)
+		return ret;
+
+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->lanes = 4;
+
+	return mipi_dsi_attach(dsi);
+}
+
+static int s070wv20_dsi_remove(struct mipi_dsi_device *dsi)
+{
+	struct s070wv20 *ctx = mipi_dsi_get_drvdata(dsi);
+
+	mipi_dsi_detach(dsi);
+	drm_panel_remove(&ctx->panel);
+
+	if (ctx->backlight)
+		put_device(&ctx->backlight->dev);
+
+	return 0;
+}
+
+static const struct of_device_id s070wv20_of_match[] = {
+	{ .compatible = "bananapi,s070wv20-ct16-icn6211", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, s070wv20_of_match);
+
+static struct mipi_dsi_driver s070wv20_driver = {
+	.probe = s070wv20_dsi_probe,
+	.remove = s070wv20_dsi_remove,
+	.driver = {
+		.name = "bananapi-s070wv20-ct16-icn6211",
+		.of_match_table = s070wv20_of_match,
+	},
+};
+module_mipi_dsi_driver(s070wv20_driver);
+
+MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
+MODULE_DESCRIPTION("Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB");
+MODULE_LICENSE("GPL v2");
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI

[Jagan Teki]

A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
using minimum 500MHz can't release the clock and which
is not working.

So use working minimum rate as 300MHz which is tested on
Bananapi DSI panel.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- new patch

 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 019d67bf97c4..5a3a5b821f8b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -167,6 +167,8 @@ static struct ccu_nkm pll_mipi_clk = {
 	.n		= _SUNXI_CCU_MULT(8, 4),
 	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
 	.m		= _SUNXI_CCU_DIV(0, 4),
+	.min_rate	= 300000000,		/* Actual rate is 500MHz */
+	.max_rate	= 1400000000UL,
 	.common		= {
 		.reg		= 0x040,
 		.hw.init	= CLK_HW_INIT("pll-mipi", "pll-video0",
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 13/15] dt-bindings: sun6i-dsi: Add compatible for A64 DPHY

[Jagan Teki]

The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
on the one on A31.

Add A64 compatible and append A31 compatible as fallback.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- new patch

 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
index 9fa6e7a758ad..704fb31962f2 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
@@ -36,7 +36,7 @@ D-PHY
 
 Required properties:
   - compatible: value must be one of:
-    * allwinner,sun6i-a31-mipi-dphy
+    * "allwinner,sun50i-a64-mipi-dphy", "allwinner,sun6i-a31-mipi-dphy"
   - reg: base address and size of memory-mapped region
   - clocks: phandles to the clocks feeding the DSI encoder
     * bus: the DSI interface clock
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 14/15] arm64: dts: allwinner: a64: Add DSI pipeline

[Jagan Teki]

The A64 has a MIPI-DSI block which is similar to A31
without mod clock.

So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper DSI pipeline.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- use A64 dphy compatible

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index f3a66f888205..f82e6b165d57 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -320,6 +320,11 @@
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <1>;
+
+					tcon0_out_dsi: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&dsi_in_tcon0>;
+					};
 				};
 			};
 		};
@@ -818,6 +823,46 @@
 			#interrupt-cells = <3>;
 		};
 
+
+		dsi: dsi@1ca0000 {
+			compatible = "allwinner,sun50i-a64-mipi-dsi";
+			reg = <0x01ca0000 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MIPI_DSI>;
+			clock-names = "bus";
+			resets = <&ccu RST_BUS_MIPI_DSI>;
+			phys = <&dphy>;
+			phy-names = "dphy";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					dsi_in_tcon0: endpoint {
+						remote-endpoint = <&tcon0_out_dsi>;
+					};
+				};
+			};
+		};
+
+		dphy: d-phy@1ca1000 {
+			compatible = "allwinner,sun50i-a64-mipi-dphy",
+				     "allwinner,sun6i-a31-mipi-dphy";
+			reg = <0x01ca1000 0x1000>;
+			clocks = <&ccu CLK_BUS_MIPI_DSI>,
+				 <&ccu CLK_DSI_DPHY>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_MIPI_DSI>;
+			status = "disabled";
+			#phy-cells = <0>;
+		};
+
 		pwm: pwm@1c21400 {
 			compatible = "allwinner,sun50i-a64-pwm",
 				     "allwinner,sun5i-a13-pwm";
-- 
2.18.0.321.gffc6fa0e3

[PATCH v2 15/15] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel

[Jagan Teki]

This patch add support for Bananapi S070WV20-CT16 DSI panel to
BPI-M64 board.

DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC1 as DVDD supply
- PD6 gpio for reset pin
- PD5 gpio for backlight enable pin
- PD7 gpio for backlight vdd supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Use quadratic rule on pwm brightness

 .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index ef1c90401bb2..e0c6d1870a94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -45,6 +45,7 @@
 #include "sun50i-a64.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
 
 / {
 	model = "BananaPi-M64";
@@ -56,6 +57,24 @@
 		serial1 = &uart1;
 	};
 
+	vdd_bl: regulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "bl-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */
+		enable-active-high;
+	};
+
+	backlight_dsi: backlight-dsi {
+		compatible = "pwm-backlight";
+		pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <1 2 4 8 16 32 64 128 512>;
+		default-brightness-level = <2>;
+		enable-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5 */
+		power-supply = <&vdd_bl>;
+	};
+
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
@@ -101,6 +120,23 @@
 	status = "okay";
 };
 
+&dphy {
+	status = "okay";
+};
+
+&dsi {
+	status = "okay";
+
+	panel@0 {
+		compatible = "bananapi,s070wv20-ct16-icn6211";
+		reg = <0>;
+		avdd-supply = <&reg_dc1sw>;
+		dvdd-supply = <&reg_dldo1>;
+		reset-gpios = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+		backlight = <&backlight_dsi>;
+	};
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -193,6 +229,12 @@
 	status = "okay";
 };
 
+&r_pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&r_pwm_pin>;
+	status = "okay";
+};
+
 &r_rsb {
 	status = "okay";
 
-- 
2.18.0.321.gffc6fa0e3

Re: [PATCH v2 03/15] clk: sunxi-ng: Add check for maximum rate to NKM PLLs

[Vasily Khoruzhick]

On Tue, Oct 23, 2018 at 8:51 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> Some NKM PLLs, frequency can be set above PLL working range.
>
> Add a constraint for maximum supported rate. This way, drivers can
> specify which is maximum allowed rate for PLL.

I'd squash patches 2 and 3 into a single patch.

> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - new patch
>
>  drivers/clk/sunxi-ng/ccu_nkm.c | 7 +++++++
>  drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> index d17539dc88dd..574fd2cd2a79 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> @@ -132,6 +132,13 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>                 return rate;
>         }
>
> +       if (nkm->max_rate && rate > nkm->max_rate) {
> +               rate = nkm->max_rate;
> +               if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> +                       rate /= nkm->fixed_post_div;
> +               return rate;
> +       }
> +
>         ccu_nkm_find_best(*parent_rate, rate, &_nkm);
>
>         rate = *parent_rate * _nkm.n * _nkm.k / _nkm.m;
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
> index ff5bd00f429f..c82590481188 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.h
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.h
> @@ -36,6 +36,7 @@ struct ccu_nkm {
>
>         unsigned int            fixed_post_div;
>         unsigned int            min_rate;
> +       unsigned int            max_rate;
>
>         struct ccu_common       common;
>  };
> --
> 2.18.0.321.gffc6fa0e3
>

Re: [PATCH v2 01/15] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY

[Stephen Boyd]

Quoting Jagan Teki (2018-10-23 08:50:21)
> DSI DPHY gate bit on MIPI DSI clock register is bit 15
> not bit 30.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH v2 02/15] clk: sunxi-ng: Add check for minimal rate to NKM PLLs

[Stephen Boyd]

Quoting Jagan Teki (2018-10-23 08:50:22)
> Some NKM PLLs doesn't work well when their output clock rate is set below
> certain rate.
> 
> So, add support for minimal rate for relevant PLLs.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH v2 03/15] clk: sunxi-ng: Add check for maximum rate to NKM PLLs

[Stephen Boyd]

Quoting Jagan Teki (2018-10-23 08:50:23)
> Some NKM PLLs, frequency can be set above PLL working range.
> 
> Add a constraint for maximum supported rate. This way, drivers can
> specify which is maximum allowed rate for PLL.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI

[Stephen Boyd]

Quoting Jagan Teki (2018-10-23 08:50:32)
> A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> using minimum 500MHz can't release the clock and which
> is not working.
> 
> So use working minimum rate as 300MHz which is tested on
> Bananapi DSI panel.

That's weird, but OK.

> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH v2 02/15] clk: sunxi-ng: Add check for minimal rate to NKM PLLs

[Maxime Ripard]

On Tue, Oct 23, 2018 at 09:20:22PM +0530, Jagan Teki wrote:
> Some NKM PLLs doesn't work well when their output clock rate is set below
> certain rate.
> 
> So, add support for minimal rate for relevant PLLs.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - new patch
> 
>  drivers/clk/sunxi-ng/ccu_nkm.c | 7 +++++++
>  drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> index 841840e35e61..d17539dc88dd 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> @@ -125,6 +125,13 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>  	if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
>  		rate *= nkm->fixed_post_div;
>  
> +	if (rate < nkm->min_rate) {
> +		rate = nkm->min_rate;
> +		if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> +			rate /= nkm->fixed_post_div;

I'm not sure this is right. Is the post divider taken into account to
calculate the minimum, or is the minimum on the rate before the fixed
post divider.

How did you test this?

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v2 04/15] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 4894 bytes --]

On Tue, Oct 23, 2018 at 09:20:24PM +0530, Jagan Teki wrote:
> The MIPI DSI controller on Allwinner A64 is similar to
> Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
> 
> So, alter has_mod_clk bool via driver data for respective
> SoC's compatible.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - none
> 
>  drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 47 ++++++++++++++++++++------
>  drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  5 +++
>  2 files changed, 41 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> index e3b34a345546..8e9c76febca2 100644
> --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> @@ -10,6 +10,7 @@
>  #include <linux/component.h>
>  #include <linux/crc-ccitt.h>
>  #include <linux/of_address.h>
> +#include <linux/of_device.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/regmap.h>
>  #include <linux/reset.h>
> @@ -981,6 +982,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
>  	dsi->host.ops = &sun6i_dsi_host_ops;
>  	dsi->host.dev = dev;
>  
> +	dsi->variant = of_device_get_match_data(dev);
> +
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	base = devm_ioremap_resource(dev, res);
>  	if (IS_ERR(base)) {
> @@ -1001,17 +1004,20 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
>  		return PTR_ERR(dsi->reset);
>  	}
>  
> -	dsi->mod_clk = devm_clk_get(dev, "mod");
> -	if (IS_ERR(dsi->mod_clk)) {
> -		dev_err(dev, "Couldn't get the DSI mod clock\n");
> -		return PTR_ERR(dsi->mod_clk);
> +	if (dsi->variant->has_mod_clk) {
> +		dsi->mod_clk = devm_clk_get(dev, "mod");
> +		if (IS_ERR(dsi->mod_clk)) {
> +			dev_err(dev, "Couldn't get the DSI mod clock\n");
> +			return PTR_ERR(dsi->mod_clk);
> +		}
>  	}
>  
>  	/*
>  	 * In order to operate properly, that clock seems to be always
>  	 * set to 297MHz.
>  	 */
> -	clk_set_rate_exclusive(dsi->mod_clk, 297000000);
> +	if (dsi->variant->has_mod_clk)
> +		clk_set_rate_exclusive(dsi->mod_clk, 297000000);
>  
>  	dphy_node = of_parse_phandle(dev->of_node, "phys", 0);
>  	ret = sun6i_dphy_probe(dsi, dphy_node);
> @@ -1043,7 +1049,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
>  	pm_runtime_disable(dev);
>  	sun6i_dphy_remove(dsi);
>  err_unprotect_clk:
> -	clk_rate_exclusive_put(dsi->mod_clk);
> +	if (dsi->variant->has_mod_clk)
> +		clk_rate_exclusive_put(dsi->mod_clk);
>  	return ret;
>  }
>  
> @@ -1056,7 +1063,8 @@ static int sun6i_dsi_remove(struct platform_device *pdev)
>  	mipi_dsi_host_unregister(&dsi->host);
>  	pm_runtime_disable(dev);
>  	sun6i_dphy_remove(dsi);
> -	clk_rate_exclusive_put(dsi->mod_clk);
> +	if (dsi->variant->has_mod_clk)
> +		clk_rate_exclusive_put(dsi->mod_clk);
>  
>  	return 0;
>  }
> @@ -1066,7 +1074,8 @@ static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
>  	struct sun6i_dsi *dsi = dev_get_drvdata(dev);
>  
>  	reset_control_deassert(dsi->reset);
> -	clk_prepare_enable(dsi->mod_clk);
> +	if (dsi->variant->has_mod_clk)
> +		clk_prepare_enable(dsi->mod_clk);
>  
>  	/*
>  	 * Enable the DSI block.
> @@ -1094,7 +1103,8 @@ static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
>  {
>  	struct sun6i_dsi *dsi = dev_get_drvdata(dev);
>  
> -	clk_disable_unprepare(dsi->mod_clk);
> +	if (dsi->variant->has_mod_clk)
> +		clk_disable_unprepare(dsi->mod_clk);
>  	reset_control_assert(dsi->reset);
>  
>  	return 0;
> @@ -1106,9 +1116,24 @@ static const struct dev_pm_ops sun6i_dsi_pm_ops = {
>  			   NULL)
>  };
>  
> +static const struct sun6i_dsi_variant sun6i_a31_dsi = {
> +	.has_mod_clk = true,
> +};
> +
> +static const struct sun6i_dsi_variant sun50i_a64_dsi = {
> +	.has_mod_clk = false,

This is the default already.

> +};
> +
>  static const struct of_device_id sun6i_dsi_of_table[] = {
> -	{ .compatible = "allwinner,sun6i-a31-mipi-dsi" },
> -	{ }
> +	{
> +		.compatible = "allwinner,sun6i-a31-mipi-dsi",
> +		.data = &sun6i_a31_dsi,
> +	},
> +	{
> +		.compatible = "allwinner,sun50i-a64-mipi-dsi",
> +		.data = &sun50i_a64_dsi,
> +	},
> +	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
>  
> diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> index dbbc5b3ecbda..597b62227019 100644
> --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> @@ -20,6 +20,10 @@ struct sun6i_dphy {
>  	struct reset_control	*reset;
>  };
>  
> +struct sun6i_dsi_variant {
> +	bool			has_mod_clk;
> +};
> +

This should be part of a separate patch.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 10/15] dt-bindings: panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge

[Maxime Ripard]

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On Tue, Oct 23, 2018 at 09:20:30PM +0530, Jagan Teki wrote:
> Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge panel,
> the same panel PCB comes with parallel RBG which is supported via
> panel-simple driver with "bananapi,s070wv20-ct16" compatible.
> 
> But this binding is specific for MIPI DSI to RGB bridge panels,
> which usually accessed using MIPI DSI controller driver.
> 
> for information:
> - "bananapi,s070wv20-ct16" compatible for parallel RGB panels
> - "bananapi,s070wv20-ct16-icn6211" compatible for MIPI-DSI to RGB
> bridge panels
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Why not just reusing the same binding document?

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 13/15] dt-bindings: sun6i-dsi: Add compatible for A64 DPHY

[Maxime Ripard]

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On Tue, Oct 23, 2018 at 09:20:33PM +0530, Jagan Teki wrote:
> The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
> on the one on A31.
> 
> Add A64 compatible and append A31 compatible as fallback.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - new patch
> 
>  Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> index 9fa6e7a758ad..704fb31962f2 100644
> --- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> @@ -36,7 +36,7 @@ D-PHY
>  
>  Required properties:
>    - compatible: value must be one of:
> -    * allwinner,sun6i-a31-mipi-dphy
> +    * "allwinner,sun50i-a64-mipi-dphy", "allwinner,sun6i-a31-mipi-dphy"

No. you need both. The A64 MIPI DPHY one needs to be always set with
the A31 fallback, but the A31 is also usable on its own.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 14/15] arm64: dts: allwinner: a64: Add DSI pipeline

[Maxime Ripard]

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On Tue, Oct 23, 2018 at 09:20:34PM +0530, Jagan Teki wrote:
> The A64 has a MIPI-DSI block which is similar to A31
> without mod clock.
> 
> So, add dsi node with A64 compatible, dphy node with
> A31 compatible and finally connect dsi to tcon0 to
> make proper DSI pipeline.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - use A64 dphy compatible
> 
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45 +++++++++++++++++++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index f3a66f888205..f82e6b165d57 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -320,6 +320,11 @@
>  					#address-cells = <1>;
>  					#size-cells = <0>;
>  					reg = <1>;
> +
> +					tcon0_out_dsi: endpoint@1 {
> +						reg = <1>;
> +						remote-endpoint = <&dsi_in_tcon0>;

You need to set the allwinner,channel property there.

> +					};
>  				};
>  			};
>  		};
> @@ -818,6 +823,46 @@
>  			#interrupt-cells = <3>;
>  		};
>  
> +
> +		dsi: dsi@1ca0000 {
> +			compatible = "allwinner,sun50i-a64-mipi-dsi";
> +			reg = <0x01ca0000 0x1000>;
> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_MIPI_DSI>;
> +			clock-names = "bus";
> +			resets = <&ccu RST_BUS_MIPI_DSI>;
> +			phys = <&dphy>;
> +			phy-names = "dphy";
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0>;
> +
> +					dsi_in_tcon0: endpoint {
> +						remote-endpoint = <&tcon0_out_dsi>;
> +					};
> +				};
> +			};
> +		};
> +
> +		dphy: d-phy@1ca1000 {
> +			compatible = "allwinner,sun50i-a64-mipi-dphy",
> +				     "allwinner,sun6i-a31-mipi-dphy";
> +			reg = <0x01ca1000 0x1000>;
> +			clocks = <&ccu CLK_BUS_MIPI_DSI>,
> +				 <&ccu CLK_DSI_DPHY>;
> +			clock-names = "bus", "mod";
> +			resets = <&ccu RST_BUS_MIPI_DSI>;
> +			status = "disabled";
> +			#phy-cells = <0>;
> +		};
> +

You have to order the nodes per ascending physical address ordering.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 15/15] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel

[Maxime Ripard]

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On Tue, Oct 23, 2018 at 09:20:35PM +0530, Jagan Teki wrote:
> This patch add support for Bananapi S070WV20-CT16 DSI panel to
> BPI-M64 board.
> 
> DSI panel connected via board DSI port with,
> - DC1SW as AVDD supply
> - DCDC1 as DVDD supply
> - PD6 gpio for reset pin
> - PD5 gpio for backlight enable pin
> - PD7 gpio for backlight vdd supply
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - Use quadratic rule on pwm brightness
> 
>  .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
> index ef1c90401bb2..e0c6d1870a94 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
> @@ -45,6 +45,7 @@
>  #include "sun50i-a64.dtsi"
>  
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pwm/pwm.h>
>  
>  / {
>  	model = "BananaPi-M64";
> @@ -56,6 +57,24 @@
>  		serial1 = &uart1;
>  	};
>  
> +	vdd_bl: regulator@0 {

You shouldn't have a unit address if you don't have a reg
property. This will trigger a DTC warning.

> +		compatible = "regulator-fixed";
> +		regulator-name = "bl-3v3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */
> +		enable-active-high;
> +	};
> +
> +	backlight_dsi: backlight-dsi {
> +		compatible = "pwm-backlight";
> +		pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>;
> +		brightness-levels = <1 2 4 8 16 32 64 128 512>;
> +		default-brightness-level = <2>;
> +		enable-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5 */
> +		power-supply = <&vdd_bl>;
> +	};

These nodes should be ordered by alphabetical order.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI

[Maxime Ripard]

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On Tue, Oct 23, 2018 at 09:20:32PM +0530, Jagan Teki wrote:
> A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> using minimum 500MHz can't release the clock and which
> is not working.
>
> So use working minimum rate as 300MHz which is tested on
> Bananapi DSI panel.

I'm not quite sure what you mean by that. What do you mean by "500MHz
can't release the clock"? Why would 300MHz work better then? Should be
avoid reaching 500MHz if it's a frequency in the valid range?

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 15/15] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel

[Chen-Yu Tsai]

On Wed, Oct 24, 2018 at 7:12 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> On Tue, Oct 23, 2018 at 09:20:35PM +0530, Jagan Teki wrote:
> > This patch add support for Bananapi S070WV20-CT16 DSI panel to
> > BPI-M64 board.
> >
> > DSI panel connected via board DSI port with,
> > - DC1SW as AVDD supply
> > - DCDC1 as DVDD supply
> > - PD6 gpio for reset pin
> > - PD5 gpio for backlight enable pin
> > - PD7 gpio for backlight vdd supply

This is for a removable module, which is best handled using an overlay.
This patch should be marked [DO NOT MERGE].

> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > ---
> > Changes for v2:
> > - Use quadratic rule on pwm brightness
> >
> >  .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 42 +++++++++++++++++++
> >  1 file changed, 42 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
> > index ef1c90401bb2..e0c6d1870a94 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
> > @@ -45,6 +45,7 @@
> >  #include "sun50i-a64.dtsi"
> >
> >  #include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/pwm/pwm.h>
> >
> >  / {
> >       model = "BananaPi-M64";
> > @@ -56,6 +57,24 @@
> >               serial1 = &uart1;
> >       };
> >
> > +     vdd_bl: regulator@0 {
>
> You shouldn't have a unit address if you don't have a reg
> property. This will trigger a DTC warning.
> > +             compatible = "regulator-fixed";
> > +             regulator-name = "bl-3v3";
> > +             regulator-min-microvolt = <3300000>;
> > +             regulator-max-microvolt = <3300000>;
> > +             gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */
> > +             enable-active-high;
> > +     };
> > +
> > +     backlight_dsi: backlight-dsi {

This should be just "backlight". There's nothing DSI specific
about a backlight.

> > +             compatible = "pwm-backlight";
> > +             pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>;
> > +             brightness-levels = <1 2 4 8 16 32 64 128 512>;
> > +             default-brightness-level = <2>;
> > +             enable-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5 */
> > +             power-supply = <&vdd_bl>;
> > +     };
>
> These nodes should be ordered by alphabetical order.
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

Re: [PATCH v2 10/15] dt-bindings: panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge

[Chen-Yu Tsai]

On Wed, Oct 24, 2018 at 7:08 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Tue, Oct 23, 2018 at 09:20:30PM +0530, Jagan Teki wrote:
> > Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge panel,
> > the same panel PCB comes with parallel RBG which is supported via
> > panel-simple driver with "bananapi,s070wv20-ct16" compatible.
> >
> > But this binding is specific for MIPI DSI to RGB bridge panels,
> > which usually accessed using MIPI DSI controller driver.
> >
> > for information:
> > - "bananapi,s070wv20-ct16" compatible for parallel RGB panels
> > - "bananapi,s070wv20-ct16-icn6211" compatible for MIPI-DSI to RGB
> > bridge panels
> >
> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>
> Why not just reusing the same binding document?

Agreed. Just put the MIPI-DSI-specific information you added here
into the existing document.

Rob suggested that we could even use the same compatible. That would
make sense if you are modelling the entire panel + PCB as a module,
instead of a panel node + a bridge node as I originally wanted.
Don't worry, I gave it some thought and I think having a single
combined panel node makes more sense.

ChenYu

Re: [PATCH v2 02/15] clk: sunxi-ng: Add check for minimal rate to NKM PLLs

[Jagan Teki]

On Wed, Oct 24, 2018 at 11:34 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> On Tue, Oct 23, 2018 at 09:20:22PM +0530, Jagan Teki wrote:
> > Some NKM PLLs doesn't work well when their output clock rate is set below
> > certain rate.
> >
> > So, add support for minimal rate for relevant PLLs.
> >
> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > ---
> > Changes for v2:
> > - new patch
> >
> >  drivers/clk/sunxi-ng/ccu_nkm.c | 7 +++++++
> >  drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
> >  2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> > index 841840e35e61..d17539dc88dd 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> > @@ -125,6 +125,13 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> >       if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> >               rate *= nkm->fixed_post_div;
> >
> > +     if (rate < nkm->min_rate) {
> > +             rate = nkm->min_rate;
> > +             if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> > +                     rate /= nkm->fixed_post_div;
>
> I'm not sure this is right. Is the post divider taken into account to
> calculate the minimum, or is the minimum on the rate before the fixed
> post divider.

Since we are returning from here, we need to take care post div which
is actually doing at the end of round_rate.

>
> How did you test this?

I've not used this on PLL_MIPI atleast, so I didn't test this.

Re: [PATCH v2 04/15] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support

[Jagan Teki]

On Wed, Oct 24, 2018 at 11:36 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> On Tue, Oct 23, 2018 at 09:20:24PM +0530, Jagan Teki wrote:
> > The MIPI DSI controller on Allwinner A64 is similar to
> > Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
> >
> > So, alter has_mod_clk bool via driver data for respective
> > SoC's compatible.
> >
> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > ---
> > Changes for v2:
> > - none
> >
> >  drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 47 ++++++++++++++++++++------
> >  drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  5 +++
> >  2 files changed, 41 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > index e3b34a345546..8e9c76febca2 100644
> > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > @@ -10,6 +10,7 @@
> >  #include <linux/component.h>
> >  #include <linux/crc-ccitt.h>
> >  #include <linux/of_address.h>
> > +#include <linux/of_device.h>
> >  #include <linux/pm_runtime.h>
> >  #include <linux/regmap.h>
> >  #include <linux/reset.h>
> > @@ -981,6 +982,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
> >       dsi->host.ops = &sun6i_dsi_host_ops;
> >       dsi->host.dev = dev;
> >
> > +     dsi->variant = of_device_get_match_data(dev);
> > +
> >       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >       base = devm_ioremap_resource(dev, res);
> >       if (IS_ERR(base)) {
> > @@ -1001,17 +1004,20 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
> >               return PTR_ERR(dsi->reset);
> >       }
> >
> > -     dsi->mod_clk = devm_clk_get(dev, "mod");
> > -     if (IS_ERR(dsi->mod_clk)) {
> > -             dev_err(dev, "Couldn't get the DSI mod clock\n");
> > -             return PTR_ERR(dsi->mod_clk);
> > +     if (dsi->variant->has_mod_clk) {
> > +             dsi->mod_clk = devm_clk_get(dev, "mod");
> > +             if (IS_ERR(dsi->mod_clk)) {
> > +                     dev_err(dev, "Couldn't get the DSI mod clock\n");
> > +                     return PTR_ERR(dsi->mod_clk);
> > +             }
> >       }
> >
> >       /*
> >        * In order to operate properly, that clock seems to be always
> >        * set to 297MHz.
> >        */
> > -     clk_set_rate_exclusive(dsi->mod_clk, 297000000);
> > +     if (dsi->variant->has_mod_clk)
> > +             clk_set_rate_exclusive(dsi->mod_clk, 297000000);
> >
> >       dphy_node = of_parse_phandle(dev->of_node, "phys", 0);
> >       ret = sun6i_dphy_probe(dsi, dphy_node);
> > @@ -1043,7 +1049,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
> >       pm_runtime_disable(dev);
> >       sun6i_dphy_remove(dsi);
> >  err_unprotect_clk:
> > -     clk_rate_exclusive_put(dsi->mod_clk);
> > +     if (dsi->variant->has_mod_clk)
> > +             clk_rate_exclusive_put(dsi->mod_clk);
> >       return ret;
> >  }
> >
> > @@ -1056,7 +1063,8 @@ static int sun6i_dsi_remove(struct platform_device *pdev)
> >       mipi_dsi_host_unregister(&dsi->host);
> >       pm_runtime_disable(dev);
> >       sun6i_dphy_remove(dsi);
> > -     clk_rate_exclusive_put(dsi->mod_clk);
> > +     if (dsi->variant->has_mod_clk)
> > +             clk_rate_exclusive_put(dsi->mod_clk);
> >
> >       return 0;
> >  }
> > @@ -1066,7 +1074,8 @@ static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
> >       struct sun6i_dsi *dsi = dev_get_drvdata(dev);
> >
> >       reset_control_deassert(dsi->reset);
> > -     clk_prepare_enable(dsi->mod_clk);
> > +     if (dsi->variant->has_mod_clk)
> > +             clk_prepare_enable(dsi->mod_clk);
> >
> >       /*
> >        * Enable the DSI block.
> > @@ -1094,7 +1103,8 @@ static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
> >  {
> >       struct sun6i_dsi *dsi = dev_get_drvdata(dev);
> >
> > -     clk_disable_unprepare(dsi->mod_clk);
> > +     if (dsi->variant->has_mod_clk)
> > +             clk_disable_unprepare(dsi->mod_clk);
> >       reset_control_assert(dsi->reset);
> >
> >       return 0;
> > @@ -1106,9 +1116,24 @@ static const struct dev_pm_ops sun6i_dsi_pm_ops = {
> >                          NULL)
> >  };
> >
> > +static const struct sun6i_dsi_variant sun6i_a31_dsi = {
> > +     .has_mod_clk = true,
> > +};
> > +
> > +static const struct sun6i_dsi_variant sun50i_a64_dsi = {
> > +     .has_mod_clk = false,
>
> This is the default already.

True but we need to assign the .data. how about checking device
compatible? I'm thinking of difference in driver data in future
between SoC's

>
> > +};
> > +
> >  static const struct of_device_id sun6i_dsi_of_table[] = {
> > -     { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
> > -     { }
> > +     {
> > +             .compatible = "allwinner,sun6i-a31-mipi-dsi",
> > +             .data = &sun6i_a31_dsi,
> > +     },
> > +     {
> > +             .compatible = "allwinner,sun50i-a64-mipi-dsi",
> > +             .data = &sun50i_a64_dsi,
> > +     },
> > +     { /* sentinel */ }
> >  };
> >  MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> > index dbbc5b3ecbda..597b62227019 100644
> > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> > @@ -20,6 +20,10 @@ struct sun6i_dphy {
> >       struct reset_control    *reset;
> >  };
> >
> > +struct sun6i_dsi_variant {
> > +     bool                    has_mod_clk;
> > +};
> > +
>
> This should be part of a separate patch.

How come, because has_mod_clk is using in driver file?

Re: [PATCH v2 13/15] dt-bindings: sun6i-dsi: Add compatible for A64 DPHY

[Jagan Teki]

On Wed, Oct 24, 2018 at 11:39 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> On Tue, Oct 23, 2018 at 09:20:33PM +0530, Jagan Teki wrote:
> > The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
> > on the one on A31.
> >
> > Add A64 compatible and append A31 compatible as fallback.
> >
> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > ---
> > Changes for v2:
> > - new patch
> >
> >  Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > index 9fa6e7a758ad..704fb31962f2 100644
> > --- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > @@ -36,7 +36,7 @@ D-PHY
> >
> >  Required properties:
> >    - compatible: value must be one of:
> > -    * allwinner,sun6i-a31-mipi-dphy
> > +    * "allwinner,sun50i-a64-mipi-dphy", "allwinner,sun6i-a31-mipi-dphy"
>
> No. you need both. The A64 MIPI DPHY one needs to be always set with
> the A31 fallback, but the A31 is also usable on its own.

Why wouldn't be, because we don't have any difference dphy right?

Re: [PATCH v2 14/15] arm64: dts: allwinner: a64: Add DSI pipeline

[Jagan Teki]

On Wed, Oct 24, 2018 at 11:40 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> On Tue, Oct 23, 2018 at 09:20:34PM +0530, Jagan Teki wrote:
> > The A64 has a MIPI-DSI block which is similar to A31
> > without mod clock.
> >
> > So, add dsi node with A64 compatible, dphy node with
> > A31 compatible and finally connect dsi to tcon0 to
> > make proper DSI pipeline.
> >
> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > ---
> > Changes for v2:
> > - use A64 dphy compatible
> >
> >  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45 +++++++++++++++++++
> >  1 file changed, 45 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > index f3a66f888205..f82e6b165d57 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > @@ -320,6 +320,11 @@
> >                                       #address-cells = <1>;
> >                                       #size-cells = <0>;
> >                                       reg = <1>;
> > +
> > +                                     tcon0_out_dsi: endpoint@1 {
> > +                                             reg = <1>;
> > +                                             remote-endpoint = <&dsi_in_tcon0>;
>
> You need to set the allwinner,channel property there.

Are you referring to allwinner,tcon-channel = <1> ?

Re: [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI

[Jagan Teki]

On Wed, Oct 24, 2018 at 11:43 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> On Tue, Oct 23, 2018 at 09:20:32PM +0530, Jagan Teki wrote:
> > A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> > using minimum 500MHz can't release the clock and which
> > is not working.
> >
> > So use working minimum rate as 300MHz which is tested on
> > Bananapi DSI panel.
>
> I'm not quite sure what you mean by that. What do you mean by "500MHz
> can't release the clock"? Why would 300MHz work better then? Should be
> avoid reaching 500MHz if it's a frequency in the valid range?

PLL_MIPI can't be work with existing nkm where rate set to 270MHz
(from PLL_VIDEO)
/*** round rate call in ccu_nkm.c */
[    2.408356] round: rate = 118800000
[    2.408359] round: parent_rate = 158740688
[    2.408417] round: rate = 148500000
[    2.408420] round: parent_rate = 158740688
[    2.408439] round: rate = 178200000
[    2.408441] round: parent_rate = 158740688
[    2.408460] round: rate = 205615384
[    2.408462] round: parent_rate = 158740688
[    2.408481] round: rate = 237600000
[    2.408483] round: parent_rate = 158740688
[    2.408502] round: rate = 270000000
[    2.408504] round: parent_rate = 158740688
[    2.408523] round: rate = 118800000
[    2.408525] round: parent_rate = 158740560
[    2.408544] round: rate = 148500000
[    2.408546] round: parent_rate = 158740560
[    2.408565] round: rate = 178200000
[    2.408567] round: parent_rate = 158740560
[    2.408586] round: rate = 205615384
[    2.408588] round: parent_rate = 158740560
[    2.408607] round: rate = 237600000
[    2.408609] round: parent_rate = 158740560
[    2.408627] round: rate = 270000000
[    2.408630] round: parent_rate = 158740560
[    2.408648] round: rate = 270000000
[    2.408651] round: parent_rate = 158740640
[    2.408670] round: rate = 270000000
[    2.408672] round: parent_rate = 158740704

/** set rate call in ccu_nkm **/
[    2.408685] set: rate = 270000000
[    2.408688] set: parent_rate = 297000000

By using min and max rate as per A64 manual page 94 range of PLL can
be 500MHz~1.4GHz getting 1,2,1 nkm dividers which can't be work.
[    2.423589] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[    2.423643] ideal = 220000000, rounded = 0
[    2.423647] ideal = 275000000, rounded = 0
[    2.423651] ideal = 330000000, rounded = 0
[    2.423692] ideal = 385000000, rounded = 384000000
[    2.423732] ideal = 440000000, rounded = 440000000
[    2.423736] sun4i_dclk_round_rate: div = 8 rate = 55000000
[    2.423740] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[    2.423744] ideal = 220000000, rounded = 0
[    2.423748] ideal = 275000000, rounded = 0
[    2.423751] ideal = 330000000, rounded = 0
[    2.423791] ideal = 385000000, rounded = 384000000
[    2.423831] ideal = 440000000, rounded = 440000000
[    2.423834] sun4i_dclk_round_rate: div = 8 rate = 55000000
[    2.423957] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
[    2.423961] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
[    2.424378] ccu_nkm_set_rate: rate = 440000000, parent_rate = 220000000
[    2.424381] ccu_nkm_set_rate: _nkm.n = 1
[    2.424383] ccu_nkm_set_rate: _nkm.k = 2
[    2.424385] ccu_nkm_set_rate: _nkm.m = 1
[    2.424725] sun4i_dclk_set_rate div 8
[    2.424732] sun4i_dclk_recalc_rate: val = 8, rate = 55000000
[    2.561271] usb 3-1: new high-speed USB device number 2 using ehci-platform
[    2.718486] hub 3-1:1.0: USB hub found
[    2.718606] hub 3-1:1.0: 4 ports detected
[    3.437263] ------------[ cut here ]------------
[    3.437270] [CRTC:36:crtc-0] vblank wait timed out

So, lowering the min rate by 300MHz seems working with bounded nkm
dividers 5, 2, 9. Tested on two different panels.

[    2.415773] [drm] No driver support for vblank timestamp query.
[    2.424116] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[    2.424172] ideal = 220000000, rounded = 0
[    2.424176] ideal = 275000000, rounded = 0
[    2.424194] ccu_nkm_round_rate: rate = 330000000
[    2.424197] ideal = 330000000, rounded = 330000000
[    2.424201] sun4i_dclk_round_rate: div = 6 rate = 55000000
[    2.424205] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[    2.424209] ideal = 220000000, rounded = 0
[    2.424213] ideal = 275000000, rounded = 0
[    2.424230] ccu_nkm_round_rate: rate = 330000000
[    2.424233] ideal = 330000000, rounded = 330000000
[    2.424236] sun4i_dclk_round_rate: div = 6 rate = 55000000
[    2.424253] ccu_nkm_round_rate: rate = 330000000
[    2.424270] ccu_nkm_round_rate: rate = 330000000
[    2.424278] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
[    2.424281] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
[    2.424306] ccu_nkm_set_rate: rate = 330000000, parent_rate = 297000000
[    2.424309] ccu_nkm_set_rate: _nkm.n = 5
[    2.424311] ccu_nkm_set_rate: _nkm.k = 2
[    2.424313] ccu_nkm_set_rate: _nkm.m = 9
[    2.424661] sun4i_dclk_set_rate div 6
[    2.424668] sun4i_dclk_recalc_rate: val = 6, rate = 55000000

Note: BPI-M64-bsp is setting the rate directly to 180MHz with 297MHz
parent with resulting dividers as 1, 2, 5. ans we can't produce this
180MHz rate with dclk_round_rate and ccu_nkm.

Re: [PATCH v2 02/15] clk: sunxi-ng: Add check for minimal rate to NKM PLLs

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1978 bytes --]

On Thu, Oct 25, 2018 at 04:25:59PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:34 PM Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:22PM +0530, Jagan Teki wrote:
> > > Some NKM PLLs doesn't work well when their output clock rate is set below
> > > certain rate.
> > >
> > > So, add support for minimal rate for relevant PLLs.
> > >
> > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > ---
> > > Changes for v2:
> > > - new patch
> > >
> > >  drivers/clk/sunxi-ng/ccu_nkm.c | 7 +++++++
> > >  drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
> > >  2 files changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> > > index 841840e35e61..d17539dc88dd 100644
> > > --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> > > +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> > > @@ -125,6 +125,13 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> > >       if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> > >               rate *= nkm->fixed_post_div;
> > >
> > > +     if (rate < nkm->min_rate) {
> > > +             rate = nkm->min_rate;
> > > +             if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> > > +                     rate /= nkm->fixed_post_div;
> >
> > I'm not sure this is right. Is the post divider taken into account to
> > calculate the minimum, or is the minimum on the rate before the fixed
> > post divider.
> 
> Since we are returning from here, we need to take care post div which
> is actually doing at the end of round_rate.

That's not my point though. Does the rate needs to be superior to min
/ post_div, or min?

> >
> > How did you test this?
> 
> I've not used this on PLL_MIPI atleast, so I didn't test this.

If you've never tested this, why are you adding that code?

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[-- Attachment #2: signature.asc --]
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Re: [PATCH v2 04/15] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 6536 bytes --]

On Thu, Oct 25, 2018 at 04:32:06PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:36 PM Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:24PM +0530, Jagan Teki wrote:
> > > The MIPI DSI controller on Allwinner A64 is similar to
> > > Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
> > >
> > > So, alter has_mod_clk bool via driver data for respective
> > > SoC's compatible.
> > >
> > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > ---
> > > Changes for v2:
> > > - none
> > >
> > >  drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 47 ++++++++++++++++++++------
> > >  drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  5 +++
> > >  2 files changed, 41 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > index e3b34a345546..8e9c76febca2 100644
> > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
> > > @@ -10,6 +10,7 @@
> > >  #include <linux/component.h>
> > >  #include <linux/crc-ccitt.h>
> > >  #include <linux/of_address.h>
> > > +#include <linux/of_device.h>
> > >  #include <linux/pm_runtime.h>
> > >  #include <linux/regmap.h>
> > >  #include <linux/reset.h>
> > > @@ -981,6 +982,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
> > >       dsi->host.ops = &sun6i_dsi_host_ops;
> > >       dsi->host.dev = dev;
> > >
> > > +     dsi->variant = of_device_get_match_data(dev);
> > > +
> > >       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > >       base = devm_ioremap_resource(dev, res);
> > >       if (IS_ERR(base)) {
> > > @@ -1001,17 +1004,20 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
> > >               return PTR_ERR(dsi->reset);
> > >       }
> > >
> > > -     dsi->mod_clk = devm_clk_get(dev, "mod");
> > > -     if (IS_ERR(dsi->mod_clk)) {
> > > -             dev_err(dev, "Couldn't get the DSI mod clock\n");
> > > -             return PTR_ERR(dsi->mod_clk);
> > > +     if (dsi->variant->has_mod_clk) {
> > > +             dsi->mod_clk = devm_clk_get(dev, "mod");
> > > +             if (IS_ERR(dsi->mod_clk)) {
> > > +                     dev_err(dev, "Couldn't get the DSI mod clock\n");
> > > +                     return PTR_ERR(dsi->mod_clk);
> > > +             }
> > >       }
> > >
> > >       /*
> > >        * In order to operate properly, that clock seems to be always
> > >        * set to 297MHz.
> > >        */
> > > -     clk_set_rate_exclusive(dsi->mod_clk, 297000000);
> > > +     if (dsi->variant->has_mod_clk)
> > > +             clk_set_rate_exclusive(dsi->mod_clk, 297000000);
> > >
> > >       dphy_node = of_parse_phandle(dev->of_node, "phys", 0);
> > >       ret = sun6i_dphy_probe(dsi, dphy_node);
> > > @@ -1043,7 +1049,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
> > >       pm_runtime_disable(dev);
> > >       sun6i_dphy_remove(dsi);
> > >  err_unprotect_clk:
> > > -     clk_rate_exclusive_put(dsi->mod_clk);
> > > +     if (dsi->variant->has_mod_clk)
> > > +             clk_rate_exclusive_put(dsi->mod_clk);
> > >       return ret;
> > >  }
> > >
> > > @@ -1056,7 +1063,8 @@ static int sun6i_dsi_remove(struct platform_device *pdev)
> > >       mipi_dsi_host_unregister(&dsi->host);
> > >       pm_runtime_disable(dev);
> > >       sun6i_dphy_remove(dsi);
> > > -     clk_rate_exclusive_put(dsi->mod_clk);
> > > +     if (dsi->variant->has_mod_clk)
> > > +             clk_rate_exclusive_put(dsi->mod_clk);
> > >
> > >       return 0;
> > >  }
> > > @@ -1066,7 +1074,8 @@ static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
> > >       struct sun6i_dsi *dsi = dev_get_drvdata(dev);
> > >
> > >       reset_control_deassert(dsi->reset);
> > > -     clk_prepare_enable(dsi->mod_clk);
> > > +     if (dsi->variant->has_mod_clk)
> > > +             clk_prepare_enable(dsi->mod_clk);
> > >
> > >       /*
> > >        * Enable the DSI block.
> > > @@ -1094,7 +1103,8 @@ static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
> > >  {
> > >       struct sun6i_dsi *dsi = dev_get_drvdata(dev);
> > >
> > > -     clk_disable_unprepare(dsi->mod_clk);
> > > +     if (dsi->variant->has_mod_clk)
> > > +             clk_disable_unprepare(dsi->mod_clk);
> > >       reset_control_assert(dsi->reset);
> > >
> > >       return 0;
> > > @@ -1106,9 +1116,24 @@ static const struct dev_pm_ops sun6i_dsi_pm_ops = {
> > >                          NULL)
> > >  };
> > >
> > > +static const struct sun6i_dsi_variant sun6i_a31_dsi = {
> > > +     .has_mod_clk = true,
> > > +};
> > > +
> > > +static const struct sun6i_dsi_variant sun50i_a64_dsi = {
> > > +     .has_mod_clk = false,
> >
> > This is the default already.
> 
> True but we need to assign the .data. how about checking device
> compatible? I'm thinking of difference in driver data in future
> between SoC's

That's not my point. You'll need the structure, but has_mod_clk will
be initialised to false already, so you can drop the explicit
assignment.

> >
> > > +};
> > > +
> > >  static const struct of_device_id sun6i_dsi_of_table[] = {
> > > -     { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
> > > -     { }
> > > +     {
> > > +             .compatible = "allwinner,sun6i-a31-mipi-dsi",
> > > +             .data = &sun6i_a31_dsi,
> > > +     },
> > > +     {
> > > +             .compatible = "allwinner,sun50i-a64-mipi-dsi",
> > > +             .data = &sun50i_a64_dsi,
> > > +     },
> > > +     { /* sentinel */ }
> > >  };
> > >  MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
> > >
> > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> > > index dbbc5b3ecbda..597b62227019 100644
> > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> > > @@ -20,6 +20,10 @@ struct sun6i_dphy {
> > >       struct reset_control    *reset;
> > >  };
> > >
> > > +struct sun6i_dsi_variant {
> > > +     bool                    has_mod_clk;
> > > +};
> > > +
> >
> > This should be part of a separate patch.
> 
> How come, because has_mod_clk is using in driver file?

You're doing two things here: Adding a quirk structure, and adding
support for an SoC. This should be two patches.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 13/15] dt-bindings: sun6i-dsi: Add compatible for A64 DPHY

[Maxime Ripard]

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On Thu, Oct 25, 2018 at 06:22:51PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:39 PM Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:33PM +0530, Jagan Teki wrote:
> > > The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
> > > on the one on A31.
> > >
> > > Add A64 compatible and append A31 compatible as fallback.
> > >
> > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > ---
> > > Changes for v2:
> > > - new patch
> > >
> > >  Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > > index 9fa6e7a758ad..704fb31962f2 100644
> > > --- a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > > +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > > @@ -36,7 +36,7 @@ D-PHY
> > >
> > >  Required properties:
> > >    - compatible: value must be one of:
> > > -    * allwinner,sun6i-a31-mipi-dphy
> > > +    * "allwinner,sun50i-a64-mipi-dphy", "allwinner,sun6i-a31-mipi-dphy"
> >
> > No. you need both. The A64 MIPI DPHY one needs to be always set with
> > the A31 fallback, but the A31 is also usable on its own.
> 
> Why wouldn't be, because we don't have any difference dphy right?

That's not my point. You removed from the binding documentation that
allwinner,sun6i-a31-mipi-dphy was a valid option on its own. It's not
ok to do so.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 14/15] arm64: dts: allwinner: a64: Add DSI pipeline

[Maxime Ripard]

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On Thu, Oct 25, 2018 at 06:51:14PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:40 PM Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:34PM +0530, Jagan Teki wrote:
> > > The A64 has a MIPI-DSI block which is similar to A31
> > > without mod clock.
> > >
> > > So, add dsi node with A64 compatible, dphy node with
> > > A31 compatible and finally connect dsi to tcon0 to
> > > make proper DSI pipeline.
> > >
> > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > ---
> > > Changes for v2:
> > > - use A64 dphy compatible
> > >
> > >  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45 +++++++++++++++++++
> > >  1 file changed, 45 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > > index f3a66f888205..f82e6b165d57 100644
> > > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > > @@ -320,6 +320,11 @@
> > >                                       #address-cells = <1>;
> > >                                       #size-cells = <0>;
> > >                                       reg = <1>;
> > > +
> > > +                                     tcon0_out_dsi: endpoint@1 {
> > > +                                             reg = <1>;
> > > +                                             remote-endpoint = <&dsi_in_tcon0>;
> >
> > You need to set the allwinner,channel property there.
> 
> Are you referring to allwinner,tcon-channel = <1> ?

Yep

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI

[Maxime Ripard]

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On Thu, Oct 25, 2018 at 09:21:31PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:43 PM Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:32PM +0530, Jagan Teki wrote:
> > > A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> > > using minimum 500MHz can't release the clock and which
> > > is not working.
> > >
> > > So use working minimum rate as 300MHz which is tested on
> > > Bananapi DSI panel.
> >
> > I'm not quite sure what you mean by that. What do you mean by "500MHz
> > can't release the clock"? Why would 300MHz work better then? Should be
> > avoid reaching 500MHz if it's a frequency in the valid range?
> 
> PLL_MIPI can't be work with existing nkm where rate set to 270MHz
> (from PLL_VIDEO)
> /*** round rate call in ccu_nkm.c */
> [    2.408356] round: rate = 118800000
> [    2.408359] round: parent_rate = 158740688
> [    2.408417] round: rate = 148500000
> [    2.408420] round: parent_rate = 158740688
> [    2.408439] round: rate = 178200000
> [    2.408441] round: parent_rate = 158740688
> [    2.408460] round: rate = 205615384
> [    2.408462] round: parent_rate = 158740688
> [    2.408481] round: rate = 237600000
> [    2.408483] round: parent_rate = 158740688
> [    2.408502] round: rate = 270000000
> [    2.408504] round: parent_rate = 158740688
> [    2.408523] round: rate = 118800000
> [    2.408525] round: parent_rate = 158740560
> [    2.408544] round: rate = 148500000
> [    2.408546] round: parent_rate = 158740560
> [    2.408565] round: rate = 178200000
> [    2.408567] round: parent_rate = 158740560
> [    2.408586] round: rate = 205615384
> [    2.408588] round: parent_rate = 158740560
> [    2.408607] round: rate = 237600000
> [    2.408609] round: parent_rate = 158740560
> [    2.408627] round: rate = 270000000
> [    2.408630] round: parent_rate = 158740560
> [    2.408648] round: rate = 270000000
> [    2.408651] round: parent_rate = 158740640
> [    2.408670] round: rate = 270000000
> [    2.408672] round: parent_rate = 158740704
> 
> /** set rate call in ccu_nkm **/
> [    2.408685] set: rate = 270000000
> [    2.408688] set: parent_rate = 297000000
> 
> By using min and max rate as per A64 manual page 94 range of PLL can
> be 500MHz~1.4GHz getting 1,2,1 nkm dividers which can't be work.
> [    2.423589] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> [    2.423643] ideal = 220000000, rounded = 0
> [    2.423647] ideal = 275000000, rounded = 0
> [    2.423651] ideal = 330000000, rounded = 0
> [    2.423692] ideal = 385000000, rounded = 384000000
> [    2.423732] ideal = 440000000, rounded = 440000000
> [    2.423736] sun4i_dclk_round_rate: div = 8 rate = 55000000
> [    2.423740] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> [    2.423744] ideal = 220000000, rounded = 0
> [    2.423748] ideal = 275000000, rounded = 0
> [    2.423751] ideal = 330000000, rounded = 0
> [    2.423791] ideal = 385000000, rounded = 384000000
> [    2.423831] ideal = 440000000, rounded = 440000000
> [    2.423834] sun4i_dclk_round_rate: div = 8 rate = 55000000
> [    2.423957] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
> [    2.423961] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
> [    2.424378] ccu_nkm_set_rate: rate = 440000000, parent_rate = 220000000
> [    2.424381] ccu_nkm_set_rate: _nkm.n = 1
> [    2.424383] ccu_nkm_set_rate: _nkm.k = 2
> [    2.424385] ccu_nkm_set_rate: _nkm.m = 1
> [    2.424725] sun4i_dclk_set_rate div 8
> [    2.424732] sun4i_dclk_recalc_rate: val = 8, rate = 55000000
> [    2.561271] usb 3-1: new high-speed USB device number 2 using ehci-platform
> [    2.718486] hub 3-1:1.0: USB hub found
> [    2.718606] hub 3-1:1.0: 4 ports detected
> [    3.437263] ------------[ cut here ]------------
> [    3.437270] [CRTC:36:crtc-0] vblank wait timed out
> 
> So, lowering the min rate by 300MHz seems working with bounded nkm
> dividers 5, 2, 9. Tested on two different panels.
> 
> [    2.415773] [drm] No driver support for vblank timestamp query.
> [    2.424116] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> [    2.424172] ideal = 220000000, rounded = 0
> [    2.424176] ideal = 275000000, rounded = 0
> [    2.424194] ccu_nkm_round_rate: rate = 330000000
> [    2.424197] ideal = 330000000, rounded = 330000000
> [    2.424201] sun4i_dclk_round_rate: div = 6 rate = 55000000
> [    2.424205] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> [    2.424209] ideal = 220000000, rounded = 0
> [    2.424213] ideal = 275000000, rounded = 0
> [    2.424230] ccu_nkm_round_rate: rate = 330000000
> [    2.424233] ideal = 330000000, rounded = 330000000
> [    2.424236] sun4i_dclk_round_rate: div = 6 rate = 55000000
> [    2.424253] ccu_nkm_round_rate: rate = 330000000
> [    2.424270] ccu_nkm_round_rate: rate = 330000000
> [    2.424278] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
> [    2.424281] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
> [    2.424306] ccu_nkm_set_rate: rate = 330000000, parent_rate = 297000000
> [    2.424309] ccu_nkm_set_rate: _nkm.n = 5
> [    2.424311] ccu_nkm_set_rate: _nkm.k = 2
> [    2.424313] ccu_nkm_set_rate: _nkm.m = 9
> [    2.424661] sun4i_dclk_set_rate div 6
> [    2.424668] sun4i_dclk_recalc_rate: val = 6, rate = 55000000
> 
> Note: BPI-M64-bsp is setting the rate directly to 180MHz with 297MHz
> parent with resulting dividers as 1, 2, 5. ans we can't produce this
> 180MHz rate with dclk_round_rate and ccu_nkm.

I'm still not quite sure what you mean by "500MHz can't release the
clock".

From what you're saying, this seems to be related to the boundaries of
the dividers rather than the rate itself.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [linux-sunxi] Re: [PATCH v2 02/15] clk: sunxi-ng: Add check for minimal rate to NKM PLLs

[Jagan Teki]

On 29/10/18 2:28 PM, Maxime Ripard wrote:
> On Thu, Oct 25, 2018 at 04:25:59PM +0530, Jagan Teki wrote:
>> On Wed, Oct 24, 2018 at 11:34 PM Maxime Ripard
>> <maxime.ripard@bootlin.com> wrote:
>>>
>>> On Tue, Oct 23, 2018 at 09:20:22PM +0530, Jagan Teki wrote:
>>>> Some NKM PLLs doesn't work well when their output clock rate is set below
>>>> certain rate.
>>>>
>>>> So, add support for minimal rate for relevant PLLs.
>>>>
>>>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>>>> ---
>>>> Changes for v2:
>>>> - new patch
>>>>
>>>>   drivers/clk/sunxi-ng/ccu_nkm.c | 7 +++++++
>>>>   drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
>>>>   2 files changed, 8 insertions(+)
>>>>
>>>> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
>>>> index 841840e35e61..d17539dc88dd 100644
>>>> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
>>>> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
>>>> @@ -125,6 +125,13 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>>>>        if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
>>>>                rate *= nkm->fixed_post_div;
>>>>
>>>> +     if (rate < nkm->min_rate) {
>>>> +             rate = nkm->min_rate;
>>>> +             if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
>>>> +                     rate /= nkm->fixed_post_div;
>>>
>>> I'm not sure this is right. Is the post divider taken into account to
>>> calculate the minimum, or is the minimum on the rate before the fixed
>>> post divider.
>>
>> Since we are returning from here, we need to take care post div which
>> is actually doing at the end of round_rate.
> 
> That's not my point though. Does the rate needs to be superior to min
> / post_div, or min?

ie what I'm trying to say, since it's common code min or max should / 
post_div and PLL_MIPI doesn't use any post_div.

We need to take care post_div though the current test (PLL_MIPI) in not 
used since it's common code. just like nkmp, nm etc.

> 
>>>
>>> How did you test this?
>>
>> I've not used this on PLL_MIPI atleast, so I didn't test this.
> 
> If you've never tested this, why are you adding that code?

Like above, it's common code. otherwise might effect.

Re: [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI

[Jagan Teki]

On Mon, Oct 29, 2018 at 2:39 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Thu, Oct 25, 2018 at 09:21:31PM +0530, Jagan Teki wrote:
> > On Wed, Oct 24, 2018 at 11:43 PM Maxime Ripard
> > <maxime.ripard@bootlin.com> wrote:
> > >
> > > On Tue, Oct 23, 2018 at 09:20:32PM +0530, Jagan Teki wrote:
> > > > A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> > > > using minimum 500MHz can't release the clock and which
> > > > is not working.
> > > >
> > > > So use working minimum rate as 300MHz which is tested on
> > > > Bananapi DSI panel.
> > >
> > > I'm not quite sure what you mean by that. What do you mean by "500MHz
> > > can't release the clock"? Why would 300MHz work better then? Should be
> > > avoid reaching 500MHz if it's a frequency in the valid range?
> >
> > PLL_MIPI can't be work with existing nkm where rate set to 270MHz
> > (from PLL_VIDEO)
> > /*** round rate call in ccu_nkm.c */
> > [    2.408356] round: rate = 118800000
> > [    2.408359] round: parent_rate = 158740688
> > [    2.408417] round: rate = 148500000
> > [    2.408420] round: parent_rate = 158740688
> > [    2.408439] round: rate = 178200000
> > [    2.408441] round: parent_rate = 158740688
> > [    2.408460] round: rate = 205615384
> > [    2.408462] round: parent_rate = 158740688
> > [    2.408481] round: rate = 237600000
> > [    2.408483] round: parent_rate = 158740688
> > [    2.408502] round: rate = 270000000
> > [    2.408504] round: parent_rate = 158740688
> > [    2.408523] round: rate = 118800000
> > [    2.408525] round: parent_rate = 158740560
> > [    2.408544] round: rate = 148500000
> > [    2.408546] round: parent_rate = 158740560
> > [    2.408565] round: rate = 178200000
> > [    2.408567] round: parent_rate = 158740560
> > [    2.408586] round: rate = 205615384
> > [    2.408588] round: parent_rate = 158740560
> > [    2.408607] round: rate = 237600000
> > [    2.408609] round: parent_rate = 158740560
> > [    2.408627] round: rate = 270000000
> > [    2.408630] round: parent_rate = 158740560
> > [    2.408648] round: rate = 270000000
> > [    2.408651] round: parent_rate = 158740640
> > [    2.408670] round: rate = 270000000
> > [    2.408672] round: parent_rate = 158740704
> >
> > /** set rate call in ccu_nkm **/
> > [    2.408685] set: rate = 270000000
> > [    2.408688] set: parent_rate = 297000000
> >
> > By using min and max rate as per A64 manual page 94 range of PLL can
> > be 500MHz~1.4GHz getting 1,2,1 nkm dividers which can't be work.
> > [    2.423589] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> > [    2.423643] ideal = 220000000, rounded = 0
> > [    2.423647] ideal = 275000000, rounded = 0
> > [    2.423651] ideal = 330000000, rounded = 0
> > [    2.423692] ideal = 385000000, rounded = 384000000
> > [    2.423732] ideal = 440000000, rounded = 440000000
> > [    2.423736] sun4i_dclk_round_rate: div = 8 rate = 55000000
> > [    2.423740] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> > [    2.423744] ideal = 220000000, rounded = 0
> > [    2.423748] ideal = 275000000, rounded = 0
> > [    2.423751] ideal = 330000000, rounded = 0
> > [    2.423791] ideal = 385000000, rounded = 384000000
> > [    2.423831] ideal = 440000000, rounded = 440000000
> > [    2.423834] sun4i_dclk_round_rate: div = 8 rate = 55000000
> > [    2.423957] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
> > [    2.423961] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
> > [    2.424378] ccu_nkm_set_rate: rate = 440000000, parent_rate = 220000000
> > [    2.424381] ccu_nkm_set_rate: _nkm.n = 1
> > [    2.424383] ccu_nkm_set_rate: _nkm.k = 2
> > [    2.424385] ccu_nkm_set_rate: _nkm.m = 1
> > [    2.424725] sun4i_dclk_set_rate div 8
> > [    2.424732] sun4i_dclk_recalc_rate: val = 8, rate = 55000000
> > [    2.561271] usb 3-1: new high-speed USB device number 2 using ehci-platform
> > [    2.718486] hub 3-1:1.0: USB hub found
> > [    2.718606] hub 3-1:1.0: 4 ports detected
> > [    3.437263] ------------[ cut here ]------------
> > [    3.437270] [CRTC:36:crtc-0] vblank wait timed out
> >
> > So, lowering the min rate by 300MHz seems working with bounded nkm
> > dividers 5, 2, 9. Tested on two different panels.
> >
> > [    2.415773] [drm] No driver support for vblank timestamp query.
> > [    2.424116] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> > [    2.424172] ideal = 220000000, rounded = 0
> > [    2.424176] ideal = 275000000, rounded = 0
> > [    2.424194] ccu_nkm_round_rate: rate = 330000000
> > [    2.424197] ideal = 330000000, rounded = 330000000
> > [    2.424201] sun4i_dclk_round_rate: div = 6 rate = 55000000
> > [    2.424205] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> > [    2.424209] ideal = 220000000, rounded = 0
> > [    2.424213] ideal = 275000000, rounded = 0
> > [    2.424230] ccu_nkm_round_rate: rate = 330000000
> > [    2.424233] ideal = 330000000, rounded = 330000000
> > [    2.424236] sun4i_dclk_round_rate: div = 6 rate = 55000000
> > [    2.424253] ccu_nkm_round_rate: rate = 330000000
> > [    2.424270] ccu_nkm_round_rate: rate = 330000000
> > [    2.424278] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
> > [    2.424281] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
> > [    2.424306] ccu_nkm_set_rate: rate = 330000000, parent_rate = 297000000
> > [    2.424309] ccu_nkm_set_rate: _nkm.n = 5
> > [    2.424311] ccu_nkm_set_rate: _nkm.k = 2
> > [    2.424313] ccu_nkm_set_rate: _nkm.m = 9
> > [    2.424661] sun4i_dclk_set_rate div 6
> > [    2.424668] sun4i_dclk_recalc_rate: val = 6, rate = 55000000
> >
> > Note: BPI-M64-bsp is setting the rate directly to 180MHz with 297MHz
> > parent with resulting dividers as 1, 2, 5. ans we can't produce this
> > 180MHz rate with dclk_round_rate and ccu_nkm.
>
> I'm still not quite sure what you mean by "500MHz can't release the
> clock".
>
> From what you're saying, this seems to be related to the boundaries of
> the dividers rather than the rate itself.

Yes, with 500MHz rate the boundaries of the dividers never release
hence it hangs during set_rate and finally after sometime it trigger
vblank timeout. can't release here means the same, may be I would
confused, sorry for that.

Re: [linux-sunxi] Re: [PATCH v2 02/15] clk: sunxi-ng: Add check for minimal rate to NKM PLLs

[Maxime Ripard]

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On Mon, Oct 29, 2018 at 06:10:47PM +0530, Jagan Teki wrote:
> On 29/10/18 2:28 PM, Maxime Ripard wrote:
> > On Thu, Oct 25, 2018 at 04:25:59PM +0530, Jagan Teki wrote:
> > > On Wed, Oct 24, 2018 at 11:34 PM Maxime Ripard
> > > <maxime.ripard@bootlin.com> wrote:
> > > > 
> > > > On Tue, Oct 23, 2018 at 09:20:22PM +0530, Jagan Teki wrote:
> > > > > Some NKM PLLs doesn't work well when their output clock rate is set below
> > > > > certain rate.
> > > > > 
> > > > > So, add support for minimal rate for relevant PLLs.
> > > > > 
> > > > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > > > ---
> > > > > Changes for v2:
> > > > > - new patch
> > > > > 
> > > > >   drivers/clk/sunxi-ng/ccu_nkm.c | 7 +++++++
> > > > >   drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
> > > > >   2 files changed, 8 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> > > > > index 841840e35e61..d17539dc88dd 100644
> > > > > --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> > > > > +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> > > > > @@ -125,6 +125,13 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> > > > >        if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> > > > >                rate *= nkm->fixed_post_div;
> > > > > 
> > > > > +     if (rate < nkm->min_rate) {
> > > > > +             rate = nkm->min_rate;
> > > > > +             if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
> > > > > +                     rate /= nkm->fixed_post_div;
> > > > 
> > > > I'm not sure this is right. Is the post divider taken into account to
> > > > calculate the minimum, or is the minimum on the rate before the fixed
> > > > post divider.
> > > 
> > > Since we are returning from here, we need to take care post div which
> > > is actually doing at the end of round_rate.
> > 
> > That's not my point though. Does the rate needs to be superior to min
> > / post_div, or min?
> 
> ie what I'm trying to say, since it's common code min or max should /
> post_div and PLL_MIPI doesn't use any post_div.
> 
> We need to take care post_div though the current test (PLL_MIPI) in not used
> since it's common code. just like nkmp, nm etc.
> 
> > 
> > > > 
> > > > How did you test this?
> > > 
> > > I've not used this on PLL_MIPI atleast, so I didn't test this.
> > 
> > If you've never tested this, why are you adding that code?
> 
> Like above, it's common code. otherwise might effect.

Adding untested, unverified and unneeded code is just bloat, nothing
else.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Re: [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI

[Maxime Ripard]

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On Mon, Oct 29, 2018 at 08:38:14PM +0530, Jagan Teki wrote:
> On Mon, Oct 29, 2018 at 2:39 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Thu, Oct 25, 2018 at 09:21:31PM +0530, Jagan Teki wrote:
> > > On Wed, Oct 24, 2018 at 11:43 PM Maxime Ripard
> > > <maxime.ripard@bootlin.com> wrote:
> > > >
> > > > On Tue, Oct 23, 2018 at 09:20:32PM +0530, Jagan Teki wrote:
> > > > > A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> > > > > using minimum 500MHz can't release the clock and which
> > > > > is not working.
> > > > >
> > > > > So use working minimum rate as 300MHz which is tested on
> > > > > Bananapi DSI panel.
> > > >
> > > > I'm not quite sure what you mean by that. What do you mean by "500MHz
> > > > can't release the clock"? Why would 300MHz work better then? Should be
> > > > avoid reaching 500MHz if it's a frequency in the valid range?
> > >
> > > PLL_MIPI can't be work with existing nkm where rate set to 270MHz
> > > (from PLL_VIDEO)
> > > /*** round rate call in ccu_nkm.c */
> > > [    2.408356] round: rate = 118800000
> > > [    2.408359] round: parent_rate = 158740688
> > > [    2.408417] round: rate = 148500000
> > > [    2.408420] round: parent_rate = 158740688
> > > [    2.408439] round: rate = 178200000
> > > [    2.408441] round: parent_rate = 158740688
> > > [    2.408460] round: rate = 205615384
> > > [    2.408462] round: parent_rate = 158740688
> > > [    2.408481] round: rate = 237600000
> > > [    2.408483] round: parent_rate = 158740688
> > > [    2.408502] round: rate = 270000000
> > > [    2.408504] round: parent_rate = 158740688
> > > [    2.408523] round: rate = 118800000
> > > [    2.408525] round: parent_rate = 158740560
> > > [    2.408544] round: rate = 148500000
> > > [    2.408546] round: parent_rate = 158740560
> > > [    2.408565] round: rate = 178200000
> > > [    2.408567] round: parent_rate = 158740560
> > > [    2.408586] round: rate = 205615384
> > > [    2.408588] round: parent_rate = 158740560
> > > [    2.408607] round: rate = 237600000
> > > [    2.408609] round: parent_rate = 158740560
> > > [    2.408627] round: rate = 270000000
> > > [    2.408630] round: parent_rate = 158740560
> > > [    2.408648] round: rate = 270000000
> > > [    2.408651] round: parent_rate = 158740640
> > > [    2.408670] round: rate = 270000000
> > > [    2.408672] round: parent_rate = 158740704
> > >
> > > /** set rate call in ccu_nkm **/
> > > [    2.408685] set: rate = 270000000
> > > [    2.408688] set: parent_rate = 297000000
> > >
> > > By using min and max rate as per A64 manual page 94 range of PLL can
> > > be 500MHz~1.4GHz getting 1,2,1 nkm dividers which can't be work.
> > > [    2.423589] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> > > [    2.423643] ideal = 220000000, rounded = 0
> > > [    2.423647] ideal = 275000000, rounded = 0
> > > [    2.423651] ideal = 330000000, rounded = 0
> > > [    2.423692] ideal = 385000000, rounded = 384000000
> > > [    2.423732] ideal = 440000000, rounded = 440000000
> > > [    2.423736] sun4i_dclk_round_rate: div = 8 rate = 55000000
> > > [    2.423740] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> > > [    2.423744] ideal = 220000000, rounded = 0
> > > [    2.423748] ideal = 275000000, rounded = 0
> > > [    2.423751] ideal = 330000000, rounded = 0
> > > [    2.423791] ideal = 385000000, rounded = 384000000
> > > [    2.423831] ideal = 440000000, rounded = 440000000
> > > [    2.423834] sun4i_dclk_round_rate: div = 8 rate = 55000000
> > > [    2.423957] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
> > > [    2.423961] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
> > > [    2.424378] ccu_nkm_set_rate: rate = 440000000, parent_rate = 220000000
> > > [    2.424381] ccu_nkm_set_rate: _nkm.n = 1
> > > [    2.424383] ccu_nkm_set_rate: _nkm.k = 2
> > > [    2.424385] ccu_nkm_set_rate: _nkm.m = 1
> > > [    2.424725] sun4i_dclk_set_rate div 8
> > > [    2.424732] sun4i_dclk_recalc_rate: val = 8, rate = 55000000
> > > [    2.561271] usb 3-1: new high-speed USB device number 2 using ehci-platform
> > > [    2.718486] hub 3-1:1.0: USB hub found
> > > [    2.718606] hub 3-1:1.0: 4 ports detected
> > > [    3.437263] ------------[ cut here ]------------
> > > [    3.437270] [CRTC:36:crtc-0] vblank wait timed out
> > >
> > > So, lowering the min rate by 300MHz seems working with bounded nkm
> > > dividers 5, 2, 9. Tested on two different panels.
> > >
> > > [    2.415773] [drm] No driver support for vblank timestamp query.
> > > [    2.424116] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> > > [    2.424172] ideal = 220000000, rounded = 0
> > > [    2.424176] ideal = 275000000, rounded = 0
> > > [    2.424194] ccu_nkm_round_rate: rate = 330000000
> > > [    2.424197] ideal = 330000000, rounded = 330000000
> > > [    2.424201] sun4i_dclk_round_rate: div = 6 rate = 55000000
> > > [    2.424205] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
> > > [    2.424209] ideal = 220000000, rounded = 0
> > > [    2.424213] ideal = 275000000, rounded = 0
> > > [    2.424230] ccu_nkm_round_rate: rate = 330000000
> > > [    2.424233] ideal = 330000000, rounded = 330000000
> > > [    2.424236] sun4i_dclk_round_rate: div = 6 rate = 55000000
> > > [    2.424253] ccu_nkm_round_rate: rate = 330000000
> > > [    2.424270] ccu_nkm_round_rate: rate = 330000000
> > > [    2.424278] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
> > > [    2.424281] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
> > > [    2.424306] ccu_nkm_set_rate: rate = 330000000, parent_rate = 297000000
> > > [    2.424309] ccu_nkm_set_rate: _nkm.n = 5
> > > [    2.424311] ccu_nkm_set_rate: _nkm.k = 2
> > > [    2.424313] ccu_nkm_set_rate: _nkm.m = 9
> > > [    2.424661] sun4i_dclk_set_rate div 6
> > > [    2.424668] sun4i_dclk_recalc_rate: val = 6, rate = 55000000
> > >
> > > Note: BPI-M64-bsp is setting the rate directly to 180MHz with 297MHz
> > > parent with resulting dividers as 1, 2, 5. ans we can't produce this
> > > 180MHz rate with dclk_round_rate and ccu_nkm.
> >
> > I'm still not quite sure what you mean by "500MHz can't release the
> > clock".
> >
> > From what you're saying, this seems to be related to the boundaries of
> > the dividers rather than the rate itself.
> 
> Yes, with 500MHz rate the boundaries of the dividers never release
> hence it hangs during set_rate and finally after sometime it trigger
> vblank timeout. can't release here means the same, may be I would
> confused, sorry for that.

I'm sorry, but I still don't get what you mean by release here.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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