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[2003:dc:d707:2200:6919:79d1:fb98:407]) by smtp.googlemail.com with ESMTPSA id u10-v6sm13759388wrt.59.2018.10.28.05.55.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 28 Oct 2018 05:55:15 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-arm-kernel@lists.infradead.org, khilman@baylibre.com, carlo@caione.org, Martin Blumenstingl Subject: [PATCH 2/2] clocksource: meson6_timer: implement ARM delay timer Date: Sun, 28 Oct 2018 13:55:01 +0100 Message-Id: <20181028125501.17336-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181028125501.17336-1-martin.blumenstingl@googlemail.com> References: <20181028125501.17336-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement an ARM delay timer to be used for udelay(). This allows us to skip the delay loop calibration at boot. With this patch udelay() is now independent of CPU frequency changes. This is a good thing on Meson8, Meson8b and Meson8m2 because changing the CPU frequency requires running the CPU clock off the XTAL while changing the PLL or it's dividers. After changing the CPU clocks we need to wait a few usecs for the clock to become stable. So having an udelay() implementation that doesn't depend on the CPU frequency is beneficial. Suggested-by: Jianxin Pan Signed-off-by: Martin Blumenstingl --- drivers/clocksource/meson6_timer.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c index c622135bee9d..5ee2a575069b 100644 --- a/drivers/clocksource/meson6_timer.c +++ b/drivers/clocksource/meson6_timer.c @@ -22,6 +22,10 @@ #include #include +#ifdef CONFIG_ARM +#include +#endif + enum meson6_timera_input_clock { MESON_TIMERA_CLOCK_1US = 0x0, MESON_TIMERA_CLOCK_10US = 0x1, @@ -60,6 +64,18 @@ enum meson6_timere_input_clock { static void __iomem *timer_base; +#ifdef CONFIG_ARM +static unsigned long meson6_read_current_timer(void) +{ + return readl_relaxed(timer_base + MESON_ISA_TIMERE); +} + +static struct delay_timer meson6_delay_timer = { + .read_current_timer = meson6_read_current_timer, + .freq = 1000 * 1000, +}; +#endif + static u64 notrace meson6_timer_sched_read(void) { return (u64)readl(timer_base + MESON_ISA_TIMERE); @@ -198,6 +214,12 @@ static int __init meson6_timer_init(struct device_node *node) clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC, 1, 0xfffe); + +#ifdef CONFIG_ARM + /* Also use MESON_ISA_TIMERE for delays */ + register_current_timer_delay(&meson6_delay_timer); +#endif + return 0; } TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer", -- 2.19.1