From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4216AC2BC61 for ; Mon, 29 Oct 2018 07:26:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 062FC2080A for ; Mon, 29 Oct 2018 07:26:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="d5nxVtX8" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 062FC2080A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=alliedtelesis.co.nz Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729454AbeJ2QN2 (ORCPT ); Mon, 29 Oct 2018 12:13:28 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:51836 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729422AbeJ2QN1 (ORCPT ); Mon, 29 Oct 2018 12:13:27 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 437E2886D4; Mon, 29 Oct 2018 20:25:54 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1540797954; bh=kYBflEaqCViIATbPoUT7Qcmh1CYF3yDA8Hzlo/yMh20=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=d5nxVtX8vVm8MfbTAXvC5Ak8GAGGh2BPuC9EwkzkmSinYBVc0K3xnYY5BHg3xgTIz BmoS9envkc60RBbKOlyTkwJGyUNCnIVqNvpijLrV+kG3pVr8ZuAo+UtJTa8XTIpJH0 bZHUcehIuufju6fof2A7C+SgF0X5jjS179EdIDXMyCi64Xn9zmEO8Bh/uEalS51QWJ ljvFZWsLs6vNhODzxFyUC+BL/ZqH5VxWdLmeOYZRuPzPEHYerz1Gkrn5KvxNW0frk2 Mx9KW8050buSqlB6uj5BlTocj/kZW73e8VzKMXuAHDk6B2JNUHn0wCHCdLnbchLn87 yjHEa5BCnuMKg== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Mon, 29 Oct 2018 20:25:54 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 79A0513EFB8; Mon, 29 Oct 2018 20:25:53 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A04E91E21FF; Mon, 29 Oct 2018 20:25:48 +1300 (NZDT) From: Chris Packham To: linux@armlinux.org.uk Cc: u.kleine-koenig@pengutronix.de, jlu@pengutronix.de, bp@alien8.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v5 3/8] ARM: aurora-l2: add defines for parity and ECC registers Date: Mon, 29 Oct 2018 20:25:30 +1300 Message-Id: <20181029072535.31667-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> References: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable x-atlnz-ls: pat Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jan Luebbe These defines will be used by subsequent patches to add support for the parity check and error correction functionality in the Aurora L2 cache controller. Signed-off-by: Jan Luebbe Signed-off-by: Chris Packham --- =20.../include/asm/hardware/cache-aurora-l2.h | 48 +++++++++++++++++++= =201 file changed, 48 insertions(+) diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/i= nclude/asm/hardware/cache-aurora-l2.h index dc5c479ec4c3..39769ffa0051 100644 --- a/arch/arm/include/asm/hardware/cache-aurora-l2.h +++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h @@ -31,6 +31,9 @@ =20#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \ =20 (3 << AURORA_ACR_REPLACEMENT_OFFSET) =20 +#define AURORA_ACR_PARITY_EN (1 << 21) +#define AURORA_ACR_ECC_EN (1 << 20) + =20#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0 =20#define AURORA_ACR_FORCE_WRITE_POLICY_MASK \ =20 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) @@ -41,6 +44,51 @@ =20#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \ =20 (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) =20 +#define AURORA_ERR_CNT_REG 0x600 +#define AURORA_ERR_ATTR_CAP_REG 0x608 +#define AURORA_ERR_ADDR_CAP_REG 0x60c +#define AURORA_ERR_WAY_CAP_REG 0x610 +#define AURORA_ERR_INJECT_CTL_REG 0x614 +#define AURORA_ERR_INJECT_MASK_REG 0x618 + +#define AURORA_ERR_CNT_CLR_OFFSET 31 +#define AURORA_ERR_CNT_CLR \ + (0x1 << AURORA_ERR_CNT_CLR_OFFSET) +#define AURORA_ERR_CNT_UE_OFFSET 16 +#define AURORA_ERR_CNT_UE_MASK \ + (0x7fff << AURORA_ERR_CNT_UE_OFFSET) +#define AURORA_ERR_CNT_CE_OFFSET 0 +#define AURORA_ERR_CNT_CE_MASK \ + (0xffff << AURORA_ERR_CNT_CE_OFFSET) + +#define AURORA_ERR_ATTR_SRC_OFF 16 +#define AURORA_ERR_ATTR_SRC_MSK \ + (0x7 << AURORA_ERR_ATTR_SRC_OFF) +#define AURORA_ERR_ATTR_TXN_OFF 12 +#define AURORA_ERR_ATTR_TXN_MSK \ + (0xf << AURORA_ERR_ATTR_TXN_OFF) +#define AURORA_ERR_ATTR_ERR_OFF 8 +#define AURORA_ERR_ATTR_ERR_MSK \ + (0x3 << AURORA_ERR_ATTR_ERR_OFF) +#define AURORA_ERR_ATTR_CAP_VALID_OFF 0 +#define AURORA_ERR_ATTR_CAP_VALID \ + (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF) + +#define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0 + +#define AURORA_ERR_WAY_IDX_OFF 8 +#define AURORA_ERR_WAY_IDX_MSK \ + (0xfff << AURORA_ERR_WAY_IDX_OFF) +#define AURORA_ERR_WAY_CAP_WAY_OFFSET 1 +#define AURORA_ERR_WAY_CAP_WAY_MASK \ + (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET) + +#define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0 +#define AURORA_ERR_ATTR_TXN_OFF 12 +#define AURORA_ERR_INJECT_CTL_EN_MASK 0x3 +#define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2 +#define AURORA_ERR_INJECT_CTL_EN_ECC 0x1 + =20#define AURORA_MAX_RANGE_SIZE 1024 =20 =20#define AURORA_WAY_SIZE_SHIFT 2 --=20 2.19.1